APPARATUS FOR REMOTE FLASHING OF A BIOS MEMORY IN A DATA PROCESSING SYSTEM
A method and apparatus thereof for flashing a BIOS of a data processing system remotely are provided. A BIOS flash instruction is given remotely from a remote console, transmitted to a microprocessor and a corresponding storage media of the data processing system via network, where the microprocessor is irresponsible for operating system. A BIOS image file is identified correct before performing BIOS of a system microprocessor that is responsible for operating system, where the system microprocessor is usually CPU. BIOS is remotely flashed with this method and apparatus, and since flash operation is performed independently of the operating system of the data processing system, BIOS re-flash can be performed and data processing system can be rebooted even when flash operation is failed or operating system is disable.
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This application is a divisional of a prior application Ser. No. 10/907,341, filed Mar. 30, 2005, which claims the priority benefit of Taiwan application serial no. 93109435, filed on Apr. 6, 2004 and is pending. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.
BACKGROUND OF THE INVENTION1. Field of Invention
The present invention relates to a method for flashing of a BIOS memory in a data processing system, and more particularly, to a method for remote flashing of a BIOS memory that is complied with various of operating systems, and manages to re-flash with BIOS flash failed.
2. Description of the Related Art
Generally speaking, in order to flash a data processing system, for example, BIOS flash for a computer, the flashing operation has to be performed under normally running Operating System. In the case when the Power On Self Test (POST) is not successfully passed or the Operating System is not normally operated, remote BIOS flash is not feasible.
Referring to
Regarding hardware configuration of the prior art technology, referring to the block diagram illustrating BIOS flash operation BIOS as shown in
According to one aspect of the present invention, a method for remotely flashing BIOS is provided, wherein disability of remote BIOS re-flash caused by a BIOS flash failure is solved.
According to another aspect of the present invention, a method for flashing BIOS is provided, wherein a BIOS image file to be flashed provided remotely, bridged with a microprocessor yet not performed with the operating system thereof, manages to directly or indirectly perform BIOS flash and system reboot.
In accordance with the above aspects of the present invention, a data processing system is provided, for remotely flashing a rewritable memory. The data processing system includes a remote console, a first microprocessor module, a second microprocessor module, a network, and a network interface. Wherein, after transmitted through the network and converted by the network interface, the flashing instruction and the flashing content provided by the remote console are received and executed by the first microprocessor module which is connected to the network interface, and a subsequent process is performed to flash the rewritable memory. In the present invention, the rewritable memory, being rewritable BIOS memory of the CPU, for example, is disposed with the second microprocessor module. In such case, the rewritable BIOS memory can be directly flashed by the first microprocessor module without performance of the second microprocessor module. If the first microprocessor module does not serve to directly flash the rewritable BIOS memory function, an alternative method can be used to indirectly flash the rewritable memory via the BIOS boot block by connecting the second microprocessor module thereto. The first microprocessor module of the present invention includes a first microprocessor and a first register. Usually, the first microprocessor is a microprocessor other than the CPU of the computer, and the first register is a memory corresponding to the first microprocessor, e.g. a flash memory, a RAM, etc. In the present invention, a remote instruction and flashing content are received via the network for BIOS flash of the CPU, where the first microprocessor serves as a bridge along with the operation of the first register. Since the first microprocessor being responsible for performing memory flash and the second microprocessor and the second register thereof to be flashed are independent, the rewritable memory of the second microprocessor can be flashed either directly or indirectly by the first microprocessor, which is irrelevant to the operating system. Even memory flash fails, a flash instruction is able to be remotely re-performed via the first microprocessor by the remote console until the operating system resumes properly.
Furthermore, a direct method for flashing the rewritable memory of the second microprocessor without operation of the second microprocessor is provided as well in the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention provides a remote console that enables a system's BIOS to be flashed remotely, and more particularly, provides a method for re-flashing BIOS if BIOS flash ever fails. The failure to flash the BIOS properly could lead to a system failure. A BIOS image file to be flashed is provided remotely from the remote console of the BIOS flashing system, where a microprocessor serves as a bridge and bypasses the operation system, before BIOS is successfully flashed and the data processing system is successfully rebooted.
An indirect method for remotely flashing BIOS is provided in the present invention, where a microprocessor serves as a bridge. Since the microprocessor includes a data register, e.g. flash memory, RAM, etc., when a BIOS flash is instructed by a remote administrator, the microprocessor remotely flashes the BIOS thereof.
A direct method and an indirect method of remotely flashing BIOS are provided according to technology of the present invention. Wherein the direct method, the microprocessor and the rewritable memory of the system are coupled with an interface, where the microprocessor manages to flash the BIOS at arbitrary time. If the system is without the interface, an alternative indirect method mentioned above is triggered to flash the BIOS. According to the indirect method for flashing BIOS in the present invention, BIOS is flashed with the code embedded in the BOOT block thereof, thus BIOS is flashed before POST is terminated. Moreover, the code embedded in the BOOT block is non-versatile after the system is fabricated, the BOOT block is never vulnerable and re-flash of the BIOS is secured.
Referring to
In the present invention, when BIOS flash is to be remotely flashed by the system administrator, a BIOS flashing instruction is issued by a remote console to the microprocessor of the system, where BIOS is to be flashed remotely thereof. BIOS is flashed directly as the microprocessor receives the instruction (referring to
Referring to
Referring to
Although the invention has been described with reference to a particular embodiment thereof, it will be apparent to those skilled in the art that modifications to the described embodiment may be made without departing from the spirit of the invention. Accordingly, the scope of the invention will be defined by the attached claims and not by the above detailed description.
Claims
1. A data processing system apparatus, for performing a flash operation to a rewritable memory remotely, the data processing system apparatus comprising:
- a remote console;
- a network;
- a network interface;
- a first microprocessor;
- a first register;
- a second microprocessor; and
- a second register;
- wherein the first microprocessor serves as a bridge between the remote console and the network and the network interface, where an information transmitted from the remote console for the flash operation is stored in the first register, in order to flash the rewritable memory associated with the second microprocessor along with the second register.
2. The data processing system apparatus of claim 1, wherein the remote console comprises a remote data processing system.
3. The data processing system apparatus of claim 2, wherein the remote data processing system is selected at least one from a group of: a desktop computer, a laptop computer, and a server.
4. The data processing system apparatus of claim 1, wherein the network comprises an Ethernet.
5. The data processing system apparatus of claim 1, wherein the network comprises a Local Area Network (LAN).
6. The data processing system apparatus of claim 1, wherein the network interface comprises a Network Interface Card (NIC).
7. The data processing system apparatus of claim 1, wherein the first register comprises at least one of a flash memory and a Random Access Memory (RAM).
8. The data processing system apparatus of claim 1, wherein the first microprocessor comprises a Central Processing Unit (CPU).
9. The data processing system apparatus of claim 1, wherein the second register comprises at least one of a flash memory and a Random Access Memory (RAM).
10. The data processing system apparatus of claim 9, wherein the flash operation is performed by the first microprocessor via the second microprocessor along with the flash memory.
11. The data processing system apparatus of claim 9, wherein the flash operation is performed directly by the first microprocessor accessing the flash memory.
12. The data processing system apparatus of claim 1, wherein the rewritable memory comprises a Basic Input/Output System (BIOS) chip.
13. The data processing system apparatus of claim 12, wherein the rewritable memory comprises two programmable parts, where any one of the programmable parts comprises a copy of a code of the rewritable memory while the flash operation is performed on the rewritable memory, and only the programmable part that is unable is performed with the flash operation.
14. The data processing system apparatus of claim 12, wherein the rewritable memory comprises an EEPROM.
15. The data processing system apparatus of claim 1, wherein the data processing system is a computer system.
16. The data processing system apparatus of claim 1, wherein the data processing system is a computer network system.
17. A data processing system suitable for flashing a rewritable memory with a remote instruction, the system comprising:
- a remote console for providing the remote instruction and a flashing content;
- a first microprocessor module;
- a second microprocessor module, associated with the rewritable memory, coupled to the first microprocessor module;
- a network; and
- a network interface, coupled to the network and the second microprocessor module.
18. The data processing system of claim 17, wherein the first microprocessor module comprises:
- a first microprocessor, coupled to the network interface; and
- a first register, coupled to the first microprocessor.
19. The data processing system of claim 18, wherein the first register comprises at least one of a flash memory and a Random Access Memory (RAM).
20. The data processing system of claim 17, wherein an operating system booted by the second microprocessor module via the rewritable memory comprises:
- a second microprocessor, being coupled to the first microprocessor; and
- a second register, being coupled to the second microprocessor.
21. The data processing system of claim 17, wherein an operating system booted by the second microprocessor module via the rewritable memory comprises:
- a second microprocessor, coupled to the first microprocessor; and
- a second register, coupled to the first microprocessor and the second microprocessor.
22. The data processing system of claim 18, wherein the second register comprises at least one of a flash memory and a Random Access Memory (RAM).
23. The data processing system of claim 18, wherein the second microprocessor is a Central Processing Unit (CPU).
24. The data processing system of claim 17, wherein the remote console comprises a remote data processing system.
25. The data processing system of claim 17, wherein the network comprises an Ethernet.
26. The data processing system of claim 17, wherein the network comprises a Local Area Network (LAN).
27. The data processing system of claim 17, wherein the network interface comprises a Network Interface Card (NIC).
Type: Application
Filed: Mar 16, 2007
Publication Date: Jul 5, 2007
Applicant: WISTRON CORPORATION (Taipei Hsien)
Inventors: Sen-Ta Chan (Taipei Hsien), Yi-Hsun Chen (Taipei Hsien), Chao-Sheng Hsu (Taipei Hsien), Yi-Chang Wu (Taipei Hsien), Wen-Pin Huang (Taipei Hsien)
Application Number: 11/686,966
International Classification: G06F 15/177 (20060101);