SEALED THREE DIMENSIONAL METAL BONDED INTEGRATED CIRCUITS
The invention provides a sealing layer that seals metal bonding structures between three dimensional bonded integrated circuits from a surrounding environment. A material may be applied to fill a volume between the bonded integrated circuits or seal the perimeter of the volume between the bonded integrated circuits. The material may be the same material as that used for underfilling the volume between the bottom integrated circuit and a substrate.
This U.S. patent application is a continuation of U.S. patent application Ser. No. 10/791,492 filed Mar. 1, 2004.
BACKGROUND OF THE INVENTIONIn three dimensional integrated circuits, there are microelectronic devices on more than one device layer. This allows three dimensional integrated circuits to have a higher device density and a smaller chip area than non-three dimensional integrated circuits.
To form a three dimensional integrated circuit, several semiconductor dies with microelectronic devices are fabricated at once on a first wafer. Several more semiconductor dies with microelectronic devices are fabricated at once on a second wafer. Conductors from dies on the first wafer are bonded to conductors from the dies on the second wafer to form the three dimensional bonded integrated circuits. The wafers are cut apart to result in a three dimensional bonded integrated circuits where a die from the first wafer is bonded to a die from the second wafer.
Alternatively, the wafers may be cut into dies prior to being bonded together. The first and second wafers may each be cut into dies. A die from the first wafer may then be bonded to a die from the second wafer to form a three dimensional bonded integrated circuit.
The resulting three dimensional metal bonded integrated circuits have conductors, usually copper, extending between the two integrated circuits. These conductors can have exposed surfaces between the two integrated circuits. These exposed surfaces may be affected by environmental factors. For example, the copper conductors may corrode and cause the device to fail.
BRIEF DESCRIPTION OF THE DRAWINGS
The assembly 100 may include a first die 104. The first die 104 may be an integrated circuit die and include one or more microelectronic devices, such as transistors or other devices. The first die 104 may be connected to the substrate 102 by a first set of conductive connection structures 106. These connection structures 106 may be, for example, controlled collapse chip connects (“C4”), solder ball bumps, or other connection structures 106, and they may connect the first die 104 to the substrate 102 electrically and/or structurally in some embodiments. There may be a distance 108 between a first surface 120 of the substrate 102 and a first surface 122 of the first die 104. This distance 108 may be in a range from about 75 to about 100 microns in some embodiments. There may be a volume 130 between the first die 104 and the substrate 102 and around the connection structures 106.
The assembly 100 may also include a second die 110. The second die 110 may be an integrated circuit die and include one or more microelectronic devices, such as transistors or other devices. The second die 110 may have a first surface 126.
The first die 104 may have several conductive structures 114. The second die 110 may also have several conductive structures 112. These structures 112, 114 may be made of a metal, such as copper, or another conductive material. The structures 114 of the first die 104 may extend beneath the second surface 124 of the first die 104 into the first die 104, and also extend above the second surface 124 of the first die 104. The structures 112 of the second die 110 may extend beneath the first surface 126 of the second die 110 into the second die 110, and also extend beyond the first surface 126 of the second die 110.
The conductive structures 114, 112 may be first and second sets, respectively, of portions of conductive connection structures 118 that may extend between and connect the first die 104 and the second die 110. In an embodiment, the conductive structures 114, 112 may comprise copper and be bonded together to connect the first die 104 and the second die 110. The conductive structures 114 of the first die 104 make up the first portions of conductive connection structures 118 and the conductive structures 112 of the second die 110 make up the second portions of conductive connection structures 118 that are formed once the conductive structures 114, 112 are bonded together. Together, each bonded pair of conductive structures 114, 112 comprise a conductive connection structure 118 that connects the first die 104 to the second die 110.
There may be a distance 116 between a second surface 124 of the first die 104 and the first surface 126 of the second die 110. This distance 116 may be in a range from about 100 to about 200 nanometers in some embodiments. There may be a volume 132 between the first die 104 and the second die 110 and around the bonded connection structures 114, 112. As is apparent from
In some embodiments, underfill material 134 that is used to fill the volume 130 between the first die 104 and the substrate 102 is also used to seal the volume 132 between the first and second dies 104, 110. The underfill material 134 thus also acts as a sealing layer. Enough underfill material 134 may be applied to the unsealed and not yet underfilled assembly 100 so that the material 134 fills the volume 130 between the first die 104 and the substrate 102 and also seals the volume 132 between the first and second dies 104, 110. This underfill material 134 that acts as a sealing layer may be applied at the same time as the underfill material 134 that acts as underfill between the substrate 102 and the first die 104. The underfill material 134 may be an epoxy or other material, and may comprise filler particles, such as glass filler particles, which may have a size of about one micron. In the embodiment shown in
In some embodiments, underfill material 134 that is used to fill the volume 130 between the first die 104 and the substrate 102 is also used to seal the volume 132 between the first and second dies 104, 110. Enough underfill material 134 may be applied so that the material 134 extends from the second surface 124 of the first die 104 to the first surface 126 of the second die 110 around the perimeters of the first and second dies 104, 110 to seal off the volume 132 between the first and second dies 104, 110 from the surrounding environment. The underfill material 134 thus acts as a sealing layer.
The underfill material 134 may be an epoxy or other material, and may comprise filler particles. In the embodiment shown in
The material may extend between the second surface 124 of the first die 104 and the first surface 126 of the second die 110 to seal the volume 132 without filling the volume 132, as shown in
A second wafer 304 may have multiple dies 312, 314 fabricated on it. The dies 312, 314 may be integrated circuit dies and each may include one or more microelectronic devices, such as transistors or other devices. The dies 312, 314 may also include portions of conductive connection structures 306. The portions of the conductive connection structures 306 of the dies 308, 310 of the first wafer 302 may be bonded to the portions of the conductive connection structures 306 of the dies 312, 314 of the second wafer 304 to form the three dimensional metal bonded wafer assembly 300.
The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms, such as left, right, top, bottom, over, under, upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. The embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.
Claims
1. A method, comprising:
- sealing a device, the device comprising: a substrate with a top surface; a first integrated circuit die above the substrate and spaced apart from the substrate by a first distance to form a first volume between the substrate and the first integrated circuit die, the first integrated circuit die having a bottom surface closer to the substrate and a top surface further from the substrate and a plurality of microelectronic devices; a first plurality of connectors extending from the top surface of the substrate to the bottom surface of the first integrated circuit die and forming an electrical connection between the substrate and the bottom surface of the first integrated circuit; a second integrated circuit die above the first integrated circuit die and spaced apart from the first integrated circuit die by a second distance to form a second volume between the first integrated circuit die and the second integrated circuit die, the second integrated circuit die having a bottom surface closer to the first integrated circuit die and a top surface further from the first integrated circuit die and a plurality of microelectronic devices; a second plurality of connectors extending from the top surface of the first integrated circuit die to the bottom surface of the second integrated circuit die;
- wherein sealing the device comprises substantially sealing the second volume between the first and second integrated circuit dies from a surrounding environment by applying a layer of underfill material extending from the substrate to the second integrated circuit die, wherein a portion of the second volume between the first integrated circuit die and the second integrated circuit die and the second volume around the second plurality of connectors is filled by the underfill material after sealing the device;
2. The method of claim 1, wherein formation of the device comprises:
- fabricating the first integrated circuit die, the fabricated first integrated circuit die having a first set of first portions of the second plurality of connectors;
- fabricating the second integrated circuit die, the fabricated second integrated circuit die having a second set of second portions of the second plurality of connectors;
- singulating the first integrated circuit die from a first wafer comprising a plurality of integrated circuit dies;
- singulating the second integrated circuit die from a second wafer comprising a plurality of integrated circuit dies; and
- bonding the first set of first portions to the second set of second portions to connect the first integrated circuit die to the second integrated circuit die.
3. The method of claim 2, wherein the device is sealed after the first and second integrated circuit dies have been singulated from the first and second wafers.
4. The method of claim 3, wherein the device is sealed by a layer of underfill material and the layer of underfill material comprises filler particles having an average diameter greater than the second distance between the first integrated circuit die and the second integrated circuit die.
5. The method of claim 3, wherein the first distance between the substrate and the first integrated circuit die is in a range from about 75 microns to about 100 microns, and the second distance between the first integrated circuit die and the second integrated circuit die is in a range from about 100 nanometers to about 200 nanometers.
6. The method of claim 3, wherein sealing the device comprises applying a layer of material extending from the first integrated circuit die to the second integrated circuit die.
7. The method of claim 1, wherein the device is sealed by a layer of underfill material and the layer of underfill material substantially fills the second volume between the first integrated circuit die and the second integrated circuit die and around the second plurality of connectors.
8. The method of claim 7, wherein sealing the device occurs after the first integrated circuit die has been bonded to the second integrated circuit die and before the first integrated circuit die has been bonded to the substrate.
9. The method of claim 1, wherein the first plurality of connectors do not extend substantially beyond the top surface of the substrate or the bottom surface of the first integrated circuit.
10. The method of claim 9, wherein the second plurality of connectors do not extend substantially beyond the top surface of the first integrated circuit or the bottom surface of the second integrated circuit.
11. The method of claim 1, wherein sealing the device comprises applying a single layer of underfill material extending from the substrate to the second integrated circuit die, the layer of underfill material being in contact with both the first and second integrated circuit dies.
12. A method, comprising:
- sealing a device, the device comprising: a substrate; a first integrated circuit die above the substrate and spaced apart from the substrate by a first distance to form a first volume between the substrate and the first integrated circuit die, the first integrated circuit die having a bottom surface closer to the first integrated circuit die and a top surface further from the first integrated circuit die and a plurality of microelectronic devices; a first plurality of connectors extending from the top surface of the substrate to the bottom surface of the first integrated circuit die; a second integrated circuit die above the first integrated circuit die and spaced apart from the first integrated circuit die by a second distance to form a second volume between the first integrated circuit die and the second integrated circuit die, the second integrated circuit die having a plurality of microelectronic devices; a second plurality of connectors extending from the first integrated circuit die to the second integrated circuit die;
- wherein sealing the device comprises substantially sealing the second volume between the first and second integrated circuit dies from a surrounding environment by applying a layer of underfill material extending from the substrate to the second integrated circuit die, wherein a portion of the second volume between the first integrated circuit die and the second integrated circuit die and around the second plurality of connectors is filled with the underfill material after sealing.
13. The method of claim 12, wherein the device is sealed after the first and second integrated circuit dies have been singulated from first and second wafers.
14. The method of claim 12, wherein sealing the device comprises applying a single layer of underfill material extending from the substrate to the second integrated circuit die, the layer of underfill material being in contact with both the first and second integrated circuit dies.
Type: Application
Filed: May 11, 2007
Publication Date: Sep 13, 2007
Inventors: Patrick Morrow (Portland, OR), Grant Kloster (Lake Oswego, OR)
Application Number: 11/747,846
International Classification: H01L 21/98 (20060101);