Abstract: A semiconductor package is disclosed. The disclosed semiconductor package includes a substrate having bonding pads at an upper surface thereof, a lower semiconductor chip, at least one upper semiconductor chip disposed on the lower semiconductor chip, and a dam structure having a closed loop shape surrounding the lower semiconductor chip. The dam structure includes narrow and wide dams disposed between the lower semiconductor chip and the bonding pads. The wide dam has a greater inner width than the narrow dam. The semiconductor packages further includes an underfill disposed inside the dam structure and being filled between the substrate and the lower semiconductor chip.

Abstract: A carrier film for performing a semiconductor package process on a mother substrate including a multi-layer circuit, a mother substrate, and a method of manufacturing a semiconductor package, the carrier film including a base material layer having a predetermined stiffness; and an adhesive layer configured to attach the base material layer onto the mother substrate, the adhesive layer including a water soluble material, wherein the carrier film includes a plurality of openings passing therethrough from a top surface to a bottom surface thereof.

Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.

Abstract: The present disclosure provides a display module, a manufacturing method thereof, and a display device. The display module includes: a display panel including a substrate; a chip on film connected to the display panel; a circuit board connected to the chip on film; and a first film layer attached to surfaces of the display panel and the circuit board facing away from the substrate and covering at least the chip on film and the circuit board.

Abstract: A method of forming an assembly is provided. The method includes attaching a packaged semiconductor device to a substrate. An isolation structure is formed and located between the packaged semiconductor device and the substrate. An underfill material is dispensed between the packaged semiconductor device and the substrate. The isolation structure prevents the underfill material from contacting a first conductive connection formed between the packaged semiconductor device and the substrate.

Abstract: A device and substrate are disclosed. An illustrative device includes a substrate having a first surface and an opposing second surface, a solder material receiving curved surface exposed at the second surface of the substrate, a solder resist material that at least partially covers the solder material receiving curved surface such that a middle portion of the solder receiving curved surface is exposed and such that an edge portion of the solder material receiving curved surface is covered by the solder resist material and forms an undercut, and a solder material disposed within the solder material receiving curved surface and within the undercut.

Abstract: A semiconductor device including: a first silicon layer including a first single crystal silicon layer; first transistors with a single crystal channel and overlaid by a first metal layer; overlaid by a second metal layer; overlaid by a third metal layer; a second level with second transistors and including a metal gate, and then disposed over the third metal layer; the second level is overlaid by a third level with third transistors; and then overlaid by a fourth metal layer; fourth overlaid by a fifth metal layer; a via disposed through the second level; the device includes at least one temperature sensor; the fifth metal layer average thickness is greater than the third metal layer average thickness by at least 50%; at least one element within at least one of the second transistors has been processed independently of the third transistors.

Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.

Abstract: The present embodiments provide systems, processes and/or methods of controlling irrigation. In some embodiments, methods are provided that receive (4112) water usage information corresponding to a first volumetric water usage at a site location having an irrigation controller (130), wherein the first volumetric water usage corresponds to volumetric water usage from a beginning of a budget period of time to a first time within the budget period of time; determine (4114) automatically whether a volumetric water budget at the site location will be met for the budget period of time based on at least the first volumetric water usage, the volumetric water budget corresponding to a specified volume of water for use during the budget period of time; determine (4116) automatically, in the event the volumetric water budget will not be met, an adjustment to the irrigation by the irrigation controller; and output (4118) signaling to effect the adjustment.

Abstract: A semiconductor package includes a lower substrate including a central region and an edge region, an upper substrate on the central region of the lower substrate, a first semiconductor chip on the upper substrate, a second semiconductor chip on the upper substrate and horizontally spaced apart from the first semiconductor chip, a reinforcing structure on the edge region of the lower substrate, and a molding layer that covers an inner sidewall of the reinforcing structure, a top surface of the lower substrate, a sidewall of the first semiconductor chip, a sidewall of the second semiconductor chip, and the upper substrate. The molding layer is interposed between the lower substrate and the upper substrate, between the upper substrate and the first semiconductor chip, and between the upper substrate and the second semiconductor chip. The first semiconductor chip is of a different type from the second semiconductor chip.

Abstract: Provided is a packaging method, including: providing a base with a groove in its surface, which includes at least one pad exposed by the groove; providing a chip having a first surface and a second surface opposite to each other, at least one conductive bump being provided on the first surface of the chip; filling a first binder in the groove; applying a second binder on the first surface of the chip and the conductive bump; and installing the chip on the base, the conductive bump passing through the first binder and the second binder to connect with the pad.

Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes a package substrate, a semiconductor device, an underfill element, and a groove. The semiconductor device is bonded to the surface of the package substrate through multiple electrical connectors. The underfill element is formed between the semiconductor device and the surface of the package substrate to surround and protect the electrical connectors. The underfill element includes a fillet portion that extends laterally beyond the periphery of the semiconductor device and is formed along the periphery of the semiconductor device. The groove is formed in the fillet portion and spaced apart from the periphery of the semiconductor device.

Abstract: A semiconductor package includes a package substrate with a first vent hole, a first semiconductor chip mounted the package substrate, an interposer including supporters on a bottom surface of the interposer and a second vent hole, wherein the supporters contact a top surface of the first semiconductor chip, and the interposer is electrically connected to the package substrate through connection terminals. The semiconductor package further include a second semiconductor chip mounted on the interposer, and a molding layer disposed on the package substrate to cover the first semiconductor chip, the interposer, and the second semiconductor chip.

Abstract: A method includes providing a processed first wafer having front and back sides and including power semiconductor dies implemented within the wafer by processing its front side, each die having a first load terminal at the front side and a second load terminal at the back side; providing an unprocessed second wafer made of an electrically insulating material and having first and second opposing sides; forming a plurality of recesses within the second wafer; filling the plurality of recesses with a conductive material; forming a stack by attaching, prior or subsequent to filling the recesses, the second wafer to the front side of the first wafer, the conductive material electrically contacting the first load terminals of the power semiconductor dies; and ensuring that the conductive material provides an electrical connection between the first side and the second side of the second wafer.

Abstract: A semiconductor device including: a first silicon layer including a first single crystal silicon layer; first transistors with a single crystal channel and overlaid by a first metal layer; overlaid by a second metal layer; overlaid by a third metal layer; a second level with second transistors and including a metal gate, and then disposed over the third metal layer; the second level is overlaid by a third level with third transistors; and then overlaid by a fourth metal layer; fourth overlaid by a fifth metal layer; parts of the second transistors are made with Atomic Layer Deposition (“ALD”); the fifth metal layer average thickness is greater than the third metal layer average thickness by at least 50%; at least one element within at least one of the second transistors has been processed independently of the third transistors.

Abstract: The present invention is a method for producing a power module, including processes (1) to (4) in the following order: (1) a disposition process of disposing a thermosetting resin composition that is solid at 25° C. into a container housing an insulator substrate with multiple semiconductor components mounted thereon; (2) a melt process involving disposing the container having the thermosetting resin composition disposed therein into a molding apparatus capable of heating, pressurization, and depressurization, and heating the container to melt the thermosetting resin composition; (3) a pressurization-depressurization process of performing one or more depressurizations and one or more pressurizations inside the molding apparatus; and (4) a cure process of heating the inside of the molding apparatus to cure the thermosetting resin composition. This is to provide a method for producing a power module having few voids at the time of molding and excellent reliability.

Abstract: A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate and forming a first adhesive element directly on the chip structure. The first adhesive element has a first thermal conductivity. The method also includes forming a second adhesive element directly on the chip structure. The second adhesive element has a second thermal conductivity, and the second thermal conductivity is greater than the first thermal conductivity. The method further includes attaching a protective lid to the chip structure through the first adhesive element and the second adhesive element.

Abstract: An electronic device includes a substrate, a plurality of micro semiconductor structure, a plurality of conductive members, and a non-conductive portion. The substrate has a first surface and a second surface opposite to each other. The micro semiconductor structures are distributed on the first surface of the substrate. The conductive members electrically connect the micro semiconductor structures to the substrate. Each conductive member is defined by an electrode of one of the micro semiconductor structures and a corresponding conductive pad on the substrate. The non-conductive portion is arranged on the first surface of the substrate. The non-conductive portion includes one or more non-conductive members, and the one or more non-conductive members are attached to the corresponding one or more conductive members of the one or more micro conductive structures.

Abstract: The present invention discloses a method for packaging a chip-on-film (COF). The method includes: S1, forming a plurality of first pins on a circuit surface of a flexible circuit substrate, and forming a plurality of second pins on a chip to be packaged; S2, arranging to keep the circuit surface always facing downwards, arranging to keep a surface of the chip to be packaged, where the second pins matching the first pins are arranged, always facing upwards, and arranging the first pins and the second pins, to be opposite to each other; and S3, applying a top-down pressure to the flexible circuit substrate, and/or applying a bottom-up pressure to the chip to be packaged, and simultaneously heating at high temperature to solder the first pins and the second pins in a fused eutectic manner. The method of the present invention improves the product yield and stability.

Abstract: An electronic package structure and a method for manufacturing the same are provided. The electronic package structure includes a first electronic component, a second electronic component, an interconnection element, an insulation layer, and an encapsulant. The second electronic component is disposed adjacent to the first electronic component. The interconnection element is disposed between the first electronic component and the second electronic component. The insulation layer is disposed between the first electronic component and the second electronic component and has a side surface and a top surface connecting to the side surface. The encapsulant surrounds the interconnection element and at least partially covers the top surface of the insulation layer and has an extended portion in contact with the side surface of the insulation layer.

Abstract: A semiconductor device includes: a lead frame that is formed of metal; a wiring substrate that is opposed to the lead frame; an electronic component that is disposed between the lead frame and the wiring substrate; a connection member that connects lead frame and the wiring substrate; and encapsulating resin that is filled between the lead frame and the wiring substrate and covers the electronic component and the connection member. The lead frame includes: a first surface opposed to the wiring substrate and covered by the encapsulating resin; a second surface located on a back side of the first surface and exposed from the encapsulating resin; and a side surface neighboring first surface or the second surface, at least a portion of the side surface exposed from the encapsulating resin.

Abstract: A semiconductor device, the device including: a first silicon layer including a first single crystal silicon layer; a plurality of first transistors each including a single crystal channel; a first metal layer disposed over the plurality of first transistors; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer; a via disposed through the second level, where at least one of the plurality of second transistors includes a metal gate, where an average thickness of the fifth metal layer is greater than an average thickness of the third metal layer by at least 50%; and at least one Electrostatic discharge (“ESD”) structure.

Abstract: Hybrid microelectronic substrates, and related devices and methods, are disclosed herein. In some embodiments, a hybrid microelectronic substrate may include a low-density microelectronic substrate having a recess at a first surface, and a high-density microelectronic substrate disposed in the recess and coupled to a bottom of the recess via solder.

Abstract: This invention describes resins with phosphate cores and a simple, three-step process for their synthesis. Preferred resins are cyanate ester resins with bridging phosphate groups. These resins can be cured to produce thermoset polymers having Tgs of between 131 and >360° C. depending on the number of cyanate ester groups per phosphate and the substitution pattern of the aromatic rings. The high char yields of these resins, up to about 67%, coupled with the phosphate core means that these materials will have applications as fire-resistant polymers. Additionally, these materials can potentially be blended with conventional cyanate esters or other compatible thermosetting resins to improve the fire resistance of composite materials. Other applications may include use in fire-resistant circuit boards, or as surface coatings to reduce flammability of conventional composite materials or thermoplastics.

Abstract: A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a substrate, a semiconductor device, a ring structure, a lid structure, and an adhesive member. The semiconductor device is disposed over the substrate. The ring structure is disposed over the substrate and surrounds the semiconductor device. The lid structure is disposed over the ring structure and extends across the semiconductor device. The adhesive member is disposed in a gap between the ring structure and the semiconductor device and attached to the lid structure and the substrate.

Abstract: Provided are a wafer level package and a method of manufacturing the same, wherein an underfill sufficiently fills a space between a redistribution substrate and a semiconductor chip, thereby reducing warpage. The wafer level package includes a redistribution substrate including at least one redistribution layer (RDL), a semiconductor chip on the redistribution substrate, and an underfill filling a space between the redistribution substrate and the semiconductor chip. The underfill covers side surfaces of the semiconductor chip. The redistribution substrate includes a trench having a line shape and extending in a first direction along a first side surface of the semiconductor chip.

Abstract: A method of forming a semiconductor package is provided. The method includes mounting a chip on a package substrate. The method further includes placing a heat spreader over the chip and applying a thermal interface material to a first surface of the heat spreader facing the chip. The heat spreader is flexible. In addition, the method includes attaching the heat spreader to the chip through the thermal interface material by rolling a rod over a second surface of the heat spreader, and the second surface is opposite to the first surface.

Abstract: Embodiments described herein provide techniques for forming an interconnect structure that includes micro features formed therein. Such embodiments can assist with improving interconnect joint reliability when compared to conventional pads that have a flat surface. An interconnect structure may comprise: a metal pad over a substrate (e.g., a semiconductor package, a PCB, an interposer, etc.). Micro features may be formed in an edge of the metal pad or away from the edge of the metal pad. The micro features can assist with: (i) increasing the contact area between solder used to form an interconnect joint and the metal pad; and (ii) improving adherence of solder used to form an interconnect joint to the metal pad. These benefits can improve interconnect joint reliability by, among others, improving the interconnect joint's ability to absorb stress from substrates having differing coefficients of thermal expansion.

Abstract: A semiconductor package is provided. The semiconductor package includes an encapsulating layer, a semiconductor die formed in the encapsulating layer, and an interposer structure covering the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure also includes insulting features formed on the first surface of the insulating base and extending into the encapsulating layer. The insulting features are arranged in a matrix and face a top surface of the semiconductor die. The interposer structure further includes first conductive features formed on the first surface of the insulating base and extending into the encapsulating layer. The first conductive features surround the matrix of the plurality of insulting features.

Abstract: The method of producing an electronic component (100) comprises a step A) of providing a semiconductor chip (2) having an underside (20), having a plurality of contact pins (21), and having at least one positioning pin (25) protruding from the underside. The contact pins are adapted to electrically contact the semiconductor chip. The positioning pin narrows in the direction away from the underside and protrudes further from the underside than the contact pins. The semiconductor chip is placed on the connection carrier, with the contact pins each being inserted into a contact recess and the positioning pin being inserted into the positioning recess. The contact pins are immersed in the molten solder material.

Abstract: Present disclosure provides a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes a substrate, a conductive layer in the substrate, a conductive bump over the substrate and electrically coupled to the conductive layer, and a dielectric stack, including a polymer layer laterally surrounding the conductive bump and including a portion spaced from a nearest outer edge of the conductive bump with a gap, wherein a first thickness of the polymer layer in a first region is greater than a second thickness of the polymer layer in a second region adjacent to the first region, a first bottom surface of the polymer layer in the first region is leveled with a second bottom surface of the polymer layer in the second region, and a dielectric layer underneath the polymer layer.

Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.

Abstract: An electronic substrate and an electronic device are provided. The electronic substrate includes a base, a protruding portion, and a bonding pad. The protruding portion and the bonding pad are disposed on the base. The bonding pad is not overlapped with a boundary of the protruding portion.

Abstract: A semiconductor device, the device including: a first silicon layer including a first single crystal silicon layer; a first metal layer disposed over the first single crystal silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer; and a via disposed through the second level, where the via has a diameter of less than 450 nm, and where a typical thickness of the fifth metal layer is greater than a typical thickness of the third metal layer by at least 50%.

Abstract: Disclosed herein are various methods of packaging a semiconductor X-ray detector. The methods may include bonding chips including an X-ray absorption layer or including both an X-ray absorption layer and an electronic layer onto another support such as an interposer substrate or a printed circuit board.

Abstract: A method of selectively transferring micro devices from a donor substrate to contact pads on a receiver substrate. Micro devices being attached to a donor substrate with a donor force. The donor substrate and receiver substrate are aligned and brought together so that selected micro devices meet corresponding contact pads. A receiver force is generated to hold selected micro devices to the contact pads on the receiver substrate. The donor force is weakened and the substrates are moved apart leaving selected micro devices on the receiver substrate. Several methods of generating the receiver force are disclosed, including adhesive, mechanical and electrostatic techniques.

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a mold over and around a first die and a first via. The semiconductor package has a conductive pad of a first redistribution layer disposed on a top surface of the first die and/or a top surface of the mold. The semiconductor package includes a second die having a solder ball coupled to a die pad on a bottom surface of the second die, where the solder ball of the second die is coupled to the first redistribution layer. The first redistribution layer couples the second die to the first die, where the second die has a first edge and a second edge, and where the first edge is positioned within a footprint of the first die and the second edge is positioned outside the footprint of the first die.

Abstract: An integrated magnetoresistive device includes a substrate of semiconductor material that is covered, on a first surface, by an insulating layer. A magnetoresistor of ferromagnetic material extends within the insulating layer and defines a sensitivity plane of the sensor. A concentrator of ferromagnetic material includes at least one arm that extends in a transversal direction to the sensitivity plane and is vertically offset from the magnetoresistor. The concentrator concentrates deflects magnetic flux lines perpendicular to the sensitivity plane so as to generate magnetic-field components directed in a parallel direction to the sensitivity plane.

Abstract: A method for forming a chip package structure is provided. The method includes disposing a first chip structure and a second chip structure over a wiring substrate. The first chip structure is spaced apart from the second chip structure by a gap. The method includes disposing a ring structure over the wiring substrate. The ring structure has a first opening, the first chip structure and the second chip structure are in the first opening, the first opening has a first inner wall, the first inner wall has a first recess, and the gap extends toward the first recess.

Abstract: A package structure is provided. The package structure includes a redistribution structure and a semiconductor die over the redistribution structure, and bonding elements below the redistribution structure. The semiconductor die has a first sidewall and a second sidewall connected to each other. The bonding elements include a first row of bonding elements and a second row of bonding elements. In a plan view, the second row of bonding elements is arranged between the first row of bonding elements and an extending line of the second sidewall. A minimum distance between the second row of bonding elements and the first sidewall is greater than the minimum distance between the first row of bonding elements and the first sidewall.

Abstract: The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a package substrate, a bottom device die, an interposing package substrate and a top device die. The bottom device die is bonded to the package substrate. The interposing package substrate is located over the bottom device die and bonded to the package substrate. The top device die is bonded to the interposing package substrate form above the interposing package substrate.

Abstract: A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a substrate, an electronic component, a ring structure, and an adhesive layer. The electronic component is located over a first surface of the substrate. The ring structure is located over the first surface of the substrate and surrounding the electronic component. The ring structure has a bottom surface facing the first surface of the substrate and a top surface opposite the bottom surface. The ring structure includes a plurality of side parts and a plurality of corner parts recessed from the top surface and thinner than the side parts. Any two of the corner parts are separated from one another by one of the side parts. The adhesive layer is interposed between the bottom surface of the ring structure and the first surface of the substrate.

Abstract: Underfill materials with graded moduli for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, the underfill material between a semiconductor die and a package substrate includes a matrix material, first filler particles with a first size distribution, and second filler particles with a second size distribution different than the first size distribution. Centrifugal force may be applied to the underfill material to arrange the first and second filler particles such that the underfill material may form a first region having a first elastic modulus and a second region having a second elastic modulus different than the first elastic modulus. Once the underfill material is cured, portions of conductive pillars coupling the semiconductor die with the package substrate may be surrounded by the first region, and conductive pads of the package substrate may be surrounded by the second region.

Abstract: A method for fabricating an electronic package is provided. A filling material is formed in an interval S, at which a plurality of electronic components disposed on a carrying structure are spaced apart from one another. The filling material acts as a spacer having a groove, and the groove acts as a stress buffering region. Therefore, the electronic components can be prevented from being broken due to stress concentration.

Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

Abstract: A stack package and a method of manufacturing the stack package are provided. The method includes: attaching a first semiconductor device onto a first surface of a first package substrate; attaching a molding resin material layer onto a first surface of a second package substrate; arranging the first surface of the first package substrate and the first surface of the second package substrate to face each other; compressing the first package substrate and the second package substrate while reflowing the molding resin material layer; and hardening the reflowed molding resin material layer.

Abstract: A semiconductor package includes a package substrate and a semiconductor chip mounted on the package substrate. The package substrate includes a signal bump land and an anchoring bump land, and the semiconductor chip includes a signal bump and an anchoring bump. The signal bump is bonded to the signal bump land, the anchoring bump is disposed to be adjacent to the anchoring bump land, and a bottom surface of the anchoring bump is located at a level which is lower than a top surface of the anchoring bump land with respect to a surface of the package substrate.

Abstract: A semiconductor device, the device including: a first silicon layer including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first single crystal silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer; and a via disposed through the second level, where the via has a diameter of less than 450 nm, where the via includes tungsten, and where a typical thickness of the fifth metal layer is greater than a typical thickness of the second metal layer by at least 50%.

Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.

Abstract: Discussed is a flexible display device to reduce a width of a bezel. The flexible display device includes a substrate being formed of a flexible material, a plurality of gate lines and a plurality of data lines crossing each other, a plurality of pads formed in a pad area of a non-display area, a plurality of links formed in a link area of the non-display area a plurality of insulation films formed over the entire surface of the substrate, and a first bending hole formed in a bending area of the non-display area, the first bending hole passing through at least one of the insulation films disposed under the link, wherein the bending area is bent such that the pads are disposed on the lower surface of the substrate.