Abstract: Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression.

Abstract: The described techniques address issues associated with electrostatic discharge (ESD) protection for multi-die integrated circuits (ICs). The techniques include the use of two or more semiconductor dies within a multi-die IC, which may include a first semiconductor die without ESD protection but with full ESD exposure. The first semiconductor receives ESD protection via a second semiconductor die that is integrated as part of the same package with the first semiconductor die. The second semiconductor die may be electrically more remote from ESD-exposed pins compared to the first semiconductor die. The first semiconductor die may include integrated passive devices. The second semiconductor die enables ESD protection for both semiconductor dies in the same integrated IC package.

Abstract: Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression.

Abstract: Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression.

Abstract: A semiconductor package includes a redistribution substrate and a semiconductor chip thereon. The redistribution substrate includes a ground under-bump pattern, signal under-bump patterns laterally spaced apart from the ground under-bump pattern, first signal line patterns disposed on the signal under-bump patterns and coupled to corresponding signal under-bump patterns, and a first ground pattern coupled to the ground under-bump pattern and laterally spaced apart from the first signal line pattern. Each of the signal and ground under-bump patterns includes a first part and a second part formed on the first part and that is wider than the first part. The second part of the ground under-bump pattern is wider than the second part of the signal under-bump pattern. The ground under-bump pattern vertically overlaps the first signal line patterns. The first ground pattern does not vertically overlap the signal under-bump patterns.

Abstract: A method for adjusting a height of an edge ring arranged around an outer portion of a substrate support includes receiving at least one input indicative of one or more erosion rates of the edge ring. The at least one input includes a plurality of erosion rates for respective usage periods of a substrate processing system. The method further includes determining at least one erosion rate of the edge ring using the plurality of erosion rates for the respective usage periods, monitoring an overall usage of the edge ring and storing the overall usage of the edge ring in a memory, calculating an amount of erosion of the edge ring based on the determined at least one erosion rate and the overall usage of the edge ring, and adjusting the height of the edge ring based on the calculated amount of erosion to compensate for the calculated amount of erosion.

Abstract: A package that includes a substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the first integrated device. A portion of the second integrated device overhangs over the first integrated device. The second integrated device is configured to be coupled to the substrate. The second integrated device includes a front side and a back side. The front side of the second integrated device faces the substrate.

Abstract: A wet alignment method for a micro-semiconductor chip and a display transfer structure are provided. The wet alignment method for a micro-semiconductor chip includes: supplying a liquid to a transfer substrate including a plurality of grooves; supplying the micro-semiconductor chip onto the transfer substrate; scanning the transfer substrate by using an absorber capable of absorbing the liquid. According to the wet alignment method, the micro-semiconductor chip may be transferred onto a large area.

Abstract: This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device.

Abstract: Clamped semiconductor wafers and clamped semiconductor devices include reservoirs filled with a flowable metal which hardens to allow the wafers/devices to be shipped or stored. The hardened metal may also be reflowed to a liquid to allow clamping of the semiconductor wafers together and to allow clamping of the semiconductor packages together. The flowable metal may be filled into the reservoirs as a liquid or paste. Thereafter, the flowable metal may be cooled to harden the flowable metal into a clamping member.

Abstract: A connection structure includes a circuit board, an insulating member, a housing, and a conductive wire. The insulating member includes a first portion and a second portion. The first portion is fixed to the circuit board. The second portion faces the first portion. The second portion is fixed to the housing. The housing includes a grounded contact. The conductive wire electrically connects the circuit board and the housing while being wound around the insulating member. A shortest distance along a surface of the housing from a position where the conductive wire and the housing are connected to the contact is shorter than a shortest distance along a surface of the housing from the second portion of the insulating member to the contact.

Abstract: An electronic device is disclosed. The electronic device includes a circuit layer, an electronic element and a thermal conducting element. The electronic element is disposed on the circuit layer and electrically connected to the circuit layer. The thermal conducting element is disposed between the circuit layer and the electronic element. The thermal conducting element is used for performing heat exchange with the electronic element.

Abstract: Various embodiments of the disclosure disclose a method for manufacturing a micro Light Emitting Diode (LED) display. The disclosed manufacturing method may include coating a face of a substrate including a circuit portion with a first thickness of a polymer adhesive solution containing a plurality of metal particles, attaching an array of micro LED chips on the polymer adhesive solution, physically connecting a connection pad for each of the array of micro LED chips to the metal particles through heating and pressing the attached plurality of micro LED chips to descend through the polymer adhesive solution, and chemically bonding the metal particles to the connection pad and the circuit portion through heating and pressing so that the micro LED chips are electrically connected to the circuit portion. Various other embodiments are also possible.

Abstract: Exemplary embodiments for redistribution layers of integrated circuit components are disclosed. The redistribution layers of integrated circuit components of the present disclosure include one or more arrays of conductive contacts that are configured and arranged to allow a bonding wave to displace air between the redistribution layers during bonding. This configuration and arrangement of the one or more arrays minimize discontinuities, such as pockets of air to provide an example, between the redistribution layers during the bonding.

Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.

Abstract: A semiconductor package includes a first semiconductor chip having a first substrate, a first insulating layer on the first substrate, and a plurality of first bonding pads on the first insulating layer, and having a flat upper surface by an upper surface of the first insulating layer and upper surfaces of the plurality of first bonding pads; and a second semiconductor chip on the upper surface of the first semiconductor chip and having a second substrate, a second insulating layer below the second substrate and in contact with the first insulating layer, and a plurality of second bonding pads on the second insulating layer and in contact with the first bonding pads, respectively, wherein the first insulating layer includes an insulating interfacial layer in contact with the second insulating layer, embedded in the first insulating layer, and spaced apart from the plurality of first bonding pads.

Abstract: Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer.

Abstract: A semiconductor device including a base substrate B, which includes wire layers, chips C1, C2, C3, C4, C5, and C6 provided on the base substrate B, and a protective film P provided on each of the side faces of the chips C1, C2, C3, C4, C5, and C6.

Abstract: A semiconductor device having a channel between active sections or portions of the device is disclosed. An elastic material, such as dielectric or a polymer, is deposited into the channel and cured to increase flexibility and thermal expansion properties of the semiconductor device. The elastic material reduces the thermal and mechanical mismatch between the semiconductor device and the substrate to which the semiconductor device is coupled in downstream processing to improve reliability. The semiconductor device may also include a plurality of channels formed transverse with respect to each other. Some of the channels extend all the way through the semiconductor device, while other channels extend only partially through the semiconductor device.

Abstract: A power converter includes a field graded substrate, a plurality of power device dies attached to the field graded substrate, a polymer layer on the field graded substrate, one or more conductors over the polymer layer, and a plurality of power conditioning components mounted on the field graded substrate to form a power converter circuit. The field graded substrate includes a first conductor layer, a graded layer that blends conductor and insulator material, and a second conductor layer, the graded layer having an insulator core.

Abstract: A method of forming a semiconductor package includes the following operations. A first integrated circuit structure is provided, and the first integrated circuit structure includes a first substrate and a silicon layer over the first substrate. A plasma treatment is performed to transform a top portion of the silicon layer to a first bonding layer on the remaining silicon layer of the first integrated circuit structure. A second integrated circuit structure is provided, and the second integrated circuit structure includes a second substrate and a second bonding layer over the second substrate. The second integrated circuit structure is bonded to the first integrated circuit structure through the second bonding layer of the second integrated circuit structure and the first bonding layer of the first integrated circuit structure.

Abstract: Using nucleotide architectures to very closely and precisely placed chromophores that produce quantum coherent excitons, biexcitons, and triexcitons upon excitement to create excitonic quantum wires, switching, and gates that would then form the basis of quantum computation. Creating the various excitons and controlling the timing of the excitons would be performed using light of the corresponding wavelength and polarization to stimulate the corresponding chromophores.

Abstract: A method for forming a package structure may comprise applying a die and vias on a carrier having an adhesive layer and forming a molded substrate over the carrier and around the vias, and the ends of the vias and mounts on the die exposed. The vias may be in via chips with one or more dielectric layers separating the vias. The via chips 104 may be formed separately from the carrier. The dielectric layer of the via chips may separate the vias from, and comprise a material different than, the molded substrate. An RDL having RDL contact pads and conductive lines may be formed on the molded substrate. A second structure having at least one die may be mounted on the opposite side of the molded substrate, the die on the second structure in electrical communication with at least one RDL contact pad.

Abstract: A circuit device includes: a first substrate having a first barrier layer; a second substrate having a second barrier layer; a first conductive portion arranged over the first barrier layer; a second conductive portion arranged over the second barrier layer; a first expanding pad arranged on the first conductive portion and including a first contact area greater than that of the first conductive portion; and a second expanding pad bonded to the first expanding pad, arranged on the second conductive portion and including a second expanded contact area greater than that of the second conductive portion. The first barrier layer and the second barrier layer include aluminum fluoride.

Abstract: A semiconductor package includes a first die structure, a first redistribution structure that is disposed on the first die structure, a second die structure that is disposed on the first redistribution structure, and a second redistribution structure that is disposed on the second die structure. The first die structure includes an interposer, and the interposer includes a semiconductor substrate and through-vias that penetrate through the semiconductor substrate. A first integrated circuit die is disposed in the semiconductor substrate of the interposer. The second die structure includes a second integrated circuit die that is encapsulated in an encapsulant and several conductive pillars that penetrate through the encapsulant. The first integrated circuit die is electrically connected to the second integrated circuit die through the first redistribution structure, the conductive pillars, and the second redistribution structure.

Abstract: A microLED mass transfer stamping system includes a stamp substrate with an array of trap sites, each configured with a columnar-shaped recess to temporarily secure a keel extended from a bottom surface of a microLED. In the case of surface mount microLEDs, the keel is electrically nonconductive. In the case of vertical microLEDs, the keel is an electrically conductive second electrode. The stamping system also includes a fluidic assembly carrier substrate with an array of wells having a pitch separating adjacent wells that matches the pitch separating the stamp substrate trap sites. A display substrate includes an array of microLED pads with the same pitch as the trap sites. The stamp substrate top surface is pressed against the display substrate, with each trap site interfacing a corresponding microLED site, and the microLEDs are transferred. Fluidic assembly stamp substrates are also presented for use with microLEDs having keels or axial leads.

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip bumps between the first package substrate and the first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, a molding member which covers the plurality of second semiconductor chips, on the first semiconductor chip, and a thermoelectric cooling layer attached onto a surface of the first semiconductor chip. The thermoelectric cooling layer includes a cooling material layer extending along the surface of the first semiconductor chip, a first electrode pattern which surrounds the plurality of first chip bumps from a planar viewpoint, in the cooling material layer, and a second electrode pattern which surrounds the first electrode pattern from the planar viewpoint, in the cooling material layer.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first wafer including a first metal structure within a body of the first wafer. The semiconductor structure also includes a second wafer including a second metal structure within a body of the second wafer, where the first wafer is coupled to the second wafer at an interface. The semiconductor structure further includes a metal bonding structure coupled to the first metal structure and the second metal structure and extending through the interface.

Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.

Abstract: A method and device for bonding a first substrate to a second substrate at contact surfaces of the substrates. The method includes the following steps: mounting the first substrate on a first mounting surface of a first substrate holder and mounting the second substrate on a second mounting surface of a second substrate holder, wherein the substrate holders are arranged in a chamber; contacting the contact surfaces at a bond initiation surface; and bonding the first substrate to the second substrate from the bond initiation surface to the centre of the substrates.

Abstract: A method of manufacturing a wafer includes a wafer preparing step of preparing a wafer having semiconductor devices formed in a plurality of respective areas demarcated thereon by a plurality of intersecting streets, a removing step of removing from the wafer a defective device region including a semiconductor device determined as a defective product among the semiconductor devices formed on the wafer, an enlarging step of enlarging a removed region formed in the wafer by removing the defective device region from the wafer, and an inlaying step of inlaying a device chip including a non-defective semiconductor device that is functionally identical to the semiconductor device determined as the defective product, in the enlarged removed region.

Abstract: A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material.

Abstract: A method for bonding a first substrate and a second substrate includes: forming a protrusion at a partial region of the first substrate; measuring a position of the first substrate after the protrusion is formed in the first substrate; and bonding the first substrate and the second substrate by contacting the protrusion of the first substrate with a surface of the second substrate to form a contact region and enlarging the contact region.

Abstract: A wet alignment method for a micro-semiconductor chip and a display transfer structure are provided. The wet alignment method for a micro-semiconductor chip includes: supplying a liquid to a transfer substrate including a plurality of grooves; supplying the micro-semiconductor chip onto the transfer substrate; scanning the transfer substrate by using an absorber capable of absorbing the liquid. According to the wet alignment method, the micro-semiconductor chip may be transferred onto a large area.

Abstract: Embodiments disclosed herein include electronic packages with conformal shields and methods of forming such packages. In an embodiment, the electronic package comprises a die having a first surface, a second surface opposite the first surface, and sidewall surfaces. A redistribution layer is over the first surface of the die, and the redistribution layer comprises a first conductive layer. In an embodiment, an under ball metallization (UBM) layer is over the redistribution layer, and a conductive shield is over the sidewall surfaces of the die and the second surface of the die. In an embodiment, the conductive shield is electrically coupled to the UBM layer.

Abstract: A solidly mounted resonator (SMR)-based magnetoelectric (ME) antenna comprises a substrate, a Bragg reflector disposed on the substrate, a magnetostrictive/piezoelectric ME composite element disposed on the Bragg reflector, a first electrically conductive contact and a second electrically conductive contact. The first contact is disposed between the Bragg reflector and the magnetostrictive/piezoelectric ME composite element and electrically coupled to a bottom surface of the magnetostrictive/piezoelectric ME composite element. The second contact is disposed on top of the magnetostrictive/piezoelectric ME composite element and electrically coupled to the top of the magnetostrictive/piezoelectric ME composite element. The magnetostrictive/piezoelectric ME composite element comprises a magnetorestrictive multilayer deposited on a piezoelectric layer. The magnetorestrictive multilayer produces an in-plane uniaxial magnetic anisotropy (UMA). The UMA is a twofold UMA that exhibits a symmetric radiation pattern.

Abstract: Polymers synthesized by solid-phase synthesis are selectively released from a solid support by reversing the bias of spatially addressable electrodes. Change in the current and voltage direction at one or more of the spatially addressable electrodes changes the ionic environment which triggers cleavage of linkers that leads to release of the attached polymers. The spatially addressable electrodes may be implemented as CMOS inverters embedded in an integrated circuit (IC). The IC may contain an array of many thousands of spatially addressable electrodes. Control circuity may independently reverse the bias on any of the individual electrodes in the array. This provides fine-grained control of which polymers are released from the solid support. Examples of polymers that may be synthesized on this type of array include oligonucleotides and peptides.

Abstract: Semiconductor device packages may include a first semiconductor device over a substrate and a second semiconductor device over the first semiconductor device. An active surface of the second semiconductor device may face away from the substrate. Conductors may extend from bond pads of the second semiconductor device, along surfaces of the second semiconductor device, first semiconductor device, and substrate to pads of routing members of the substrate. The conductors may be in contact with the bond pads and the routing members and a dielectric material interposed between the conductors and the first semiconductor device and between the conductors and the second semiconductor device. An encapsulant distinct from the dielectric material may cover the conductors, the first semiconductor device, the second semiconductor device, and an upper surface of the substrate. Methods of fabrication are also disclosed.

Abstract: A die stack structure including a first die, an encapsulant, a redistribution layer and a second die is provided. The encapsulant laterally encapsulates the first die. The redistribution layer is disposed below the encapsulant, and electrically connected with the first die. The second die is disposed between the redistribution layer and the first die, wherein the first and second dies are electrically connected with each other, the second die comprises a body portion having a first side surface, a second side surface and a curved side surface therebetween, and the curved side surface connects the first side surface and the second side surface.

Abstract: First and second chiplets are positioned along a surface to respectively cover first and second electrodes. The first electrode is activated to cause an attraction force between the first electrode and the first chiplet. The second electrode is deactivated allowing the second chiplet to rotate on the surface. While the first electrode is activated and the second electrode is deactivated, a rotation field is applied to cause the second chiplet to be oriented at a desired orientation angle, the first chiplet being prevented from rotating by the attraction force.

Abstract: A package on package structure includes a first package, a plurality of conductive bumps, a second package and an underfill. The conductive bumps are disposed on a second surface of the first package and electrically connected to the first package. The second package is disposed on the second surface of the first package through the conductive bumps, and includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. A shortest distance from an upper surface of the encapsulating material to an upper surface of the semiconductor device is greater than or substantially equal to twice a thickness of the semiconductor device. The underfill is filled between the first package and the second package.

Abstract: An emitter may include a substrate, a conductive layer on at least a bottom surface of a trench, and a first metal layer to provide a first electrical contact of the emitter on an epitaxial side of the substrate. The first metal layer may be within the trench such that the first metal layer contacts the conductive layer within the trench. The emitter may further include a second metal layer to provide a second electrical contact of the emitter on the epitaxial side of the substrate, and an isolation implant to block lateral current flow between the first electrical contact and the second electrical contact.

Abstract: Methods of bonding and structures with such bonding are disclosed. One such method includes providing a first substrate with a first electrical contact; providing a second substrate with a second electrical contact above the first electrical contact, wherein an upper surface of the first electrical contact is spaced apart from a lower surface of the second electrical contact by a gap; and depositing a layer of selective metal on the lower surface of the second electrical contact and on the upper surface of the first electrical contact by a thermal Atomic Layer Deposition (ALD) process until the gap is filled to create a bond between the first electrical contact and the second electrical contact.

Abstract: A semiconductor device including: a first formation site and a second formation site for forming a first conductive bump and a second conductive bump; when a first environmental density corresponding to the first formation site is greater than a second environmental density corresponding to the second formation site, a cross sectional area of the second formation site is greater than a cross sectional area of the first formation site; wherein the first environmental density is determined by a number of formation sites around the first formation site in a predetermined range and the second environmental density is determined by a number of formation sites around the second formation site in the predetermined range; wherein a first area having the first environmental density forms an ellipse layout while a second area having the second environmental density forms a strip layout surrounding the ellipse layout.

Abstract: A method of interconnecting metallic structures in the manufacture of a three-dimensional semiconductor is provided, the method comprising providing a first upper surface of a first substrate and a second upper surface of a second substrate with a bonding layer; bonding the first upper surface to the second upper surface to provide a bond; etching a via through a lower surface of the first substrate, through the first substrate, around a first metallic structure embedded in the first substrate, through the bond and to a second metallic structure embedded in the second substrate; and filling the via with a conductive material to provide a via structure, thereby electrically connecting the metallic structures.

Abstract: A protective enclosure for a PCB assembly, e.g., a solid-state-drive assembly. In an example embodiment, the enclosure comprises a flexible, stamped-metal heat spreader connected, by way of cured-liquid TIM parts, to at least some of the packaged integrated circuits on one side of the PCB assembly. In some embodiments, additional cured-liquid TIM parts may be connected between the body of the protective enclosure and packaged integrated circuits on the other side of the PCB assembly and/or the assembly's PCB. The PCB assembly, heat spreader, and various TIM parts are arranged in a manner that helps to significantly lower the risk of solder-joint failure under thermal cycling.

Abstract: A power semiconductor package comprises a lead frame, a semiconductor chip, and a molding encapsulation. The lead frame comprises an elevated section comprising a source section; a drain section; and a plurality of leads. The semiconductor chip includes a metal-oxide-semiconductor field-effect transistor (MOSFET) disposed over the lead frame. The semiconductor chip comprises a source electrode, a drain electrode, and a gate electrode. The source electrode of the semiconductor chip is electrically and mechanically connected to the source section of the elevated section of the lead frame. The semiconductor chip is served as a low side field-effect transistor as a flipped-chip connected to a heat sink by a first thermal interface material. A high side field-effect transistor is connected to the heat sink by a second thermal interface material. The low side field-effect transistor and the high side field-effect transistor are mounted on a printed circuit board.

Abstract: Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an integrated assembly includes a pillar having an upper source/drain, a middle source/drain, a lower source/drain, an upper channel between the upper source/drain and the middle source/drain, and a lower channel between the middle source/drain and the lower source/drain. The integrated assembly includes a gate pair that includes a first gate and a second gate. The first gate is positioned on a first side of the pillar at a first height, and the second gate is positioned on a second side of the pillar, that is opposite the first side, at a second height that is different from the first height. The integrated assembly includes a capacitor that is electrically coupled with the upper source/drain. Some implementations include methods of forming the various structures, integrated assemblies, and memory devices.

Abstract: In a high resolution temperature sensor, first and second MEMS resonators generate respective first and second clock signals and a locked-loop reference clock generator generates a reference clock signal having a frequency that is phase-locked to at least one of the first and second clock signals. A frequency-ratio engine within the MEMS temperature sensor oversamples at least one of the first and second clock signals with the reference clock signal to generate a ratio of the frequencies of the first and second clock signals.

Abstract: A semiconductor package includes: a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential. The first pad is spaced inward from an edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. Methods of production are also provided.