Assembly Of Devices Consisting Of Solid-state Components Formed In Or On A Common Substrate; Assembly Of Integrated Circuit Devices (epo) Patents (Class 257/E21.705)
  • Patent number: 10908022
    Abstract: A method of manufacturing a Fabry-Perot interference filter includes a forming step of forming a first thinned region, a first mirror layer, a sacrificial layer, and a second mirror layer are formed on a first main surface of a wafer, and the first thinned region in which at least one of the first mirror layer, the sacrificial layer, and the second mirror layer is partially thinned along each of a plurality of lines is formed; a cutting step of cutting the wafer into a plurality of substrates along each of the plurality of lines by forming a modified region within the wafer along each of the plurality of lines through irradiation of a laser light, after the forming step; and a removing step of removing a portion from the sacrificial layer through etching, between the forming step and the cutting step or after the cutting step.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: February 2, 2021
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Takashi Kasahara, Katsumi Shibayama, Masaki Hirose, Toshimitsu Kawai, Hiroki Oyama, Yumi Kuramoto
  • Patent number: 10856404
    Abstract: A signal processing circuit includes: a printed circuit board (PCB) including a first surface layer, a second surface layer, a first reference layer, and a second reference layer, wherein the first and second surface layers are positioned on opposing side of the PCB while the first reference layer and the second reference layer are positioned between the first and second surface layers; a memory chip positioned on the first surface layer; a controller chip positioned on the second surface layer; a first set of signal lines arranged on the first surface layer and coupled with the memory chip, wherein all signal lines in the first set of signal lines does not cross each other; and a second set of signal lines arranged on the second surface layer and coupled with the controller chip, wherein all signal lines in the second set of signal lines does not cross each other.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: December 1, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Shou-Te Yen, Chao-Min Lai, Ping-Chia Wang
  • Patent number: 10833048
    Abstract: A technique relates to a semiconductor device. First nanowires are formed on a first substrate, the first nanowires being electrically coupled to one or more first electrical sites on the first substrate. Second nanowires are formed on a second substrate, the second nanowires being electrically coupled to one or more second electrical sites on the second substrate. The first nanowires and the second nanowires are electrically coupled such that the one or more first electrical sites are electrically coupled to the one or more second electrical sites.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Li-Wen Hung, Reinaldo Vega, Hari Mallela
  • Patent number: 10748792
    Abstract: A method for mass arrangement of micro-component devices includes the following process stages: disposing the micro-component devices to float on a liquid suspending medium, wherein the micro-component devices are spaced apart from each other with a larger initial gap along a first direction and along a second direction; using electromagnetic force to actuate the floating micro-component devices to move closer so that the micro-component devices become spaced apart from each other with a smaller specified target gap along the first and the second directions; and transferring the arranged micro-component devices with the target gap on a carrier substrate. A system for arranging the micro-component devices is also disclosed to implement the method. Therefore, a precisely arranged array of the micro-component devices can be formed on a target application substrate.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: August 18, 2020
    Assignee: Maven Optronics Co., Ltd.
    Inventor: Chieh Chen
  • Patent number: 10707187
    Abstract: The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device capable of reducing the uppermost semiconductor chip damage and stably performing wire bonding even if an excessive force is applied during a die bonding process or a wire bonding process, and a method for manufacturing the semiconductor device.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: July 7, 2020
    Assignee: LG Chem, Ltd.
    Inventors: Jung Hak Kim, Hee Jung Kim, Se Ra Kim, Jung Ho Jo, Kwang Joo Lee, Seung Hee Nam, Young Kook Kim
  • Patent number: 10651132
    Abstract: A semiconductor device includes a wiring board, a first semiconductor chip fixed to the wiring board and having a first surface film, a second semiconductor chip having a second surface film and positioned such that the first semiconductor chip is between the second semiconductor chip and the wiring board, a supporting plate between the first and second semiconductor chips, the supporting plate having a first surface and a second surface located on the side opposite to the first surface, the second surface facing the first semiconductor chip, and supporting the second semiconductor chip, a front surface layer on the first surface and formed of the same material as the second surface film, a spacer between the wiring board and the supporting plate, and a sealing resin that covers the second semiconductor chip and the supporting plate and contacts the second surface film and the front surface layer.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: May 12, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshitaka Ono, Masamitsu Oshikiri
  • Patent number: 10600713
    Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip which are disposed side-by-side on a surface of a package substrate. A heat insulation wall is disposed between the first semiconductor chip and the second semiconductor chip. The heat insulation wall thermally isolates the first semiconductor chip from the second semiconductor chip.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: March 24, 2020
    Assignee: SK hynix Inc.
    Inventors: Min Kyu Kang, Jae Hyun Son, Ji Hyeok Shin
  • Patent number: 10573632
    Abstract: A method of manufacturing a display module includes preparing a first substrate structure including an light-emitting diode (LED) array containing a plurality of LED cells, electrode pads connected to the first and second conductivity-type semiconductor layers, and a first bonding layer covering the LED array; preparing a second substrate structure including a plurality of thin-film transistor (TFT) cells disposed on a second substrate, and each having a source region, a drain region and a gate electrode disposed therebetween, the second substrate structure being provided by forming a circuit region, in which connection portions disposed to correspond to the electrode pads are exposed to one surface thereof, and by forming a second bonding layer covering the circuit region, respectively planarizing the first and second bonding layers, and bonding the first and second substrate structures to each other.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: February 25, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji Hye Yeon, Su Hyun Jo, Sung Hyun Sim, Ha Nul Yoo, Yong Il Kim, Han Kyu Seong
  • Patent number: 10559594
    Abstract: A new architecture to fabricate high-rise fully monolithic three-dimensional Integrated-Circuits (3D-ICs) is described. It has the major advantage over all known prior arts in that it substantially reduces RC-delays and fully eliminates or very substantially reduces the large and bulky electrically conductive Through-Silicon-VIAS in a monolithic 3D integration. This enables the 3D-ICs to have faster operational speed with denser device integration.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: February 11, 2020
    Inventors: Ahmad Tarakji, Nirmal Chaudhary
  • Patent number: 10530367
    Abstract: The disclosure relates to systems and methods for sector-to-sector and die-to-die clock synchronization in programmable logic devices. The methods and systems may employ phase difference detector and programmable delay elements to minimize skews in the clock tree and facilitate timing closure of time-critical paths and increase in operating frequencies.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 7, 2020
    Assignee: Intel Corporation
    Inventors: Chooi Pei Lim, Teik Wah Lim, Boon Haw Ooi, Keong Hong Oh
  • Patent number: 10475675
    Abstract: An apparatus for manufacturing a semiconductor device includes a stage configured to hold tape adhering to a second surface of a semiconductor wafer having the second surface and a first surface opposite to the second surface, a vacuum mechanism attachable to an upper side of a substrate provided to adhere to the first surface, a driving unit configured to drive the vacuum mechanism in a direction by which the vacuum mechanism is separated from the substrate, and a cooling unit configured to cool the tape.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: November 12, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Jun Tanaka, Masaya Shima
  • Patent number: 10418311
    Abstract: Apparatuses and methods using a silicon on insulator (SOI) substrate are described. An example apparatus includes: a substrate including a first surface and a second surface opposite to the first surface; a circuit formed in the first surface; a first electrode through the substrate from the first surface to the second surface; and a first insulative film around the first electrode. The first electrode includes: a first portion formed in the substrate; and a second portion continuous to the first portion and protruding from the second surface. The first insulative film is formed between the first portion of the first electrode in the substrate and extending to a side surface of the second portion of the first electrode.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: September 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Toshiyuki Maenosono, Yuta Kikuchi, Manabu Ito, Yoshihiro Saeki
  • Patent number: 10396061
    Abstract: Dust-sized and light transparent semiconductor chips are provided and are used in a transparent electronic system. The dust-sized and light transparent semiconductor chips are composed entirely of materials that are transparent to visible light. The dust-sized and light transparent semiconductor chips are used as a component of a transparent electronic system.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ning Li, Devendra K. Sadana, Stephen W. Bedell, Ghavam G. Shahidi, Theodore van Kessel
  • Patent number: 10347611
    Abstract: A semiconductor package is provided which includes a redistribution substrate, an interconnect substrate on the redistribution substrate, a metal layer on the semiconductor chip, a semiconductor chip on the redistribution substrate and in the hole of the interconnect substrate, and a mold layer in a gap between the semiconductor chip and the interconnect substrate. The interconnect substrate includes a hole penetrating thereinside. The interconnect substrate includes base layers and a conductive member extending through the base layers. A top surface of the interconnect substrate is positioned either above or below the level of the top surface of the metal layer.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: July 9, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jichul Kim, Jae Choon Kim, Hansung Ryu, KyongSoon Cho, YoungSang Cho, Yeo-Hoon Yoon
  • Patent number: 10347513
    Abstract: Embodiments are related to systems and methods for fluidic assembly, and more particularly to systems and methods for assuring deposition of elements in relation to a substrate.
    Type: Grant
    Filed: January 1, 2018
    Date of Patent: July 9, 2019
    Assignee: eLux Inc.
    Inventors: Paul John Schuele, David Robert Heine, Mark Albert Crowder, Sean Mathew Garner, Changqing Zhan, Avinash Tukaram Shinde, Kenji Alexander Sasaki, Kurt Michael Ulmer
  • Patent number: 10319696
    Abstract: Methods of forming semiconductor device packages comprising stacking multiple dice, the die stack exhibiting thin bond lines and having an outer environmental coating, the bond lines and environmental coating comprising an in situ formed compound. Semiconductor device packages so formed and electronic systems incorporating such packages are also disclosed.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: June 11, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Eiichi Nakano
  • Patent number: 10276465
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a core substrate formed of a first material having a device-attach surface and a solder-bump-attach surface opposite to the die-attach surface. A bump pad is disposed on the bump-attach surface. A first solder mask layer formed of the first material covers the bump-attach surface of the core substrate and a portion of the bump pad. A second solder mask layer covers the device-attach surface of the core substrate, wherein the second solder mask layer is formed of a second material.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: April 30, 2019
    Assignee: MEDIATEK INC.
    Inventor: Shiann-Tsong Tsai
  • Patent number: 10256227
    Abstract: Disclosed are semiconductor devices that include additional gate pads, and methods of fabricating and testing such devices. A device may include a first gate pad, a second gate pad, and a third gate pad. The first gate pad is connected to a gate including a gate oxide layer. The second and third gate pads are part of an electro-static discharge (ESD) protection network for the device. The ESD protection network is initially isolated from the first gate pad and hence from the gate and gate oxide layer. Accordingly, gate oxide integrity (GOI) testing can be effectively performed and the reliability and quality of the gate oxide layer can be checked. The second gate pad can be subsequently connected to the first gate pad to enable the ESD protection network, and the third gate pad can be subsequently connected to an external terminal when the device is packaged.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: April 9, 2019
    Assignee: VISHAY-SILICONIX
    Inventors: Chanho Park, Ayman Shibib, Kyle Terrill
  • Patent number: 10192845
    Abstract: An electronic device includes an electronic element, a plurality of first sub-electrodes arrayed in a first direction, a plurality of second sub-electrodes arrayed in a second direction that is orthogonal to the first direction, a dummy electrode, and a sealing resin. The sealing resin has a resin back surface from which the plurality of first sub-electrodes, the plurality of second sub-electrodes and the dummy electrode are exposed. The plurality of second sub-electrodes are located further in the first direction than any of the plurality of first sub-electrodes. The plurality of first sub-electrodes are located further in the second direction than any of the plurality of second sub-electrodes. The dummy electrode is located further in the first direction than any of the plurality of first sub-electrodes, and is located further in the second direction than any of the plurality of second sub-electrodes.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: January 29, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Hiroaki Matsubara, Yasumasa Kasuya, Taro Nishioka
  • Patent number: 10153179
    Abstract: An embodiment method of forming a package-on-package (PoP) device includes temporarily mounting a substrate on a carrier, stacking a first die on the substrate, at least one of the die and the substrate having a coefficient of thermal expansion mismatch relative to the carrier, and stacking a second die on the first die. The substrate may be formed from one of an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, and a laminate substrate.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: December 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jing-Cheng Lin, Shih Ting Lin, Chen-Hua Yu
  • Patent number: 10150993
    Abstract: Provided herein is technology relating to depositing and/or placing a macromolecule at a desired site for an assay and particularly, but not exclusively, to methods and systems for placing or guiding a macromolecule such as a protein, a nucleic acid, or a protein: nucleic acid complex to an assay site, such as near a nanopore, a nanowell, or a zero mode waveguide.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: December 11, 2018
    Assignee: IBIS BIOSCIENCES, INC.
    Inventor: Mark A. Hayden
  • Patent number: 10114775
    Abstract: This application is directed to a stacked semiconductor device assembly including first and second integrated circuit (IC) devices. Each of the first and second IC devices further includes a master interface, a channel master circuit configured to receive read/write data using the master interface, a slave interface, a channel slave circuit configured to receive read/write data using the slave interface, a memory core coupled to the channel salve circuit, and a modal pad. The first and second IC devices are configured such that in response to at least a modal selection signal received at one of the modal pads of the first and second IC devices, one of the first and second IC devices is configured to receive read/write data using its respective charnel master circuit, and the other of the first and second IC devices is configured to receive read/write data using its respective channel slave circuit.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: October 30, 2018
    Assignee: RAMBUS INC.
    Inventor: Scott C. Best
  • Patent number: 10117306
    Abstract: A flexible display device includes: a display substrate including a plurality of protrusion portions and a plurality of recess portions at one surface thereof and curved surfaces respectively extending between ones of the plurality of protrusion portions towards a center of an adjacent one of the plurality of recess portions; a pixel unit configured to emit light on the display substrate; a first wiring coupled to the pixel unit and elongated in a first direction; and a second wiring elongated in a second direction crossing the first direction.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: October 30, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Byung Han Yoo
  • Patent number: 10083940
    Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a substrate. A first die is coupled beneath a lower surface of the substrate. A second die is coupled beneath the lower surface of the substrate and is disposed over the first die. A thermal contact pad is arranged beneath a lower surface of the second die and an upper surface of the first die. The thermal contact pad thermally isolates the first die from the second die.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: September 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Der-Chyang Yeh
  • Patent number: 9991342
    Abstract: The electronic device comprises a substrate (1), at least one semiconductor nanowire (2) and a buffer layer (3) interposed between the substrate (1) and said nanowire (2). The buffer layer (3) is at least partly formed by a transition metal nitride layer (9) from which extends the nanowire (2), said transition metal nitride being chosen from: vanadium nitride, chromium nitride, zirconium nitride, niobium nitride, molybdenum nitride, hafnium nitride or tantalum nitride.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: June 5, 2018
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, ALEDIA
    Inventors: Bérangère Hyot, Benoit Amstatt, Marie-Françoise Armand, Florian Dupont
  • Patent number: 9942979
    Abstract: A flexible printed circuit board (PCB) has stretchability and durability. The flexible PCB includes: a first polymer substrate having flexibility, stretchability, or elasticity; a second polymer substrate having flexibility, stretchability, or elasticity; a conductive track disposed between the first and second polymer substrates and including metal nanowires; and a cured silane coupling agent which bonds the conductive track to at least one of the first and second polymer substrates.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: April 10, 2018
    Assignees: SAMSUNG ELECTRONICS CO., LTD., RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Kyung-wan Park, Shi-yun Cho, Hyo-young Lee, Hyun-jung Kim, Mee-ree Kim, Ik-joon Kim
  • Patent number: 9905461
    Abstract: A system for interconnecting at least two die each die having a plurality of conducting layers and dielectric layers disposed upon a substrate which may include active and passive elements. In one embodiment there is at least one interconnect coupling at least one conducting layer on a side of one die to at least one conducting layer on a side of the other die. Another interconnect embodiment is a slug having conducting and dielectric layers disposed between two or more die to interconnect between the die. Other interconnect techniques include direct coupling such as rod, ball, dual balls, bar, cylinder, bump, slug, and carbon nanotube, as well as indirect coupling such as inductive coupling, capacitive coupling, and wireless communications. The die may have features to facilitate placement of the interconnects such as dogleg cuts, grooves, notches, enlarged contact pads, tapered side edges and stepped vias.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: February 27, 2018
    Assignee: GULA CONSULTING LIMITED LIABILITY COMPANY
    Inventor: Ernest E. Hollis
  • Patent number: 9892944
    Abstract: Embodiments are related to systems and methods for fluidic assembly, and more particularly to systems and methods for assuring deposition of elements in relation to a substrate.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: February 13, 2018
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Paul John Schuele, David Robert Heine, Mark Albert Crowder, Sean Mathew Garner, Changqing Zhan, Avinash Tukaram Shinde, Kenji Alexander Sasaki, Kurt Michael Ulmer
  • Patent number: 9859382
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to integrated CMOS wafers and methods of manufacture. The structure includes: a chip of a first technology type comprising a trench structure on a front side; a chip of a second technology type positioned within the trench structure and embedded therein with an interlevel dielectric material; and a common wiring layer on the front side connecting to both the chip of the first technology type and the chip of the second technology type.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: January 2, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anthony K. Stamper, Vibhor Jain, Renata A. Camillo-Castillo
  • Patent number: 9785582
    Abstract: A data processing architecture includes a processor which may access a memory and fetch a command recorded in the memory, transmit the fetched command to a subject configured to perform an operation corresponding to the fetched command through a network, and receive a result of performing the operation from the subject and record the result of performing the operation in the memory.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: October 10, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Chang Hyun Roh
  • Patent number: 9679870
    Abstract: An integrated circuit (IC) device includes an IC and encapsulating material surrounding the IC. Leads are coupled to the IC and extend outwardly from sides of the encapsulating material, with each lead having three contiguous exposed segments with upper and lower bends defining a Z-shape. In another example, the leads include an upper horizontal segment, lower horizontal segment, and intermediate curved segment extending upwardly from the upper horizontal segment and downwardly to the lower horizontal segment.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: June 13, 2017
    Assignee: STMicroelectronics Pte Ltd
    Inventors: Yiyi Ma, Kim-Yong Goh, Xueren Zhang, Wei Zhen Goh
  • Patent number: 9666516
    Abstract: An electronic package and a method of making the same in provided. The electronic package includes a dielectric layer and a conformal masking layer disposed on at least a portion of the dielectric layer. The electronic package further includes a routing layer disposed on at least a portion of the masking layer and a micro-via disposed at least in part in the conformal masking layer and the routing layer. Further, at least a portion of the routing layer forms a conformal electrically conductive layer in at least a portion of the micro-via. Also, the conformal masking layer is configured to define a size of the micro-via. The electronic package further includes a semiconductor die operatively coupled to the micro-via.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: May 30, 2017
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Scott Smith, Christopher James Kapusta, Glenn Alan Forman, Eric Patrick Davis
  • Patent number: 9620408
    Abstract: A semiconductor device having a semiconductor element (a thin film transistor, a thin film diode, a photoelectric conversion element of silicon PIN junction, or a silicon resistor element) which is light-weight, flexible (bendable), and thin as a whole is provided as well as a method of manufacturing the semiconductor device. In the present invention, the element is not formed on a plastic film. Instead, a flat board such as a substrate is used as a form, the space between the substrate (third substrate (17)) and a layer including the element (peeled layer (13)) is filled with coagulant (typically an adhesive) that serves as a second bonding member (16), and the substrate used as a form (third substrate (17)) is peeled off after the adhesive is coagulated to hold the layer including the element (peeled layer (13)) by the coagulated adhesive (second bonding member (16)) alone. In this way, the present invention achieves thinning of the film and reduction in weight.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: April 11, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junya Maruyama, Toru Takayama, Yuugo Goto
  • Patent number: 9570431
    Abstract: An embodiment semiconductor wafer includes a bottom semiconductor layer having a first doping concentration, a middle semiconductor layer over the bottom semiconductor layer, and a top semiconductor layer over the middle semiconductor layer. The middle semiconductor layer has a second doping concentration greater than the first doping concentration, and the top semiconductor layer has a third doping concentration less than the second doping concentration. A lateral surface of the bottom semiconductor layer is an external surface of the semiconductor wafer, and sidewalls of the bottom semiconductor layer, the middle semiconductor layer, and top semiconductor layer are substantially aligned.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: February 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Te Lee, Chung-Yi Yu, Jen-Cheng Liu, Kuan-Chieh Huang, Yeur-Luen Tu
  • Patent number: 9524932
    Abstract: Semiconductor chips are described that combine a semiconductor device and a capacitor onto a single substrate such that the semiconductor device and the capacitor are electrically isolated from each other. In one example, a semiconductor chip includes a substrate having a first side and a second side, wherein the second side is opposite the first side. The semiconductor chip further includes a semiconductor device formed on the first side of the substrate and an electrically insulating layer formed on at least a portion of the second side of the substrate. The semiconductor chip further includes a capacitor device formed on at least a portion of the electrically insulating layer on the second side of the substrate, wherein the capacitor device is electrically insulated from the semiconductor device.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: December 20, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Munding, Martin Gruber
  • Patent number: 9484239
    Abstract: Mechanisms are provided for sacrificial carrier dicing of semiconductor wafers. A bottom layer of a semiconductor wafer is bonded to a top layer of a sacrificial carrier. The semiconductor wafer is diced into a set of chips, such that the dicing cuts through the semiconductor wafer and into the sacrificial carrier and such that the sacrificial carrier dresses a diamond blade of a saw so as to expose one or more new, sharp layers of diamonds on the diamond blade.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: November 1, 2016
    Assignee: International Business Machines Corporation
    Inventors: Richard S. Graf, Douglas O. Powell, David J. Russell, David J. West
  • Patent number: 9478453
    Abstract: Mechanisms are provided for sacrificial carrier dicing of semiconductor wafers. A bottom layer of a semiconductor wafer is bonded to a top layer of a sacrificial carrier. The semiconductor wafer is diced into a set of chips, such that the dicing cuts through the semiconductor wafer and into the sacrificial carrier and such that the sacrificial carrier dresses a diamond blade of a saw so as to expose one or more new, sharp layers of diamonds on the diamond blade.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: October 25, 2016
    Assignee: International Business Machines Corporation
    Inventors: Richard S. Graf, Douglas O. Powell, David J. Russell, David J. West
  • Patent number: 9472411
    Abstract: A method of performing spalling of a semiconductor substrate in which a release layer is used between a handling substrate and a stressor layer. The release layer is removed using a liquid that does not damage the spalled semiconductor substrate.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: October 18, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Katherine L. Saenger
  • Patent number: 9472533
    Abstract: A semiconductor device has a first semiconductor die and a first encapsulant deposited over the first semiconductor die. An interconnect structure is formed over the first semiconductor die and first encapsulant. A modular interconnect structure including a conductive via is disposed adjacent to the first semiconductor die. The first encapsulant is deposited over the modular interconnect structure. An opening is formed in the first encapsulant extending to the modular interconnect structure or to the interconnect structure. A second semiconductor die is disposed over the first semiconductor die. A bond wire is formed over the second semiconductor die and extends into the opening in the first encapsulant. A cap is formed over an active region of the second semiconductor die. A second encapsulant is deposited over the second semiconductor die and bond wire. Alternatively, a lid is formed over the second semiconductor die and bond wire.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: October 18, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Rajendra D. Pendse
  • Patent number: 9412722
    Abstract: The present invention relates to a multichip stacking package structure and a method for manufacturing the same, wherein the multichip stacking package structure comprises a substrate including a plurality of electrical connecting pad; a first chip with a lower surface stacked on the substrate; a second chip stacked on an upper surface of the first chip by a interlaced reciprocation stacking way; a spacer stacked on an upper surface of the second chip by the interlaced reciprocation stacking way; and third chip stacked on the an upper surface of the spacer by the interlaced reciprocation stacking way, so that a first spacing is formed between an end of the third and an end of the spacer. Thereby, a position of a stress point is changed to reduce a risk of the chip crack during wire bonding.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: August 9, 2016
    Assignee: DAWNING LEADING TECHNOLOGY INC.
    Inventor: Diann-Fang Lin
  • Patent number: 9368683
    Abstract: A method of making an inorganic semiconductor structure suitable for micro-transfer printing includes providing a growth substrate and forming one or more semiconductor layers on the growth substrate. A patterned release layer is formed on the conductor layer(s) and bonded to a handle substrate. The growth substrate is removed and the semiconductor layer(s) patterned to form a semiconductor mesa. A dielectric layer is formed and then patterned to expose first and second contacts and an entry portion of the release layer. A conductor layer is formed on the dielectric layer, the first contact, and the second contact and patterned to form a first conductor in electrical contact with the first contact and a second conductor in electrical contact with the second contact but electrically separate from the first conductor. At least a portion of the release layer is removed.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: June 14, 2016
    Assignee: X-Celeprint Limited
    Inventors: Matthew Meitl, Ronald S. Cok
  • Patent number: 9337134
    Abstract: Reliability of a semiconductor device is improved. A semiconductor device has a base material comprised of insulating material having a through hole, a terminal formed on a lower surface of the base material, and a semiconductor chip mounted on an upper surface of the base material in a face-up manner. Further, the semiconductor device has a conductive member such as a wire, which electrically connects a pad of the semiconductor chip with an exposed surface of the terminal which is exposed from the through hole of the base material, and has a sealing body for sealing the conductive member, inside of the through hole of the base material, and the semiconductor chip. An anchor means is provided in a region of the exposed surface of the terminal which is exposed from the through hole of the base material except for a joint portion joined with the conductive member such as the wire.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: May 10, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Kenji Oyachi, Tamaki Wada, Yuichi Morinaga
  • Patent number: 8999807
    Abstract: A semiconductor component and methods for manufacturing the semiconductor component that includes a monolithically integrated common mode choke. In accordance with embodiments, a transient voltage suppression device may be coupled to the monolithically integrated common mode choke.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: April 7, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Li Jiang, Ryan J. Hurley, Sudhama C. Shastri, Yenting Wen, Wang-Chang Albert Gu, Phillip Holland, Der Min Liou, Rong Liu, Wenjiang Zeng
  • Patent number: 8987061
    Abstract: Methods for antenna switch modules are disclosed. In certain implementations, a method of making an antenna switch module is provided. The method includes providing a package substrate implemented to receive one or more electrical components, attaching a silicon on insulator (SOI) die to the package substrate, and providing an integrated filter. The SOI die includes a capacitor and a switch coupled to a plurality of radio frequency (RF) signal paths. The integrated filter filters an RF signal received on a first RF signal path of the plurality of RF signal paths, and includes the capacitor of the SOI die and an inductor.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: March 24, 2015
    Assignee: Skyworks Soultions, Inc.
    Inventors: Jong-Hoon Lee, Chuming Shih
  • Patent number: 8975118
    Abstract: An advantageous method and system for realizing electrically very reliable and mechanically extremely stable vias for components whose functionality is realized in a layer construction on a conductive substrate. The via (Vertical Interconnect Access), which is led to the back side of the component and which is used for the electrical contacting of functional elements realized in the layer construction, includes a connection area in the substrate that extends over the entire thickness of the substrate and is electrically insulated from the adjoining substrate by a trench-like insulating frame likewise extending over the entire substrate thickness. According to the present system, the trench-like insulating frame is filled up with an electrically insulating polymer.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: March 10, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Julian Gonska, Jens Frey, Heribert Weber, Eckhard Graf, Roman Schlosser
  • Patent number: 8970049
    Abstract: A module having multiple die includes a first die on a first substrate and an inverted second package stacked over the first die, with, where necessary, provision is made for a standoff between the second package and the first die. Also, methods for making the module include steps of providing a first package having a first die attached onto an upward facing side of a first package substrate, and stacking an inverted second package over the die on the first package, provision being made where necessary for a standoff between the second package and the first package die to avoid damaging impact between the downward-facing side of the second package and wire bonds connecting the first die to the first package substrate.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: March 3, 2015
    Assignee: ChipPAC, Inc.
    Inventor: Marcos Karnezos
  • Patent number: 8951888
    Abstract: A method for fabricating a semiconductor device includes a first step of forming, on a first substrate, a first element region in which a plurality of elements are collectively arranged, a second step of relocating the plurality of elements formed on the first substrate to a holding member in the same arrangement as in the first element region to have the plurality of elements held on the holding member, a third step of rearranging the plurality of elements held on the holding member and having the plurality of elements held on an intermediate substrate, thereby forming a second element region having a shape different from a shape of the first element region on the intermediate substrate, and a fourth step of dispersing the plurality of elements held on the intermediate substrate and adhering the plurality of elements to a second substrate.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: February 10, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Katsuyuki Suga
  • Patent number: 8916956
    Abstract: System and method for providing a multiple die interposer structure. An embodiment comprises a plurality of interposer studs in a molded interposer, with a redirection layer on each side of the interposer. Additionally, the interposer studs may be initially attached to a conductive mounting plate by soldering or wirebond welding prior to molding the interposer, with the mounting plate etched to form one of the redirection layers. Integrated circuit dies may be attached to the redirection layers on each side of the interposer, and interlevel connection structures used to mount and electrically connect a top package having a third integrated circuit to the interposer assembly.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: December 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Mirng-Ji Lii, Hao-Yi Tsai, Jui-Pin Hung, Chien-Hsun Lee, Kai-Chiang Wu
  • Patent number: 8889487
    Abstract: A three-dimensional (3D) gate driver integrated circuit includes a high-side integrated circuit stacked on a low-side integrated circuit where the high-side integrated circuit and the low-side integrated circuit are interconnected using through-silicon vias (TSV). As thus formed, the high-side integrated circuit and the low-side integrated circuit can be formed without termination regions and without buried layers. The 3D gate driver integrated circuit improves ease of high voltage integration and improves the ruggedness and reliability of the gate driver integrated circuit.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: November 18, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Shekar Mallikarjunaswamy
  • Patent number: 8889482
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. The present process can fabricate multiple components separately before assembling them into a complete integrated circuit. In an aspect, the ready-for-assembling components are taken directly from processed wafers without any additional assembling processes, and/or having lateral dimensions less than 1 mm.
    Type: Grant
    Filed: June 14, 2009
    Date of Patent: November 18, 2014
    Inventor: Jayna Sheats