STRUCTURE AND METHOD OF THREE DIMENSIONAL HYBRID ORIENTATION TECHNOLOGY
A method and device for increasing pFET performance without degradation of nFET performance. The method includes forming a first structure on a substrate using a first plane and direction and forming a second structure on the substrate using a second plane and direction. In use, the device includes a nFET stack on a substrate using a first plane and direction, e.g., (100)<110> and a pFET stack on the substrate using a second plane and direction, e.g., (111)/<112>. An isolation region within the substrate is provided between the nFET stack and the pFET stack.
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This application is a divisional of U.S. patent application Ser. No. 10/907,622, filed Apr. 8, 2005, the disclosure of which is expressly incorporated by reference herein in its entirety.
BACKGROUND OF THE INVENTION1. Field of the Invention
The invention relates to semiconductor devices, and more particularly to semiconductor devices having increased pFET performance without degradation of the nFET performance and a method of manufacture.
2. Background Description
Field effect transistors (FET's) are a fundamental building block in the field of integrated circuits. FET's can be classified into two basic structural types: horizontal and vertical. Horizontal, or lateral, FET's exhibit carrier flow from source to drain in a direction parallel (e.g., horizontal) to the plane of the substrate and vertical FET's exhibit carrier flow from source to drain in a direction transverse to the plane of the substrate (e.g., vertical) on which they are formed. FET structures may include a single gate (e.g., for forming a single channel) or a pair of gates (e.g., for forming a pair of channels), with double-gate versions providing an advantage of an increased current carrying capacity (e.g. typically greater than twofold over the single-gate versions).
A FET typically consists of source and drain electrodes interconnected by semiconductor material. Conduction between the drain and source electrodes occurs basically within the semiconductor, and the length between the source and drain is the conduction channel. In particular, the output current is inversely proportional to the channel length, while the operating frequency is inversely proportional to the square of the channel length.
The basic metal-oxide-semiconductor field-effect transistor (MOSFET) structure has a so-called “flat design”. A nFET structure is a four-terminal device and consists of a p-type semiconductor substrate, into which two n-regions, a source electrode and drain electrode are formed (e.g., by ion implantation). The metal contact on the insulator is a gate. Heavily doped polysilicon or a combination of silicide and polysilicon can also be used as the gate electrode.
The basic device parameters are the channel length L, which is the distance between the two metallurgical n-p junctions, the channel width W, the gate oxide thickness t, the junction depth, and the substrate doping. When voltage is applied to the gate, the source-to-drain electrodes correspond to two p-n junctions connected back to back. The only current that can flow from source to drain is the reverse leakage current. When a sufficiently positive bias is applied to the gate so that a surface inversion layer (or channel) is formed between the two n-regions, the source and the drain are connected by the conducting surface of the n-channel through which a current can flow.
It is known, though, that the nFETs are optimized in the horizontal plane of the substrate. That is, the electron mobility across the channel is optimized when the nFET is fabricated on the 100 plane and the 110 direction. This is a typical flat structure fabrication. The pFET device, on the other hand, has significantly decreased performance characteristics when it is fabricated on the 100 plane and the 110 direction; namely, the hole mobility is significantly decreased, thereby degrading the performance of the entire device. However, it is typical in semiconductor fabrication to build both the nFET and pFET structures in the 100 plane and the 110 direction, using well-known processes.
SUMMARY OF THE INVENTIONIn a first aspect of the invention, a method of fabricating a semiconductor structure comprising forming a first structure on a substrate using a first plane and direction and forming a second structure on the substrate using a second plane and direction.
In another aspect of the invention, a method of manufacturing a semiconductor device comprising building a nFET stack on a substrate using a first plane and direction and building a pFET stack on the substrate using a second plane and direction, different from the first plane and first direction. The method further includes providing an isolation region within the substrate between the nFET stack and the pFET stack.
In another aspect of the invention, a semiconductor structure includes a nFET stack on a substrate using a first plane and direction and a pFET stack on the substrate using a second plane and direction, different from the first plane and first direction. An isolation region within the substrate is provided between the nFET stack and the pFET
BRIEF DESCRIPTION OF THE DRAWINGS
The invention is directed to semiconductor structures and more particularly to semiconductor structures and methods of manufacture using three dimensional hybrid orientation technologies. In one aspect of the invention, the performance of a pFET is improved or optimized by increasing carrier mobility for the pFET without any degradation in the performance of the nFET. To accomplish the invention, the nFET is formed in a first plane/direction and the pFET is formed in a second plane/direction using similar processing steps. For example, in one non-limiting aspect of the invention, the nFET will be formed in the (100)/<110> plane/direction and the pFET will be formed in the (111)/<112> plane/direction. In this manner, the channel length of the pFET may be longer than the channel length of nFET using the same processes. The invention is compatible with CMOS technologies such as, for example, SOI, strained Si, dual spacer and the like.
By an exemplary illustration, the STI 12 may be formed by depositing a pad oxide and pad nitride over the substrate 10. A photo mask or a hard mask is formed over the pad nitride and an etching process etches to the substrate through the formed layers. An additional etching process etches into the substrate to form the trench. An oxide, for example, is deposited in the trench to fill the trench. The surface is planarized using a chemical mechanical polishing (CMP) process. The pad nitride may then be removed, resulting in the structure of
In
The photoresist layer 18 is then stripped using a dry stripping process, for example (
Referring to
In
Referring to
It has been found that the hole mobility for a pFET in the (111) plane and <112> direction is superior than in the (100) plane and <110> direction, but worse than in the (110) plane and <110> direction; whereas, the electron mobility for a nFET in the (111) plane and <112> direction is worse than in the (100) plane and <110> direction, but superior than in the (110) plane and <110> direction. To thus optimize the pFET performance without degrading the nFET performances, in the present invention, the pFET is formed in the (111) plane and the <112> direction and the nFET is optimized in the (100) plane and the <110> direction.
While the invention has been described in terms of exemplary embodiments, those skilled in the art will recognize that the invention can be practiced with modifications and in the spirit and scope of the appended claims.
Claims
1. A method of manufacturing a semiconductor structure, comprising forming a first structure from a poly layer on a substrate using a first plane and direction and forming a second structure from the poly layer on the substrate using a second plane and direction.
2. The method of claim 1, wherein the first structure is a stack for a nFET and the second structure is a stack for a pFET.
3. The method of claim 1, wherein the first plane and direction differ from the second plane and direction and the first structure and the second structure are formed simultaneously.
4. The method of claim 3, wherein the first plane and direction is (100)/<110> and the second plane and direction is (111)/<112>.
5. The method of claim 1, wherein forming the second structure on the substrate using a second plane and direction comprises etching the substrate to form an angled sidewall and building the second structure at least partially on the angled sidewall.
6. The method of claim 5, wherein forming the angled sidewall comprises an anisotropic etching of the substrate at an active area of a pFET.
7. The method of claim 5, wherein forming the angled sidewall comprises etching the substrate to result in an angled of approximately 57.5 degrees from a plane of the substrate.
8. The method of claim 5, wherein the forming of the angled sidewall comprises etching through an oxide layer deposited over the substrate, a block material deposited over the oxide layer and into the substrate.
9. The method of claim 8, further comprising:
- etching a photoresist deposited over the block material,
- performing a selective etch of the block material using the oxide layer as a etch stop layer to form an etched area;
- stripping the photoresist layer;
- forming a spacer in the etched area; and
- anisotropic etching the substrate to a depth of approximately 200 Å to 900 Å to form a trench in the substrate which has the angled sidewall.
10. The method of claim 1, wherein forming the first structure and the second structure comprises:
- forming at least one n-well and one p-well for pFET and nFET devices, respectively;
- depositing a gate dielectric on a surface of the substrate including in a trench with an angled sidewall with respect to a plane of the surface of the substrate, the trench is formed in an active area of the pFET;
- depositing the poly layer over the gate dielectric;
- etching portions of the poly layer to form a nFET stack comprising the first structure on a plane of the substrate and a pFET stack comprising the second structure on the angled sidewall of the trench;
- forming spacers on sidewalls of the nFET stack and the pFET stack; and
- doping source and drain regions in the substrate for nFET and pFET devices on sides of the nFET stack and the pFET stack, respectively.
11. The method of claim 10, wherein the pFET stack and the nFET stack are in a (111) plane and a <112> direction and in a (100) plane and <110> direction.
12. A method of manufacturing a semiconductor device, comprising:
- building a nFET stack on a gate dielectric layer on a substrate in a first plane and direction;
- building a pFET stack on the gate dielectric layer on the substrate in a second plane and direction, which is different from the first plane and direction; and
- providing an isolation region within the substrate between the nFET stack and the pFET stack.
13. The method of claim 12, wherein the first plane and direction is (100)/<110> and the second plane and direction is (111)/<112>.
14. The method of claim 12, wherein forming the pFET stack comprises etching the substrate to form a trench with an angled sidewall and building the pFET stack at least partially on the angled sidewall.
15. The method of claim 14, wherein forming the angled sidewall comprises anisotropic etching of the substrate using basic wet chemicals at an active area of a pFET.
16. The method of claim 14, wherein the angled sidewall is etched at an angle of approximately 57.5 degrees from a plane of the substrate.
17. The method of claim 14, wherein the forming of the angled sidewall comprises:
- etching through an oxide layer deposited over the substrate, a block material deposited over the oxide layer using the oxide layer as a etch stop layer to form an etched area;
- stripping a photoresist deposited over the block material after etching the block material,
- forming a spacer in the etched area; and
- anisotropic etching the substrate using wet chemicals to a depth of approximately 200 Å to 900 Å to form the trench in the substrate having the angled sidewall.
18. The method of claim 14, wherein forming the nFET stack and the pFET stack comprises:
- forming at least one n-well and one p-well for pFET and nFET, respectively;
- depositing the gate dielectric layer on a surface of the substrate including in the trench with an angled sidewall with respect to a plane of the surface of the substrate, the trench being formed in an active area of the pFET;
- depositing a poly layer over the gate dielectric layer;
- etching portions of the poly layer to form the nFET stack and the pFET stack on the angled sidewall of the trench using an isolation region as a basis for alignment;
- forming spacers on sidewalls of the nFET stack and the pFET stack;
- implanting extensions in the substrate on the side of the nFET stack and the pFET stack; and
- doping source and drain regions in the substrate for nFET and pFET on sides of the nFET stack and the pFET stack, respectively.
19. A method of manufacturing a semiconductor structure, comprising:
- depositing a gate dielectric layer on a substrate;
- depositing a poly layer on the gate dielectric layer on the substrate; and
- forming a nFET structure from the poly layer on the gate dielectric layer on the substrate in a first plane and direction; and
- forming a pFET structure from the poly layer on the gate dielectric layer on the substrate in a second plane and direction, which is different from the first plane and direction.
20. The method of claim 19, wherein the nFET structure and the pFET structure are formed simultaneously.
Type: Application
Filed: May 18, 2007
Publication Date: Sep 27, 2007
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION (Armonk, NY)
Inventor: Oh-jung KWON (Hopewell Junction, NY)
Application Number: 11/750,830
International Classification: H01L 21/8238 (20060101);