Interposer and electronic device using the same
A novel interposer(10) includes a silicon substrate(12), a plurality of through-hole conductors (20) formed on the silicon substrate, and capacitors (15) having of upper and lower electrodes (14,18) formed with land portions, respectively, of the through-hole conductors, and a dielectric layer (16) formed between both the electrodes. When desired, wiring pattern layers can be formed on a layer separate from the capacitors.
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1. Field of the Invention
The present invention relates to an interposer and an electronic device using it, and, more particularly, to an interposer interposed between a semiconductor chip and a package substrate as well as to an electronic device composed of a combination of the semiconductor chip, the interposer, and the package substrate.
2. Description of the Related Art
There is conventionally known an interposer utilizing a printed wiring board for carrying out wiring between a semiconductor chip and a package substrate. The interposer is a wiring device used to mutually connect a conductor circuit of a semiconductor chip which has an ultra dense pitch (for example, 50 μm) and a conductor circuit of a package substrate (also referred to as “mounting substrate”) which has a pitch more coarse than the above pitch (for example, 150 μm).
Recently, an example of an interposer including a capacitor is disclosed in Japanese Patent Laid-open Publication No. 2001-326305 entitled “Interposer for Semiconductor Device, Method of Manufacturing the Same, and Semiconductor Device (published on Nov. 22, 2001).
Claim 1 of the Laid-open publication states “An interposer for a semiconductor device having first electrodes, dielectric layers formed on the first electrodes, and second electrodes formed on the dielectric layer, characterized in that a necessary number of capacitors composed of the first electrodes, the dielectric layers, and the second electrodes are formed on the interposer”.
The Japanese Patent laid-open Publication describes “Further, since a wiring is carried out by a wiring pattern on the interposer, a fine pattern can be achieved. Accordingly, since the wiring is carried out on the interposer, it is possible to reduce one layer from the layers on a mounting substrate made by a multilayer board” (see paragraph 0006).
SUMMARY OF THE INVENTIONHowever, the inventor has found by his study carried out thereafter that various problems may arise when a capacitor and a wiring layer are formed together on the interposer as disclosed in the Japanese Patent laid-open Publication.
Accordingly, an object of the present invention is to provide a novel interposer and electronic device using it.
An interposer of the present invention comprises a capacitor formed on a generally entire surface of a substrate.
The interposer may comprise the substrate including a plurality of through-hole conductors; some of the through hole conductors that have land portions formed with an upper electrode of the capacitors; some of the remaining of the through-hole conductors that have land portions formed with a lower electrode of the capacitor; and a dielectric layer interposed between the upper electrodes and the lower electrodes.
In the interposer, some of the through-hole conductors may be formed as through-hole conductors for signal on a central portion of the surface of the substrate, and through-hole conductors for power supply for forming one of the upper and lower electrodes and through-hole conductors for ground for forming the other of the upper and lower electrodes may be formed surrounding the through-hole conductors for signal.
In the interposer, some of the through-hole conductors may be formed as through-hole conductors for signal on a peripheral region of the surface of the substrate, and through-hole conductors for power supply for forming one of the upper and lower electrodes and through-hole conductors for ground for forming the other of the upper and lower electrodes may be formed inside of the peripheral region.
The interposer may further comprise a wiring layer that is formed on at least one insulating layer disposed above the capacitors.
In the interposer, the substrate may be a silicon substrate.
In the interposer, the through-hole conductors may be made of copper.
In the interposer, the upper and lower electrodes may be made of nickel or platinum.
In the interposer, the dielectric layer may be made of a ferroelectric substance.
In the interposer, the dielectric layer may be made of barium titanate.
In the interposer, at least one surface of the interposer may be covered with a solder resist layer or an insulating resin layer.
An electronic device of the present invention comprises an IC chip; a package substrate; and an interposer, according to claim 1 or 2, interposed between the IC chip and the package substrate and electrically connected to the both, wherein the interposer provides capacitors.
According to the present invention, there are provided the novel interposer and the electronic device using it.
Embodiments of novel interposers and electronic devices using the interposers according to the present invention will be explained below in detail with reference to the accompanying drawings. It should be understood that the embodiments are only exemplified and the present invention is not limited thereto. Also, note that, in the drawings, the same components are denoted by the same reference numerals to omit duplicate explanation.
[Interposer]When the surface of the silicon substrate 12 is properly polished, it has such a property that the surface is very flat and smooth. Alternatively a glass substrate and a polyimide substrate may be used in place of the silicon substrate when they satisfy the level of a surface flatness required in this embodiment.
The through-hole conductors 20-1 of the through-hole conductors 20 formed on the silicon substrate 12 are conductors for signal supply and transmit a signal between a semiconductor chip (not shown) and a package substrate (not shown) as described later. The through-hole conductors 20-2 are conductors for power supply, and the land portions of the through-hole conductors 20-2 extend to form, for example, the lower broad electrodes 18. The through-hole conductors 20-3 are conductors for ground (GND), and the land portions of the through-hole conductors 20-3 extend to form, for example, the upper broad electrodes 14.
Alternatively, the upper electrodes 14 may be formed as the land portions of the through-hole conductors 20-2 for power supply, while the lower electrodes 18 may be formed as the land portions of the through-hole conductors 20-3 for GND.
The upper and lower electrodes 14, 18 each are formed of an appropriate metal. In this embodiment the upper electrodes 14 are formed of, for example, nickel (Ni), and the lower electrodes 18 are formed of, for examples, platinum (Pt), for convenience of production. However, they may be formed of other metals.
The dielectric layer 16 is preferably composed of a high dielectric substance, for example, barium titanate (BaTiO3) having ferroelectricity.
Here, the upper electrodes 14 (the land portions of the through-hole conductors 20-3 for GND), the dielectric layer 16, and the lower electrodes 18 (or the land portions of the through-hole conductors 20-2 for power supply) form capacitors 15.
As described later, the interposer 10 shown in
A features of the interposer 10 shown in
Further, since the silicon substrate 12 used for the interposer 10 shown in
Further, a barium titanate (BaTIO3) layer being of ferroelectricity can be employed as the dielectric layer 16 used for the interposer 10 shown in
The interposer 10 shown in
As shown in
Alternatively, the through-hole conductors 20-1, the through-hole conductors 20-2, and the through-hole conductors 20-3 may be disposed in mixture.
In addition to the upper electrodes 14, the dielectric layer 16, the lower electrodes 18, the silicon substrate 12, and the through-hole conductors 20 explained in relation to
The interposer 10 shown in
In addition to the upper electrodes 14, the dielectric layer 16, the lower electrodes 18, the silicon substrate 12, the through-hole conductors 20, the solder bumps 26, the solder resist layer 28, and the solder bumps 30 explained in relation to
However, the wiring patterns 23-1, 23-2 are formed on the layers different from those of the capacitors 15 (i.e. on the interlayer insulating resin layers 21-1, 21-2). That is, since no wiring pattern exists in the capacitors 15 formed by the upper electrodes 14, the dielectric layer 16, and the lower electrodes 18, capacitor electrodes having a large area can be still formed.
Accordingly, the interposer 10 shown in
Although a method of manufacturing the interposers 10 shown in
The interposer 10 shown in
After the interposer 10 is manufactured, the electronic device 70 is formed by subjecting the solder bumps 26, 30 to reflow and connecting the interposer 10 to the semiconductor chip 40 and the package substrate 42, respectively, by soldering. The interposer 10 is located in the vicinity of the semiconductor chip 40 and functions as the decoupling capacitor having a large capacity.
The interposer 10 shown in
The interposers 10 according to the embodiments possess the following features and advantages.
(1) Because of no wiring pattern that occupies the surface of the silicon substrate 12, the electrodes for capacitor having a large area can be formed.
(2) Since the silicon substrate 12 has very flat and smooth surface, the dielectric layer 16 can be formed very thin, whereby the space between the upper electrodes 14 and the lower electrodes 18 can be formed very narrow.
(3) A ferroelectric material, for example, barium titanate (BaTiO3), can be used for the dielectric layer 16 of the interposer 10.
(4) The interposer 10 can provide capacitors (condenser) having a very large capacity by employing at least one of the above factors.
The electronic devices according to the embodiments has the following features and advantages.
(1) Noise can be absorbed by providing a decoupling capacitor having large capacity that is connected between the power supply and the ground at a position very near the semiconductor chip 40 in the devices composing the combination of the semiconductor chip 40, the interposer 10, and the package substrate 42.
(2) The wiring layers 23-1, 23-2 can be also provided by using the interposer 10 explained in relation to
The embodiments of the interposers and the electronic devices making use of the interposers according to the present invention have been explained above. It should be noted that they are only examples, and the present invention is not limited thereto.
The technical scope of the present invention should be determined according to the description of the accompanying claims.
Claims
1. An interposer comprising a capacitor formed on a generally entire surface of a substrate.
2. The interposer according to claim 1, comprising:
- the substrate including a plurality of through-hole conductors;
- some of the through hole conductors that have land portions formed with an upper electrode of the capacitors;
- some of the remaining of the through-hole conductors that have land portions formed with a lower electrode of the capacitor; and
- a dielectric layer interposed between the upper electrodes and the lower electrodes.
3. The interposer according to claim 2, wherein
- some of the through-hole conductors are formed as through-hole conductors for signal on a central portion of the surface of the substrate, and
- through-hole conductors for power supply for forming one of the upper and lower electrodes and through-hole conductors for ground for forming the other of the upper and lower electrodes are formed surrounding the through-hole conductors for signal.
4. The interposer according to claim 2, wherein
- some of the through-hole conductors are formed as through-hole conductors for signal on a peripheral region of the surface of the substrate, and
- through-hole conductors for power supply for forming one of the upper and lower electrodes and through-hole conductors for ground for forming the other of the upper and lower electrodes are formed inside of the peripheral region of the surface of the substrate.
5. The interposer according to claim 1 or 2, further comprising a wiring layer that is formed on at least one insulating layer disposed above the capacitors.
6. The interposer according to claim 1 or 2, wherein the substrate is a silicon substrate.
7. The interposer according to claim 1 or 2, wherein the through-hole conductors are made of copper.
8. The interposer according to claim 1 or 2, wherein the upper and lower electrodes are made of nickel or platinum.
9. The interposer according to claim 1 or 2, wherein the dielectric layer is made of a ferroelectric substance.
10. The interposer according to claim 1 or 2, wherein the dielectric layer is made of barium titanate.
11. The interposer according to claim 1 or 2, wherein at least one surface of the interposer is covered with a solder resist layer or an insulating resin layer.
12. An electronic device comprising
- an IC chip;
- a package substrate; and
- an interposer, according to claim 1 or 2, interposed between the IC chip and the package substrate and electrically connected to the both,
- wherein the interposer provides capacitors.
Type: Application
Filed: Jul 24, 2006
Publication Date: Jan 24, 2008
Applicant: IBIDEN CO., LTD. (Ogaki)
Inventor: Shuichi Kawano (Ogaki)
Application Number: 11/491,288
International Classification: H05K 1/16 (20060101);