With Electrical Device Patents (Class 174/260)
  • Patent number: 10734323
    Abstract: A package structure includes at least one integrated circuit component, an insulating encapsulation, and a redistribution structure. The at least one integrated circuit component includes a semiconductor substrate, an interconnection structure disposed on the semiconductor substrate, and signal terminals and power terminals located on and electrically connecting to the interconnection structure. The interconnection structure is located between the semiconductor substrate and the signal terminals and between the semiconductor substrate and the power terminals, and where a size of the signal terminals is less than a size of the power terminals. The insulating encapsulation encapsulates the at least one integrated circuit component. The redistribution structure is located on the insulating encapsulation and electrically connected to the at least one integrated circuit component.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Wen Lin, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang, Che-Wei Hsu
  • Patent number: 10734344
    Abstract: A chip structure including a chip body and a plurality of conductive bumps. The chip body includes an active surface and a plurality of bump pads disposed on the active surface. The conductive bumps are disposed on the active surface of the chip body and connected to the bump pads respectively, and at least one of the conductive bumps has a trapezoid shape having one pair of parallel sides and one pair of non-parallel sides.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: August 4, 2020
    Assignee: Novatek Microelectronics Corp.
    Inventors: Ling-Chieh Li, Chiao-Ling Huang
  • Patent number: 10706204
    Abstract: A method of performing automated surface-mount package design includes obtaining physical inputs that include names and locations of top and bottom pins, and obtaining electrical inputs that include electrical parameters such as impedance. The method also includes automatically performing analysis and processing of the physical inputs and the electrical inputs. A design file for manufacture of the surface-mount package is automatically generated based on the performing the analysis and the processing. The design file specifies a number and material of layers of the surface-mount package.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: July 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jean Audet, Alain Ayotte, Franklin Baez, Anson Call, Deana Cosmadelis, Jason Lee Frankel, Kevin Grosselfinger, Roxan Lemire, Marek Andrzej Orlowski, Gilles Poitras, Paul Robert Walling
  • Patent number: 10707023
    Abstract: An electronic component includes: a plurality of multilayer capacitors stacked in multiple rows and columns and each having external electrodes on both ends thereof in a first direction; and a board including a body and a connection portion. The connection portion includes: a plurality of positive electrode land patterns; a plurality of negative electrode land patterns; positive and negative electrode terminal patterns formed on a lower surface of the body to be spaced apart from each other in the first direction; a positive electrode connection portion connecting the plurality of positive electrode land patterns to the positive electrode terminal pattern; and a negative electrode connection portion connecting the plurality of negative electrode land patterns to the negative electrode terminal pattern.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: July 7, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ho Yoon Kim, Jae Yeol Choi, Soo Hwan Son
  • Patent number: 10707145
    Abstract: Provided is a high density multi-component package and a method of manufacturing a high density multi-component package. The high density multi-component package comprises at least two electronic components wherein each electronic component of the electronic components comprise a first external termination and a second external termination. At least one interposer is between the adjacent electronic components and attached to the interposer by an interconnect wherein the interposer is selected from an active interposer and a mechanical interposer. Adjacent electronic components are connected serially.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: July 7, 2020
    Assignee: KEMET Electronics Corporation
    Inventors: John Bultitude, Galen Miller, John E. McConnell
  • Patent number: 10705028
    Abstract: In order to inspect a substrate, an image information of a substrate before applying solder is displayed. Then, at least one inspection region on the substrate is image-captured to obtain an image of the inspection region that is image-captured. Then, image information that is to be displayed is renewed and the renewed image information is displayed. And, in order to inspect a foreign substance, obtained image of the inspection region is compared with a reference image of the substrate. Therefore, an operator can easily catch a region corresponding to a specific region of the image that is displayed, and easily detect a foreign substance on the substrate.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: July 7, 2020
    Assignee: KOH YOUNG TECHNOLOGY INC.
    Inventors: Hyun-Seok Lee, Jae-Sik Yang, Ja-Geun Kim, Hee-Tae Kim, Hee-Wook You
  • Patent number: 10702913
    Abstract: The disclosure is related to various connecting methods for a welding auxiliary joining part having a head and a rounded tip for setting in at least one first component having a die as counter-bearing, which has a concave recess with an inner wall having at least in sub-areas an arc shape and having a matrix radius MR in the range from 1.0 mm?MR?60 mm, for preparing a subsequent welding method. The geometry of the welding auxiliary joining part and the die meet the following condition: 0.001 ? SR MR ? 0.1 , in particular 0.002 ? SR MR ? 0.08 , wherein SR designates a tip radius of the rounded tip of the welding auxiliary joining part.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: July 7, 2020
    Assignee: Böllhoff Verbindungstechnik GmbH
    Inventors: Sergej Hartwig-Biglau, Torsten Draht
  • Patent number: 10685897
    Abstract: A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer. The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: June 16, 2020
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Won Bae Bang, Byong Jin Kim, Gi Jeong Kim, Jae Doo Kwon, Hyung Il Jeon
  • Patent number: 10681814
    Abstract: Provided is a high density multi-component package and a method of manufacturing a high density multi-component package. The high density multi-component package comprises at least two electronic components wherein each electronic component of the electronic components comprise a first external termination and a second external termination. At least one interposer is between the adjacent electronic components and attached to the interposer by an interconnect wherein the interposer is selected from an active interposer and a mechanical interposer. Adjacent electronic components are connected serially.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: June 9, 2020
    Assignee: KEMET Electronics Corporation
    Inventors: John Bultitude, Galen W. Miller, John McConnell
  • Patent number: 10679766
    Abstract: A printed circuit board has a printed wiring board and a semiconductor package mounted on the printed wiring board. The printed wiring board and the semiconductor package are connected with a plurality of solder balls. An underfill material covering the plurality of solder balls is filled between the printed wiring board and the semiconductor package. The underfill material has a relative dielectric constant of 8.6 or more and 54.4 or less. Thus, crosstalk noise generated in wiring in the out-of-plane direction is reduced without increasing the mounting area.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: June 9, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takuya Kondo, Shoji Matsumoto, Seiji Hayashi
  • Patent number: 10667397
    Abstract: An electronic device, and methods of manufacturing the same are disclosed. The method of manufacturing the electronic device includes forming a first metal layer on a first substrate, forming an integrated circuit or a discrete electrical component on a second substrate, forming electrical connectors on input and/or output terminals of the integrated circuit or discrete electrical component, forming a second metal layer on the first metal layer, the second metal layer improving adhesion and/or electrical connectivity of the first metal layer to the electrical connectors on the integrated circuit or discrete electrical component, and electrically connecting the electrical connectors to the second metal layer.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: May 26, 2020
    Assignee: Thin Film Electronics ASA
    Inventor: Mao Ito
  • Patent number: 10667395
    Abstract: According to one embodiment, an interposer substrate for switching wiring lines, includes a substrate body having through holes penetrating from a first main surface thereof to a second main surface, through-conductive portions provided respectively in the through holes, grouped into first groups and second groups different from the first groups, first wiring lines each provided on the first main surface and for a respective one of the first groups, second wiring lines each provided on the second main surface and for a respective one of the second groups, first terminals provided on the first main surface and connected respectively to the first wiring lines, and second terminals provided on the second main surface and connected respectively to the second wiring lines.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: May 26, 2020
    Assignee: Toshiba Electronic Devices & Storage Corporation
    Inventors: Ryoji Ninomiya, Kenichi Agawa
  • Patent number: 10667380
    Abstract: A PCB and a signal transmission system are provided. The PCB includes a connection module, and at least two signal layers and at least two reference layers spaced apart. The connection module comprises a first connection terminal and a second connection terminal. The first connection terminal is connected to at least one first signal layer and is connectable to an external optical interface. The second connection terminal is connected to at least one second signal layer and is connectable to an external electrical interface. Each reference layers is provided with a through-hole, and for each reference layers, there is an overlapping region between a projection region of an orthogonal projection of the connection module onto the reference layer and a hole region of the through-hole arranged on the reference layer.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: May 26, 2020
    Assignee: ZHENGZHOU YUNHAI INFORMATION TECHNOLOGY CO., LTD.
    Inventor: Junyang Li
  • Patent number: 10665370
    Abstract: A co-wound resistor with a low parasitic inductance includes a first resistive strip having an input and a second resistive strip having an output. The second resistive strip has a similar shape as the first resistive strip. The second resistive strip is co-wound in a same direction as the first resistive strip. The second resistive strip and the first resistive strip are configured to generate a mutual inductance that cancels an inductance of the first resistive strip and the second resistive strip. The first interconnect coupling the first resistive strip to the second resistive strip. The first resistive strip, the second resistive strip and the first interconnect are on a same level.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: May 26, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Haitao Cheng, Chao Song, Ye Lu
  • Patent number: 10658200
    Abstract: A thin film component sheet includes: a conducting interconnection layer formed of a conductor; an insulating layer that is laminated on the conducting interconnection layer and is formed of an insulating material; and a plurality of thin film electronic components, each of which has a pair of first and second electrode layers and a dielectric layer provided between the first and second electrode layers, and which are arranged to be separated on the insulating layer. In a state in which a main surface of the first electrode layer in each of the plurality of thin film electronic components is exposed to an outside on a main surface of one side of the thin film component sheet, a flat surface of the main surface of the thin film component sheet is formed.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: May 19, 2020
    Assignee: TDK CORPORATION
    Inventor: Hitoshi Saita
  • Patent number: 10649591
    Abstract: A touch controller includes a touch data generator that is connected to a plurality of sensing lines, the touch data generator sensing a change in capacitance of a sensing unit connected to each of the sensing lines and generating touch data by processing the sensing signal corresponding to the result of sensing; and a signal processor that controls a timing of generating the touch data by receiving at least one piece of timing information for driving a display panel from a timing controller, and then providing either the timing information or a signal generated from the timing information as a control signal to the touch data generator.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: May 12, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyoung-rae Kim, Yoon-kyung Choi, Hwa-hyun Cho, Sang-woo Kim, Hae-yong Ahn, Hyung-dal Kwon, Jong-kang Park, San-ho Byun, Jae-suk Yu
  • Patent number: 10643861
    Abstract: A method is provided. The method includes attaching a bridge layer to a first substrate. The method also includes forming a first connector, the first connector electrically connecting the bridge layer to the first substrate. The method also includes coupling a first die to the bridge layer and the first substrate, and coupling a second die to the bridge layer.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Sen Chang, Yu-Feng Chen, Chen-Shien Chen, Mirng-Ji Lii
  • Patent number: 10643949
    Abstract: A component carrier including an electrically insulating core, at least one electronic component embedded in the core, and a coupling structure with at least one electrically conductive through-connection extending at least partially therethrough and having a component contacting end and a wiring contacting end. The electronic component directly contacts the component contacting end. The wiring contacting end is directly electrically contacted to the wiring structure. The exterior surface portion of the coupling structure has homogeneous ablation properties and surface recesses filled with an electrically conductive wiring structure.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: May 5, 2020
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventor: Hannes Stahr
  • Patent number: 10636564
    Abstract: A receiving antenna of a wireless power receiving apparatus for wireless power charging according to one embodiment of the present invention comprises: a substrate; a soft magnetic layer disposed on the substrate; and a receiving coil which is wound in parallel with a plane of the soft magnetic layer and is embedded on one surface of the soft magnetic layer, wherein at least one surface of the receiving coil is slantly embedded on the one surface of the soft magnetic layer.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: April 28, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Jung Eun Lee, Sang Won Lee, Seok Bae, Soon Young Hyun, Hee Jung Lee
  • Patent number: 10637334
    Abstract: A printed circuit board includes a body, a first conductive pattern layer disposed on a first surface of the body, and a second conductive pattern layer disposed on a second surface of the body. The first conductive pattern layer and the second conductive pattern layer form a capacitor. The present disclosure further provides an motor having the printed circuit board.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: April 28, 2020
    Assignee: JOHNSON ELECTRIC INTERNATIONAL AG
    Inventors: Qing Bin Luo, Chi Wai Lai, Wen Ming Wu
  • Patent number: 10638609
    Abstract: A three-dimensional electrical module includes first and second parallel substrates that each includes an electrical contact oriented toward the other of the first and second substrates. The electrical module also includes a capacitor including a first electrode electrically connected and securely fastened to the contact of the first substrate, and a second electrode electrically connected and securely fastened to the contact of the second substrate. Additionally, the electrical module includes a continuity of material being formed between the first and second substrates, perpendicular to the first and second substrates and through the capacitor.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: April 28, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Benoit Thollin
  • Patent number: 10629844
    Abstract: In various aspects, an organic optoelectronic component and method for producing an organic optoelectronic component are described. An organic optoelectronic component may include a first electrode, an organic functional layer structure above the first electrode, a second electrode above the organic functional layer structure, an adhesive layer structure, and a protective film. The adhesive layer structure may contain a first adhesive layer above the first adhesive layer, and a second adhesive layer above the first adhesive layer. The first adhesive layer may be cured. The second adhesive layer may be adherent and elastic. The protective film may be above the second adhesive layer. The protective film may contain at least one region that is at least partly separated in a lateral direction.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: April 21, 2020
    Assignee: Osram OLED GmbH
    Inventor: Simon Schicktanz
  • Patent number: 10615087
    Abstract: A semiconductor wafer with a test key structure is provided. The semiconductor wafer includes a semiconductor substrate including a scribe line region, a chip region, and a seal ring region between the scribe line region and the chip region. A test pad structure and a test element are disposed over the semiconductor substrate corresponding to the scribe line region. A conductive line is disposed over the semiconductor substrate corresponding to the seal ring region, and has two ends extending to the scribe line region and electrically connected between the test pad structure and the test element.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: April 7, 2020
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Hsiu-Han Liao, Che-Fu Chuang
  • Patent number: 10617008
    Abstract: A capacitor includes a body including a plurality of dielectric layers, first and second internal electrodes alternately disposed with respective dielectric layers interposed therebetween, and first and second insulating regions. The first insulating region is disposed in each of the first internal electrodes and includes a first connection electrode disposed therein. The second insulating region is disposed in each of the second internal electrodes and includes a second connection electrode disposed therein. The products D1×Td and D2×Td are greater than 20 ?m2, where Td is a thickness of the dielectric layer, and D1 and D2 are widths of the first and second insulating regions, respectively.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: April 7, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jin Man Jung, Jin Kyung Joo, Ik Hwan Chang, Taek Jung Lee, Won Young Lee, Yong Won Seo, Jin Woo Chun
  • Patent number: 10617013
    Abstract: A lead component mounting machine is provided in which lead wires are pinched and held from both sides by a pair of pawl portions, and the lead wires are inserted into through-holes of a board. The holding by the pawl portions is loosened, and a component main body is pushed in by a pushing-in device until the component main body comes into contact with the pawl portions. Subsequently, the strength of the holding by the pawl portions is increased, and the cutting and clinching of the lead wires is performed. Sliding movement of the lead wires is in a state of being suppressed by the pawl portions.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: April 7, 2020
    Assignee: FUJI CORPORATION
    Inventor: Nobuyuki Ishikawa
  • Patent number: 10614960
    Abstract: A composite electronic component includes: a composite body in which a multilayer ceramic capacitor and a ceramic chip are coupled to each other. The multilayer ceramic capacitor includes a first ceramic body, and first and second external electrodes disposed on both end portions of the first ceramic body. The ceramic chip includes a second ceramic body disposed on a lower portion of the multilayer ceramic capacitor, and first and second terminal electrodes disposed on both end portions of the second ceramic body and connected to the first and second external electrodes. A width of first regions of the second ceramic body in which the first and second terminal electrodes are disposed is wider than a width of a second region of the second ceramic body between the first regions.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: April 7, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Se Hun Park, Gu Won Ji, Heung Kil Park
  • Patent number: 10615105
    Abstract: A semiconductor device package includes a metal carrier, a passive device, a conductive adhesive material, a dielectric layer and a conductive via. The metal carrier has a first conductive pad and a second conductive pad spaced apart from the first conductive pad. The first conductive pad and the second conductive pad define a space therebetween. The passive device is disposed on top surfaces of first conductive pad and the second conductive pad. The conductive adhesive material electrically connects a first conductive contact and a second conductive contact of the passive device to the first conductive pad and the second conductive pad respectively. The dielectric layer covers the metal carrier and the passive device and exposes a bottom surface of the first conductive pad and the second conductive pad. The conductive via extends within the dielectric layer and is electrically connected to the first conductive pad and/or the second conductive pad.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: April 7, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hui Hua Lee, Hui-Ying Hsieh, Cheng-Hung Ko, Chi-Tsung Chiu
  • Patent number: 10608205
    Abstract: A sealing structure (200) seals a light emitting unit (140) and includes a first inorganic film (210), a second inorganic film (220), a first resin-containing film (230), and a second resin-containing film (240). The film thickness of the first inorganic film (210) is equal to or greater than 1 nm and equal to or less than 300 nm. The first resin-containing film (230) is in contact with the first inorganic film (210) and includes a first resin. The second inorganic film (220) is positioned on an opposite side of the first inorganic film (210) with the first resin-containing film (230) interposed between the first and second inorganic films. The second resin-containing film (240) is positioned between the first resin-containing film (230) and the second inorganic film (220) and is in contact with the second inorganic film (220). The second resin-containing film (240) includes a second resin.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: March 31, 2020
    Assignee: PIONEER CORPORATION
    Inventor: Shinichi Tanisako
  • Patent number: 10600739
    Abstract: An interposer includes an interposer substrate having a series of vias, and a series of metallic interconnects in the series of vias. The interposer substrate has a first surface and a second surface opposite the first surface. The interposer substrate includes a dielectric material. A first pitch of the series of vias at a first end of the series of vias is different than a second pitch of the series of vias at a second end of the series of vias.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: March 24, 2020
    Assignee: HRL Laboratories, LLC
    Inventors: Florian G. Herrault, Zak C. Eckel, Tobias A. Schaedler, Robert Mone
  • Patent number: 10602633
    Abstract: According to one embodiment, an electronic apparatus includes, for example, a casing having an opening with a perimeter, and a circuit board including a first surface facing away from the casing and a second surface facing the casing, a first conductor which extends over the opening in the casing and at least a portion of which is located over the first surface, a second conductor at least portion of which extends over the second surface and is exposed to the interior of the casing at the opening in the casing, and a third conductor extending through the first surface and the second surface and electrically connected to the first conductor and the second conductor at a location outward of the perimeter of the opening.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: March 24, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yousuke Hisakuni, Nobuhiro Yamamoto, Kota Tokuda
  • Patent number: 10593484
    Abstract: An electronic component includes: a plurality of multilayer capacitors stacked in multiple rows and columns and each having external electrodes on both ends thereof in a first direction; and a board including a body and a connection portion. The connection portion includes: a plurality of positive electrode land patterns; a plurality of negative electrode land patterns; positive and negative electrode terminal patterns formed on a lower surface of the body to be spaced apart from each other in the first direction; a positive electrode connection portion connecting the plurality of positive electrode land patterns to the positive electrode terminal pattern; and a negative electrode connection portion connecting the plurality of negative electrode land patterns to the negative electrode terminal pattern.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: March 17, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ho Yoon Kim, Jae Yeol Choi, Soo Hwan Son
  • Patent number: 10595414
    Abstract: A component carrier includes a first level stack of first plural of electrically conductive layer structures and/or first electrically insulating layer structures; a first component aligned within a first through hole cut out in the first level stack such that one of an upper or a lower surface of the first component is substantially flush with an respective upper or a lower surface of the first level stack second electrically conductive layer structures and/or second electrically insulating layer structures attached onto the upper and the lower surface of the first level stack thereby covering the first component at the upper and the lower surface of the first component and pressed to form a second level stack. A second component is aligned within a second through hole cut out in the second level stack such that one of upper or a lower surface of the second component is substantially flush with an upper or a lower surface of the second level stack.
    Type: Grant
    Filed: April 1, 2018
    Date of Patent: March 17, 2020
    Assignee: AT&S (China) Co. Ltd.
    Inventor: Mikael Tuominen
  • Patent number: 10595412
    Abstract: A semiconductor device includes a printed circuit board that includes a first electrode, a resin substrate that includes a first face directed toward the printed circuit board, a second electrode formed in a second portion surrounding a first portion of the first face, a second face opposite the first face, and a third electrode formed in a third portion of the second face, the third portion overlapping the first portion in a plan view, a semiconductor chip that includes a coupling terminal joined to the third electrode, a conductive member that is formed between the printed circuit board and the resin substrate and contains a conductive particle and resin, and a solder bump that is formed between the printed circuit board and the resin substrate and is joined to the first electrode and the second electrode.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: March 17, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Shinya Sasaki, Tsuyoshi Kanki
  • Patent number: 10595397
    Abstract: A printed circuit board includes a first trace, a second trace, and a first via. The first trace is in a first conductive layer. The second trace is in a second conductive layer. The first via interconnects the first trace and the second trace, and communicates a first signal from the first trace to the second trace through a third conductive layer. The third conductive layer has a higher impedance than the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: March 17, 2020
    Assignee: Dell Products, L.P.
    Inventors: Stuart Allen Berke, Sandor Farkas, Bhyrav M. Mutnury
  • Patent number: 10583534
    Abstract: A jointing device for metal mask plate welding includes a jointing device body. A height of the jointing device body is smaller than a welding height of a welding gun. The jointing device body has a through-hole corresponding to a welding area of a metal mask. A width of the through-hole is larger than a welding spot diameter of the welding gun. The jointing device body is used for jointing the metal mask to a metal mask receiving frame.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: March 10, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Jian Zhang, Junjie Huang, De Zhang, Dejian Liu, Rong Zhao
  • Patent number: 10586650
    Abstract: A coil substrate includes insulating layers, and conductive layers laminated on the insulating layers in a plate thickness direction of the insulating layers, respectively. The conductive layers include three or more conductive layers and a set of conductive layers such that the set of conductive layers includes a first outermost conductive layer on one end side in the plate thickness direction and does not include a second outermost conductive layer on the opposite end side in the plate thickness direction and that the set of conductive layers includes coil portions each having a spiral form respectively and aligned in the plate thickness direction.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: March 10, 2020
    Assignee: IBIDEN CO., LTD.
    Inventor: Hirotaka Taniguchi
  • Patent number: 10573587
    Abstract: A package structure includes a redistribution layer, a chip, an encapsulant, an under bump supporting layer, an attachment layer and solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface and a patterned circuit layer disposed on the first surface, wherein an outer surface of the patterned circuit layer and the first surface are coplanar. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface to encapsulate the chip. The under bump supporting layer is disposed on the first surface and includes openings for exposing the outer surface. The attachment layer covers the inner surface of each opening and the exposed portion of the patterned circuit layer. The solder balls are disposed in the openings respectively and electrically connected to the patterned circuit layer.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: February 25, 2020
    Assignee: Industrial Technology Research Institute
    Inventors: Shu-Wei Kuo, Chun-Yi Cheng, Wei-Yuan Cheng
  • Patent number: 10573589
    Abstract: A semiconductor package includes a connection member having a first surface and a second surface disposed to oppose each other and including an insulating member having a plurality of insulating layers and a plurality of redistribution layers disposed on the plurality of insulating layers, respectively; a semiconductor chip disposed on the first surface of the connection member and having connection pads electrically connected to the plurality of redistribution layers; and an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip, wherein at least one of the plurality of redistribution layers includes a dummy electrode pattern in which a plurality of holes are arranged, and each of the plurality of holes has a shape including a plurality of protruding regions that protrude externally from different positions.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: February 25, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun Jin Kim, Han Kim
  • Patent number: 10559424
    Abstract: A multilayer capacitor and a board having the same provide high capacitance and low equivalent series inductance (ESL). The multilayer capacitor includes a capacitor body including an active region, including first and second internal electrodes, and first and second cover regions. Third and fourth internal electrodes are alternately disposed in the cover region adjacent to a mounting surface. First and second external electrodes respectively contact the first and second internal electrodes to provide capacitance. First and second via electrodes are disposed in the cover region, where the first via electrode connects the third internal electrode and a first band portion of the first external electrode to each other, and where the second via electrode connects the fourth internal electrode and a second band portion of the second external electrode to each other.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: February 11, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jong Pil Lee, Hyo Youn Lee, Sung Kwon An, Seung Woo Song, Taek Jung Lee, Jin Kyung Joo
  • Patent number: 10561013
    Abstract: A coupled via structure includes a plate via penetrating through an board body and having first and second plates spaced apart from each other by a first gap distance, a contact pad connected to the plate via on a surface of the board body and having first and second contacts connected to the first and second plates, respectively, and a connection line connected to the contact pad on the surface of the board body and having first and second lines connected to the first and second contacts, respectively, and spaced apart from the first line by a second gap distance. Accordingly, the deviation of the characteristic impedance is reduced (or, alternatively, minimized) between the coupled via structure and the coupled signal line.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: February 11, 2020
    Assignees: Samsung Electronics Co., Ltd., Research & Business Foundation Sungkyunkwan University
    Inventors: Dong-Yoon Seo, Jea-Eun Lee, Wansoo Nah
  • Patent number: 10553361
    Abstract: A multilayer capacitor includes: a capacitor body including an active region including a plurality of first and second internal electrodes alternately exposed, respectively, through opposite end surfaces of the capacitor body in a length direction, and upper and lower cover regions disposed on upper and lower surfaces of the active region, respectively; and first and second external electrodes formed on the opposite end surfaces of the capacitor body in the length direction, respectively. The lower cover region of the capacitor body may have a space portion.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: February 4, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Soo Hwan Son, Young Ghyu Ahn, Ho Yoon Kim
  • Patent number: 10548227
    Abstract: In one implementation, a multilayered printed circuit board is configured to redirect current distribution. The current may be distributed by steering, blocking, or otherwise manipulating current flows. The multilayered printed circuit board includes at least one power plane layer. The power plane layer does not distribute current evenly. Instead, the power plane layer includes multiple patterns with different resistances. The patterns may include a hatching pattern, a grid pattern, a directional pattern, a slot, a void, or a continuous pattern. The pattern is a predetermined spatial variation such that current flows in a first area differently than current flows in a second area.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: January 28, 2020
    Assignee: Cisco Technology, Inc.
    Inventors: Goutham Sabavat, Javid Mohamed, Subramanian Ramanathan, Stephen Scearce
  • Patent number: 10522493
    Abstract: Provided is a paste thermosetting resin composition containing solder powder, a thermosetting resin binder, an activator, and a thixotropy imparting agent. The solder powder has a melting point ranging from 100° C. to 240° C., inclusive. The thermosetting resin binder contains a main agent and a curing agent. The main agent contains a di- or higher functional oxetane compound.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: December 31, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yasuo Fukuhara, Atsushi Yamaguchi
  • Patent number: 10522471
    Abstract: Insulating layers of a redistribution layer of a semiconductor package may be formed as a polymer film having inorganic fillers formed therein. The inorganic fillers may trap reactive materials to inhibit and/or substantially prevent the metal conductors, such as chip pads of the semiconductor chip being packaged, from being damaged by the reactive material. As a result, the reliability and the durability of the semiconductor package may be improved.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: December 31, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung Lim Suk, Seokhyun Lee
  • Patent number: 10524366
    Abstract: A polymer film is applied onto a surface of a laminated printed circuit board subassembly having vias. Holes are created in the polymer film to access the vias while the polymer film remains covering adjacent areas. The polymer film with holes allows placement of hole-fill paste in the vias while preventing unwanted hole-fill paste placement or migration to adjacent areas. After filling the vias with hole-fill paste, the hole-fill paste is preferably at least partially hardened or cured, and the polymer film is preferably removed, facilitating further assembly of a printed circuit board without unwanted hole-fill paste in other areas which could be difficult to remove, The invention includes improved processes for fabricating printed circuit boards, and is particularly useful for irregular circuit boards and rigid flex circuit boards. The invention also includes covered laminated printed circuit board subassemblies, covered with a removable polymer film.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: December 31, 2019
    Assignee: Printed Circuits, LLC
    Inventors: Kenneth Richard Tannehill, Steven Craig Hanson
  • Patent number: 10522497
    Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface, and disposed in the recess portion so that the inactive surface is connected to the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers of the frame and the connection pads of the semiconductor chip to each other, wherein the stopper layer includes an insulating material.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: December 31, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong Ho Lee, Bong Ju Cho, Young Gwan Ko, Jin Su Kim, Shang Hoon Seo, Jeong Il Lee
  • Patent number: 10515899
    Abstract: A package structure is provided. The package structure includes a molding compound. The package structure also includes an integrated circuit chip having a chip edge in the molding compound. The package structure further includes a passivation layer below the integrated circuit chip and the molding compound. In addition, the package structure includes a redistribution layer in the passivation layer. The package structure also includes first bumps electrically connected to the integrated circuit chip through the redistribution layer. The first bumps are inside the chip edge and arranged along the chip edge. The package structure further includes second bumps electrically connected to the integrated circuit chip through the redistribution layer. The second bumps are outside the chip edge and arranged along the chip edge. The first bumps are next to the second bumps. The first and second bumps are spaced apart from the chip edge.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Yen Chiu, Hsin-Chieh Huang, Ching-Fu Chang
  • Patent number: 10515879
    Abstract: A package and method of manufacturing a package is disclosed. In one example, the package includes a carrier having an accommodation through hole. A component is arranged at least partially within the accommodation through hole. A connection structure connects the carrier with the component.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: December 24, 2019
    Assignee: Infineon Technologies AG
    Inventors: Manfred Schindler, Klaus Elian, Volker Strutz, Horst Theuss, Michael Weber
  • Patent number: 10515829
    Abstract: A package system comprising a first interconnect structure arranged over a first surface of a first substrate; a plurality of first through silicon via (TSV) structures in and extending through the first substrate; a molding compound material surrounding the first substrate; at least one through via in the molding compound material with the through via being offset from the first substrate in a direction parallel to the first surface; a second interconnect structure over a second surface of the first substrate; and a first integrated circuit mounted over the first surface of the substrate, with the first integrated circuit being electrically coupled to at least one of the first TSV structures through the first interconnect structure and a connecting bump while the first interconnection structure is electrically coupled to the through via.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Cheng Wu, Shang-Yun Hou, Shin-Puu Jeng, Chen-Hua Yu
  • Patent number: RE47890
    Abstract: A fingerprint sensor package, including a sensing side for sensing fingerprint information and a separate connection side for electrically connecting the fingerprint sensor package to a host device, is disclosed. The fingerprint sensor package can also include a sensor integrated circuit facing the sensing side and substantially surrounded by a fill material. The fill material includes vias at peripheral locations around the sensor integrated circuit. The fingerprint sensor package can further include a redistribution layer on the sensing side which redistributes connections of the sensor integrated circuit to the vias. The connections can further be directed through the vias to a ball grid array on the connection side. Some aspects also include electrostatic discharge traces positioned at least partially around a perimeter of the connection side. Methods of manufacturing are also disclosed.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: March 3, 2020
    Assignee: Amkor Technology, Inc.
    Inventors: Ronald Patrick Huemoeller, David Bolognia, Robert Francis Darveaux, Brett Arnold Dunlap