With Electrical Device Patents (Class 174/260)
  • Patent number: 11399429
    Abstract: A semiconductor package device includes a first dielectric layer, a first interconnection layer, a second interconnection layer, and a second dielectric layer. The first dielectric layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The first interconnection layer is within the first dielectric layer. The second interconnection layer is on the second surface of the first dielectric layer and extends from the second surface of the first dielectric layer into the first dielectric layer to electrically connect to the first interconnection layer. The second dielectric layer covers the second surface and the lateral surface of the first dielectric layer and the second interconnection layer.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: July 26, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ming-Ze Lin, Chia Ching Chen, Yi Chuan Ding
  • Patent number: 11393624
    Abstract: A board having an electronic component mounted thereon includes a capacitor body; a pair of external electrodes disposed on both ends of the capacitor body, respectively; a pair of metal frames including a pair of connection portions connected to the pair of external electrodes, respectively, and a pair of mounting portions each having a protrusion on a lower side thereof, respectively; a board; and a pair of electrode pads disposed on an upper surface of the board and connected to the pair of metal frames, respectively, and each having a groove portion corresponding to the protrusion on an upper surface thereof.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: July 19, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Gyeong Ju Song, Beom Joon Cho, Sang Yeop Kim
  • Patent number: 11380650
    Abstract: A method of manufacturing a batch of component carriers is disclosed. The method includes providing a plurality of separate wafer structures, each comprising a plurality of electronic components, simultaneously laminating the wafer structures with at least one electrically conductive layer structure and at least one electrically insulating layer structure, and singularizing a structure resulting from the laminating into the plurality of component carriers, each comprising at least one of the electronic components, a part of the at least one electrically conductive layer structure and a part of the at least one electrically insulating layer structure.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: July 5, 2022
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Heinz Moitzi, Dietmar Drofenik
  • Patent number: 11380490
    Abstract: A multilayer ceramic capacitor includes a ceramic body including a dielectric layer, a plurality of first and second internal electrodes disposed inside the ceramic body, exposed to the first and second surfaces, and having ends exposed to the third or fourth surface, and a first side margin portion and a second side margin portion disposed on side portions of the plurality of first and second internal electrodes exposed to the first and second surfaces. A ratio Db/Da satisfies 1.00 to 1.07, inclusive, where ‘Db’ is a distance, in a stacking direction of the dielectric layer, between both end points of respective edge regions of the first side margin portion and the second side margin portion, and ‘Da’ is a distance in a central region of the ceramic body in the stacking direction.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: July 5, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dong Hun Kim, Hyun Min Lee, Jong Suk Jeong, Dong Geon Yoo, Ji Hyun Lee, Seok Hyun Yoon
  • Patent number: 11375620
    Abstract: A multi-layer ceramic electronic component includes: a ceramic body including internal electrodes laminated in one axial direction and having a main surface facing in the one axial direction; and an external electrode including a base layer including a step portion formed on the main surface, and a plated layer formed on the base layer, the external electrode being connected to the internal electrodes.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: June 28, 2022
    Assignee: Taiyo Yuden Co., Ltd.
    Inventor: Takashi Sasaki
  • Patent number: 11362697
    Abstract: A multilayer printed circuit board (PCB) including a plurality of substrate layers formed in stack is provided. The multilayer printed circuit board includes a first substrate layer located on an outer side of the plurality of substrate layers, and a second substrate layer located on another outer side of the plurality of substrate layers that is opposite to the first substrate layer. The multilayer printed circuit board further includes a transmission line, connecting a first point of the first substrate layer and a second point of the second substrate layer, which passes through the first and second substrate layers, and includes a sub-transmission line disposed between and extended along at least two adjacent substrate layers among the plurality of substrate layers.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: June 14, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinsu Heo, Seungtae Ko, Sangho Lim
  • Patent number: 11355456
    Abstract: Electronic chip comprising: an electronic circuit; a resistive element arranged on a rear face of a substrate; two conductive vias passing through the substrate, each connected to the electronic circuit and to one of the ends of the resistive element, and masked by the resistive element; and comprising a weakening structure formed of blind holes such that each of the blind holes comprises a section, at the rear face, of shape and of external dimensions similar to those of the conductive vias, and comprises a portion of the substrate masked by the resistive element, or in which the resistive element comprises first and second parts spaced apart from each other, arranged one above the other, electrically connected to each other and together forming a coil pattern and/or several alternating, intermingled, wound up or intertwined patterns.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: June 7, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Stephan Borel, Lucas Duperrex
  • Patent number: 11356587
    Abstract: An array imaging apparatus having discrete camera modules is disclosed. In one embodiment, the apparatus comprises a substrate; and heterogeneous camera modules attached to the substrate and in a geometric relationship with each other, the heterogeneous camera modules having a substantially similar photometric response.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: June 7, 2022
    Assignee: Intel Corporation
    Inventor: Ramkumar Narayanswamy
  • Patent number: 11355425
    Abstract: The present disclosure relates to a chip on film and a display device. The chip on film includes a body and an insulating protective film arranged on the body, in which the body includes a first area, a first binding area for binding and connecting to the back surface of the display panel, and a first bendable area located between the first area and the first binding area and capable of being bent in a first direction; and the insulating protection film includes a first connection area connected to the first area, a second connection area for connecting to the back surface of the display panel, and a second bendable area located between the first connection area and the second connection area and capable of being bent in a second direction opposite to the first direction.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: June 7, 2022
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD, BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Kaiwen Wang, Mookeun Shin, Xiaojun Wu, Xuanxuan Qiao, Aixia Sang, Qiang Zhang, Zhenyu Han
  • Patent number: 11342273
    Abstract: Disclosed are a package structure of an integrated passive device and a manufacturing method thereof and a substrate. The method includes: providing an organic frame having a chip embedding cavity and a metal pillar, laminating at least one layer of first dielectric on an upper surface of the organic frame, and processing the first dielectric by photolithography to form an opening correspondingly above the chip embedding cavity; mounting an electronic component in the chip embedding cavity through the opening, the electronic component including an upper and lower electrodes; laminating and curing a second dielectric into the chip embedding cavity and on an upper surface of the first dielectric, thinning the first and second dielectrics to expose the upper and lower electrodes, upper and lower surfaces of the metal pillar; performing metal electroplating to form a circuit layer communicated with the upper and lower electrodes and the metal pillar.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: May 24, 2022
    Assignee: ZHUHAI ACCESS SEMICONDUCTOR CO., LTD
    Inventors: Xianming Chen, Yejie Hong, Benxia Huang, Lei Feng, Bingsen Xie
  • Patent number: 11332030
    Abstract: An object is to provide a power system interconnection system and a method of installing the power system interconnection system that are able to supply a load with required power. A power system interconnection system comprises a storage battery an AC-DC power conversion device for the storage battery a charge and discharge station for an electric-powered automobile and an interconnection control device that are installed on a parking lot. The interconnection control device supplies a first load with power from at least one of the charge and discharge station and the AC-DC power conversion device in a case where the electric power system is in an emergency situation.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: May 17, 2022
    Assignee: DAIHEN Corporation
    Inventors: Ryuhei Nishio, Akihiro Ohori, Nobuyuki Hattori, Koji Matsunaga
  • Patent number: 11330746
    Abstract: A system and method for reworking a flip chip includes use of a mill to remove an old flip chip, and a pick-and-place device for putting a new flip chip in place at the same location. The process may be automated, with the removal and the placement occurring sequentially without need for operator intervention. Other devices and processes may be part of the system/machine and process, for example cleaning following the milling, fluxing prior to the placement, and heating to cause solder reflow, to secure the new flip chip in place. Underfill may be employed to make for a more mechanically robust mounting of the new flip chip.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: May 10, 2022
    Assignee: Raytheon Company
    Inventors: James A. Robbins, Jeffrey A. Shubrooks
  • Patent number: 11324107
    Abstract: Electronic modules having complex contact structures may be formed by encapsulating panels containing pluralities of electronic modules delineated by cut lines and having conductive interconnects buried within the panel along the cut lines. Holes defining contact regions along the electronic module sidewall may be cut into the panel along the cut lines to expose the buried interconnects. The panel may be metallized, e.g. by a series or processes including plating, on selected surfaces including in the holes to form the contacts and other metal structures followed by cutting the panel along the cut lines to singulate the individual electronic models. The contacts may be located in a conductive grove providing a castellated module.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: May 3, 2022
    Assignee: Vicor Corporation
    Inventors: Patrizio Vinciarelli, Patrick R. Lavery, Rudolph F. Mutter, Jeffery J. Kirk, Andrew T. D'Amico
  • Patent number: 11322305
    Abstract: A multilayer capacitor includes a capacitor body having first through six surfaces, and having alternately stacked first internal electrodes and second internal electrodes having dielectric layers therebetween and each having one end thereof exposed through a respective one of third and fourth surfaces. First and second conductive layers respectively include first and second connection portions respectively disposed on the third and fourth surfaces of the capacitor body and respectively connected to the first and second internal electrodes, and first and second band portions respectively extending from the first and second connection portions to respective portions of the first, second, fifth, and sixth surfaces of the capacitor body. First and second reinforcing layers each include a carbon material and an impact-absorbing binder and are respectively disposed on the first and second band portions.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: May 3, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Won Kuen Oh, Hye Hun Park, Tae Gyeom Lee
  • Patent number: 11322463
    Abstract: A packaged antenna circuit structure suitable for 5G use includes a shielding layer, an electronic component, conductive pillars, a first insulation layer, a first stacked structure, an antenna structure, and a second stacked structure. The shielding layer defines a groove to receive the electronic component. The conductive pillars on the shielding layer surround the groove. The first insulation layer covers the shielding layer, the electronic component, and the conductive pillars. The first stacked structure is stacked on a side of the first insulation layer and includes a ground line connecting to the conductive pillars. The antenna structure is stacked on a side of the first stacked structure away from the first insulation layer and connected to the electronic component by the first stacked structure. The second stacked structure is stacked on a side of the first insulation layer away from the first stacked structure.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: May 3, 2022
    Assignees: Avary Holding (Shenzhen) Co., Limited., QING DING PRECISION ELECTRONICS (HUAIAN) CO., LTD
    Inventors: Yong-Chao Wei, Jia-He Li
  • Patent number: 11322368
    Abstract: A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: May 3, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Ho Park, Jin-Woo Park, Seok Hyun Lee, Jae Gwon Jang, Gwang Jae Jeon
  • Patent number: 11315732
    Abstract: A multilayer ceramic electronic component includes a ceramic body, and first and second external electrodes disposed on the surface of the ceramic body, respectively. The ceramic body includes a capacitance forming portion including a dielectric layer and internal electrodes, margin portions disposed on both sides of the capacitance forming portion, and cover portions disposed on both sides of the capacitance forming portion. The first and second external electrodes include first and second base electrodes, respectively, first and second conductive layers disposed on edges of the first and second base electrodes, respectively, and first and second terminal electrodes covering the first and second base electrodes, respectively.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: April 26, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: In Kyung Jung, Dong Hwi Shin
  • Patent number: 11302483
    Abstract: An electronic component includes a capacitor body having first to sixth surfaces, and including a plurality of dielectric layers and first and second internal electrodes; first and second external electrodes disposed on both ends of the capacitor body in a second direction in which the third and fourth surfaces oppose each other, respectively; a third external electrode disposed on the first surface of the capacitor body; and first to third metal frames connected to the first to third external electrodes, respectively, both ends of the first internal electrode are exposed through the third and fourth surfaces of the capacitor body, respectively, and the second internal electrode includes a lead portion exposed through the first surface of the capacitor body and connected to the third external electrode.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: April 12, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Je Jung Kim, Su Kyoung Cha, Ji Won Lee, Seung Ryeol Lee
  • Patent number: 11302478
    Abstract: A multilayer ceramic capacitor includes a body including a dielectric layer and an internal electrode and an external electrode disposed on an exterior of the body. The external electrode includes an electrode layer connected to the internal electrode and a plating portion including a nickel (Ni) plating layer, a nickel-tin (Ni—Sn) intermetallic compound layer, and a tin (Sn) plating layer, sequentially disposed on the electrode layer. The Ni—Sn intermetallic compound layer has a thickness of 0.1 ?m or more.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: April 12, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Byung Gyun Kim, Ji Hong Jo, Jong Ho Lee, Myung Jun Park
  • Patent number: 11297717
    Abstract: An embodiment of the invention may include a method, and resulting structure, of forming a semiconductor structure. The method may include forming a component hole from a first surface to a second surface of a base layer. The method may include placing an electrical component in the component hole. The electrical component has a conductive structure on both ends of the electrical component. The electrical component is substantially parallel to the first surface. The method may include forming a laminate layer on the first surface of the base layer, the second surface of the base layer, and between the base layer and the electrical component. The method may include creating a pair of via holes, where the pair of holes align with the conductive structures on both ends of the electrical component. The method may include forming a conductive via in the pair of via holes.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: April 5, 2022
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventor: Lei Shan
  • Patent number: 11296019
    Abstract: A vertically structured pad system and method can include: a platform having etch attributes, a platform top surface, and a platform side surface; a structure on the platform, the structure including a structure side surface extended up from the platform top surface terminating in a structure top surface, the structure including a structure interior surface defining a cavity within the structure, and the platform top surface exposed from within the cavity; and an interconnect structure adhered to the platform and the structure, the interconnect structure conforming with an exterior shape of the platform side surface in combination with the structure for locking the interconnect structure onto the platform and the structure.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: April 5, 2022
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Kwang Hong Tan, Mihalis Kolios Michael, David Alan Pruitt
  • Patent number: 11291118
    Abstract: An inductor built-in substrate includes a core substrate having an opening and a first through hole formed therein, a magnetic resin filling the opening and having a second through hole formed therein, a first through-hole conductor including a metal film formed in the first through hole, and a second through-hole conductor including a metal film formed in the second through hole. The core substrate and the magnetic resin are formed such that a surface in the first through hole has a roughness that is larger than a roughness of a surface in the second through hole.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: March 29, 2022
    Assignee: IBIDEN CO., LTD.
    Inventors: Satoru Kawai, Yasuki Kimishima
  • Patent number: 11289273
    Abstract: An electronic component includes a multilayer capacitor and an interposer. First and second internal electrodes of the multilayer capacitor are such that 0.95?{(Wm1+Wm2)/Wa}/{(Lm1+Lm2)/La}?4.93, in which Lm2 is a distance between a first internal electrode and a fourth surface of a capacitor body, Lm1 is a distance between a second internal electrode and a third surface of the capacitor body opposite the fourth surface in a first direction, Wm1 is a distance between the first or second internal electrode and a second surface of the capacitor body, Wm2 is a distance between the first or second internal electrode and a first surface of the capacitor body opposite the second surface in a third direction, La is a length in the first direction of a region of overlap of the first and second internal electrodes, and Wa is a length in the third direction of the region of overlap.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: March 29, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Ho Yoon Kim
  • Patent number: 11289893
    Abstract: The various embodiments of the present disclosure are directed to devices, systems and methods for mitigating fault propagation between two or more safety components. A system, for avoiding propagation of a fault between two or more safety components may include a control unit outputting an input signal, a first safety component electrically coupled to receive the input signal from the control unit; a second safety component electrically coupled to receive the input signal from the control unit; and a first isolating component electrically disposed between and further coupling the control unit with the first safety component. Each of the first safety component and the second safety component are electrically coupled to the control unit by at least a common lead. The first isolating component prevents a first IC fault arising with respect to the first safety component from propagating, via the input signal, to the second safety component.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: March 29, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Dieter Jozef Joos
  • Patent number: 11276529
    Abstract: An electronic component and a board having the same mounted thereon are provided. The electronic component includes: a body; an electrode disposed on an end of the body in a first direction; a metal frame including a support layer bonded to the external electrode, a mounting portion extending in the first direction in a lower end of the support layer and having a protruding portion on a lower surface, and a coating film formed to cover an upper surface of the protruding portion on an upper surface of the mounting portion and including titanium (Ti).
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: March 15, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Young Na, Ki Young Kim, Beom Joon Cho, Ji Hong Jo, Woo Chul Shin
  • Patent number: 11272615
    Abstract: A wiring circuit board includes an insulating layer and a conductive layer disposed on a front surface of the insulating layer. The conductive layer includes a first wiring, a first terminal electrically connected to the first wiring, a second wiring independent of the first wiring and having a thick thickness T2 with respect to a thickness T1 of the first wiring, and a second terminal electrically connected to the second wiring. The surfaces of the first terminal and the second terminal are disposed at generally the same position in a thickness direction.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: March 8, 2022
    Assignee: NITTO DENKO CORPORATION
    Inventors: Naoki Shibata, Hiroaki Machitani, Yasunari Oyabu, Masaki Ito, Kenya Takimoto
  • Patent number: 11264176
    Abstract: A multilayer ceramic capacitor includes a ceramic body including a dielectric layer and first and second internal electrodes stacked with the dielectric layer interposed therebetween, and having first and second external electrodes disposed on the ceramic body and connected to the first and second internal electrodes, respectively. The first external electrode includes a first electrode portion and a first band portion, and the second external electrode comprises a second electrode portion and a second band portion. A length of the ceramic body in a first direction is L, a width thereof in a second direction is W, a length of the first and second electrode portions in the first direction is BW, a width of the first or second band portion in the second direction is SW, a ratio SW/W is less than 0.46, and a ratio BW/L exceeds 0.10.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: March 1, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Tae Hoon Kim, Won Chul Sim
  • Patent number: 11244628
    Abstract: A display device including a substrate including a display area and a non-display area, a plurality of signal lines disposed in the display area and extending along a first direction and from the non-display area to the display area, a connection line extending from the non-display area and electrically connected to a respective signal line of the plurality of signal lines in the non-display area, and an initialization voltage line extending in a second direction intersecting the first direction, wherein the connection line overlaps the initialization voltage line in a thickness direction of the display device.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: February 8, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung Hwan Cho, Ki Nyeng Kang, Sang Hoon Lee, Sun Ho Kim, Tae Woo Kim, Tae Hoon Yang, Jong Hyun Choi
  • Patent number: 11246214
    Abstract: A resin multilayer board includes an insulating substrate including a first main surface and mounting electrodes only on the first main surface. The insulating substrate includes first and second resin layers that are laminated. The Young's modulus of the second resin layers is higher than that of the first resin layers. The first and second resin layers are arranged in a distributed manner along a lamination direction of the first and second resin layers. The insulating substrate includes a first and second portions that are two equally divided portions of the insulating substrate in the lamination direction and are respectively positioned closer to the first main surface and farther from the first main surface, and a volume ratio of the second resin layers in the first portion is higher than a volume ratio of the second resin layers in the second portion.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: February 8, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Tomohiro Nagai, Shigeru Tago
  • Patent number: 11244997
    Abstract: A display apparatus includes a base substrate, a plurality of data lines disposed in a display area on the base substrate, wherein at least a portion of the data lines extend to a first peripheral area adjacent to the display area, a plurality of detour lines disposed in the display area, wherein at least a portion of the detour lines extend to the first peripheral area, and a data driver electrically connected to the data lines and the detour lines, wherein at least one of the data lines electrically contacts at least one of the detour lines in the first peripheral area.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: February 8, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Minjae Jeong, Kyung-Hoon Kim, Meehye Jung
  • Patent number: 11244905
    Abstract: A substrate with an electronic component embedded therein includes a core substrate including an insulating body having a first surface and a second surface, opposite to the first surface, a first wiring layer embedded in the insulating body such that one surface thereof is exposed from the first surface, and a second wiring layer disposed on the insulating body to protrude on the second surface, the core substrate having a cavity penetrating a portion of the insulating body from the first surface toward the second surface and having a stopper layer as a bottom surface thereof; an electronic component disposed on the stopper layer in the cavity; a first insulating material covering at least a portion of each of the core substrate and the electronic component; and a third wiring layer disposed on the first insulating material.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: February 8, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Je Sang Park, Chang Yul Oh, Sang Ho Jeong, Yong Duk Lee
  • Patent number: 11227724
    Abstract: A method of manufacturing a multilayer ceramic capacitor includes forming a water-repellent coating layer on surfaces of a multilayer ceramic capacitor having an internal electrode, a dielectric layer, and an external electrode; and removing at least a portion of the water-repellent coating layer formed on the surfaces of the external electrode such that another portion of the water-repellent coating layer remains on surfaces of the dielectric layer. The external electrode has first and second surfaces opposing each other in a thickness direction, third and fourth surfaces opposing each other in a width direction, and fifth and sixth surfaces opposing each other in a length direction.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: January 18, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jin Sung Chun, Hyo Kyong Seo, Hae Suk Chung, Chae Min Park, Byung Sung Kang
  • Patent number: 11224127
    Abstract: A flexible printed circuit board and an electronic device using the same are provided. The electronic device includes a first casing, a second casing, and a printed circuit board combination. The printed circuit board combination includes a first printed circuit board, a second printed circuit board, and a flexible printed circuit board. The flexible printed circuit board includes a body portion, a first extending end, and a second extending end. The body portion defines an opening. The first extending end bends from a first side of the body portion toward the body portion and extends toward a first direction after passing through the opening to connect the first printed circuit board. The second extending end extends from a second side of the body portion toward a second direction to connect the second printed circuit board.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: January 11, 2022
    Assignee: PEGATRON CORPORATION
    Inventors: Mao-Hsiang Huang, Wei-Chih Hsu, Pen-Uei Lu
  • Patent number: 11217545
    Abstract: A semiconductor package includes a first substrate having a first surface and including a first electrode, a first bump pad located on the first surface of the first substrate and connected to the first electrode, a second substrate having a second surface facing the first surface of the first substrate and including a second electrode, a second bump pad and neighboring second bump pads on the second surface of the second substrate, and a bump structure. The second bump pad has a recess structure. That is recessed from a side surface of the second bump pad toward a center thereof. The second bump pad may be connected to the second electrode. A bump structure may contact the first bump pad and the second bump pad. The bump structure may have a portion protruding through the recess structure. The neighboring second bump pads may neighbor the second bump pad and include recess structures oriented in different directions.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: January 4, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Junghyun Roh
  • Patent number: 11211315
    Abstract: Described examples include an apparatus, including: a substrate having a first surface configured to mount at least one integrated circuit and having a second surface opposite the first surface, the second surface having a plurality of terminals arranged in rows and columns, and at least one row of the plurality of terminals disposed adjacent a first side and extending generally along the length of the substrate arranged in a pattern extending along a longitudinal line, the pattern including a first group of consecutive terminals extending in a first direction at a first angle to the longitudinal line and directed towards an interior of the substrate, a second group of consecutive terminals extending in a second direction at a second angle and extending towards the periphery of the substrate, and a third group of consecutive ones of the terminals extending from the second group in the first direction.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: December 28, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Casey Thomas Morrison, Lee Martin Sledjeski
  • Patent number: 11199882
    Abstract: A display device is provided and includes a display panel and a flexible printed wiring substrate. The display panel is provided with a binding structure. The binding structure includes a plurality of first connection terminals arranged along a width direction of the display panel; and a flexible printed wiring substrate is electrically connected to the bonding structure of the display panel. Each of the first connection terminals is obliquely disposed along a lateral edge of the width direction of the display panel, and adjacent lateral edges of two of the adjacent first connection terminals along the width direction of the display panel are parallel to each other.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: December 14, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Min Chen, Chaoyu Yuan
  • Patent number: 11195805
    Abstract: A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: December 7, 2021
    Assignee: Intel Corporation
    Inventors: Andrew Collins, Sujit Sharan, Jianyong Xie
  • Patent number: 11195779
    Abstract: A module. In some embodiments, the module includes a substrate; a plurality of electronic components, secured to an upper surface of the substrate; a thermally conductive heat spreader, on the electronic components and in thermal contact with an electronic component of the plurality of electronic components; a standoff, between the substrate and the heat spreader; an alignment element, extending into the substrate; a hard stop, under the substrate; and a plurality of compressible interconnects, under the substrate, and extending through the hard stop. The electronic components may be within a sight area of the substrate. The module may be configured to transmit a compressive load from an upper surface of the standoff to a lower surface of the substrate through a load path not including any of the electronic components.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: December 7, 2021
    Assignee: Raytheon Company
    Inventors: Michael Benjamin Brown, Alberto F. Viscarra, Michael M. Fitzgibbon, John A. Crockett, Jr., Chad E. Patterson, Kevin C. Rolston, Duke Quach, Kevin P. Agustin
  • Patent number: 11183483
    Abstract: A multichip module provided with a first substrate, a first semiconductor chip, a second substrate and a third substrate. The first semiconductor chip has a first surface provided with a first electrode and a second surface mounted on the first substrate so that the first wiring of a first mount surface of the first substrate is electrically connected to the first electrode. The second substrate has a second mounting surface and a third mounting surface bonded to the first substrate so that the second mounting surface is opposed to the first mounting surface. The third substrate has a fourth mounting surface provided with a second wiring and a fifth mounting surface bonded to the second silicon substrate so that the fourth mounting surface is opposed to the third mounting surface and is mounted with the first semiconductor chip so that the second wiring is electrically connected to the second surface.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: November 23, 2021
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Masahiro Kato, Shuhei Iriyama
  • Patent number: 11183484
    Abstract: The present invention is intended to provide a semiconductor module and a DIMM module that are capable of stably supplying power to a plurality of stacked memory chips, a manufacturing method of the semiconductor module and a manufacturing method of the DIMM module. The semiconductor module 1 having a plurality of memory chips 21 includes: a memory substrate 10 having a power supply circuit 12 exposed on an arrangement surface as one surface of the memory substrate 10; and at least one memory unit 20 arranged over the arrangement surface of the memory substrate 10. The memory unit 20 includes: the plurality of memory chips 21 stacked together such that a stacking direction D is along the arrangement surface; a through electrode 22 passing through the plurality of memory chips 21 in the stacking direction D; and an electrode layer 23 formed on one end surface in the stacking direction D and connected to the through electrode 22 and the power supply circuit 12.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: November 23, 2021
    Assignee: ULTRAMEMORY INC.
    Inventors: Fumitake Okutsu, Takao Adachi
  • Patent number: 11177071
    Abstract: A multi-layer ceramic electronic component includes a ceramic body and an external electrode, the ceramic body including a protective portion and a functional portion, the protective portion including an end surface facing in a first direction, circumferential surfaces connected to the end surface and extending in the first direction, and a ridge that includes a recess extending along the first direction and connects the circumferential surfaces, the functional portion being disposed inside the protective portion, the external electrode including a base film covering the end surface, and a plating film formed on the base film, the base film including a first covering portion formed on the end surface, second covering portions formed on the circumferential surfaces, and a third covering portion formed on the recess and spaced apart from at least one second covering portion, the plating film continuously covering the first, second, and third covering portions.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: November 16, 2021
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Ryo Ono, Tetsuhiko Fukuoka, Shoji Kusumoto, Akihiko Kono
  • Patent number: 11164701
    Abstract: A ceramic electronic device includes: a multilayer chip including a multilayer structure and cover layers, the multilayer structure having a structure in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked and are alternately exposed to two edge faces of the multilayer chip, a main component of the plurality of dielectric layers being a ceramic, the cover layers being provided on an upper face and a lower face of the multilayer structure in a stacking direction; and a pair of external electrodes that are formed on the two edge faces, wherein each of the external electrodes has a smaller thickness on a corner portion of the cover layers, has a crook toward the internal electrode layers, and has a larger thickness on an area of the two edge faces where the internal electrode layers are extracted.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: November 2, 2021
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Mikio Tahara, Tomoaki Nakamura
  • Patent number: 11166399
    Abstract: An electronic module with an integrated electromagnetic shield using surface mount shield wall components has been disclosed. Each surface mount shield wall component provides side shielding of the circuitry within the overmolded electronic module and provides an exposed conductive shield wall section to which a top conductive shield can be applied. By including the shield structure as part of the overmolded electronic module, the need for a separate shield and separate process steps for installing the separate shield can be eliminated. Each surface mount shield wall component comprises a non-conductive portion that provides stability during a reflow soldering process, but at least a sacrificial portion of the non-conductive portion can be removed to reduce the amount of area occupied by the overmoldable shield structure.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: November 2, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventors: Philip H. Thompson, Larry D. Pottebaum
  • Patent number: 11157718
    Abstract: A fingerprint identification module and a terminal device are provided. The fingerprint identification module includes: a decorative ring, provided with a mounting opening; an encapsulation cover, arranged on the decorative ring to close a side of the mounting opening; a fingerprint chip, disposed in the mounting opening, a space is formed between an outer side surface of the fingerprint chip and an inner wall surface of the decorative ring; a protective film, disposed on a side of the fingerprint chip that is towards the encapsulation cover; and a flexible printed circuit (FPC) board, disposed inside the mounting opening, the protective film covers a first partial area of the FPC board, and a second partial area of the FPC board is exposed out of the protective film; the second partial area is an area of the FPC board which is different from the first partial area of the FPC board.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: October 26, 2021
    Assignee: VIVO MOBILE COMMUNICATION CO., LTD.
    Inventors: Zidong Yang, Ying Ge
  • Patent number: 11153974
    Abstract: A connector device that includes a circuit board; a connector attached to the circuit board; a plurality of collars for external attachment; a first molded resin that is made of a first resin material whose melting point or softening point is 230° C. or less, and covers the entire circuit board and part of the connector; and a second molded resin that is welded to the first molded resin, is made of a second resin material whose melting point or softening point is higher than that of the first resin material for the first molded resin, and covers outer circumferences of the collars.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: October 19, 2021
    Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yu Muronoi, Naomichi Kawashima, Masayuki Kato, Takeo Uchino, Akihiko Matsuoka, Tatsuo Hirabayashi
  • Patent number: 11145603
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: October 12, 2021
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Joon Han, Il Kwon Shim, KyoungHee Park, Yaojian Lin, KyoWang Koo, In Sang Yoon, SeungYong Chai, SungWon Cho, SungSoo Kim, Hun Teak Lee, DeokKyung Yang
  • Patent number: 11145463
    Abstract: A multilayer capacitor includes a body, a plurality of internal electrodes, and an external electrode. A cover portion of the body has curved corners, and a radius of curvature, R, of each of the curved corners and a thickness, T, of the body satisfy a condition of 10 ?m?R?T/3, and a width, W, and a thickness, T, of the body satisfy a condition of T/W<0.8.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: October 12, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Byeong Gyu Park, Yong Jin Yun, So Ra Kang, Jung Min Park, Jea Yeol Choi
  • Patent number: 11139113
    Abstract: An electronic component includes: a capacitor body; first and second external electrodes disposed on both ends of the capacitor body in a length direction; and first and second connection terminals disposed on a mounting surface of the capacitor body and electrically connected to the first and second external electrodes, respectively, and having first and second cut portions on surfaces facing each other in the length direction of the capacitor body, respectively.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: October 5, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Heung Kil Park, Gu Won Ji, Se Hun Park, Young Ghyu Ahn
  • Patent number: 11134567
    Abstract: An embedded component structure includes a circuit board, an electronic component, a first conductive terminal, and a second conductive terminal. The circuit board includes a first electrical connection layer and a second electrical connection layer. The electronic component is embedded in the circuit board and includes a first contact and a second contact. The first conductive terminal and the second conductive terminal respectively at least cover a part of top surfaces and side walls of the first contact and the second contact, and the first electrical connection layer and the second electrical connection layer are respectively electrically connected to the first contact and the second contact through the first conductive terminal and the second conductive terminal. A method for manufacturing an embedded component structure is also provided.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: September 28, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Yu-Shen Chen, I-Ta Tsai, Chien-Chih Chen
  • Patent number: 11134572
    Abstract: The present publication discloses a method for manufacturing a circuit-board structure. In the method, a conductor layer is made, which comprises a conductor foil and a conductor pattern on the surface of the conductor foil. A component is attached to the conductor layer and the conductor layer is thinned, in such a way that the conductor material of the conductor layer is removed from outside the conductor pattern.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: September 28, 2021
    Assignee: IMBERATEK, LLC
    Inventors: Risto Tuominen, Antti Iihola, Petteri Palm