Abstract: Methods and devices including a plurality of memory cells and a first bit line connected to a first column of memory cells of the plurality of memory cells, and a second bit line connected to the first column of cells. The first bit line is shared with a second column of memory cells adjacent to the first column of memory cells. The second bit line is shared with a third column of cells adjacent to the first column of cells opposite the second column of cells.

Abstract: An area efficient readable and resettable configuration memory latch maintains latch data integrity through read and write operations and includes a non-terminated inout bit line (BL). During write operations, enabled by a Word Line Write (WLW) signal, the non-terminated inout BL drives data to be written, while, during read operations, enabled by a Word Line Read (WLR) signal, the state of the BL is indicative of a data stored in the latch. A pull-down network is activated when the WLR signal is asserted and the stored data is logic one and, when activated, operates to pull down the BL to logic zero; the pull-down network is inactive otherwise. A weak pull-up operates to pull up the BL when the pull-down network is inactive. A sensing block is configured to sense the state of the BL when the WLR signal and a read enable signal are both asserted.

Abstract: A bit line structure, a manufacturing method thereof, and a semiconductor memory are provided. The bit line structure includes a first bit line array and a second bit line array. The first bit line array includes a plurality of first bit lines extending in a Y direction. The plurality of first bit lines have a same length and are aligned and arranged in an X direction. The second bit line array includes a plurality of second bit lines extending in the Y direction. The plurality of second bit lines have a same length and are aligned and arranged in the X direction. The first bit line array and the second bit line array are not aligned in the X direction. The X direction is perpendicular to the Y direction.

Abstract: 3D NOR flash memory devices having vertically stacked memory cells are provided. In one aspect, a memory device includes: a word line/bit line stack with alternating word lines and bit lines separated by dielectric layers disposed on a substrate; a channel that extends vertically through the word line/bit line stack; and a floating gate stack surrounding the channel, wherein the floating gate stack is present between the word lines and the channel, and wherein the bit lines are in direct contact with both the channel and the floating gate stack. Techniques for configuring the memory device for neuromorphic computing are provided, as are methods of fabricating the memory device.

Abstract: An image sensor includes a pixel array unit in which pixels are arranged in a matrix, and multiple vertical signal lines provided in pixel column units. The multiple vertical signal lines provided in pixel column units are arranged in multiple wiring layers laminated on the pixel, and are arranged so that orthogonal projections of the vertical signal lines on the multiple wiring layers overlap. The wiring layer is provided with a connection portion for connecting the vertical signal line corresponding to the pixel to the pixel. A pixel signal is taken out from the vertical signal line through the connection portion.

Abstract: A memory device includes a bit line (BL); a source line (SL); and a plurality of non-volatile memory cells operatively coupled between the BL and SL, respectively. Each of the plurality of non-volatile memory cells includes a resistor with a variable resistance, a first transistor, and a second transistor that are coupled to each other in series. In response to a first one of the non-volatile memory cell not being read and a second one of the non-volatile memory cell being read, a voltage level at a first node connected between the first and second transistors of the first non-volatile memory cell is greater than zero.

Abstract: A semiconductor device includes a first electrode, a second electrode, and a multi-layer stack positioned between the first electrode and the second electrode, the multi-layer stack including at least one anti-ferroelectric layer and at least one high-k dielectric layer.

Abstract: An apparatus may include a first matrix comprising a first plurality of digit lines, a second matrix comprising a second plurality of digit lines, a plurality of sense amplifiers, and a plurality of selector circuits. Each selector circuit of the plurality of selector circuits may be configured to selectively couple a respective sense amplifier to either a first digit line of the first plurality of digit lines or a second digit line of the second plurality of digit lines.

Abstract: A memory module comprises dynamic random access memory (DRAM) devices arranged in ranks, and a module controller configurable to receive address and control signals for a memory operation, and to output first module control signals to the DRAM devices, causing a selected rank to output or receive N-bit-wide data. The module controller is further configurable to output second module control signals to a plurality of data buffers coupled to the DRAM devices via module data lines. Each respective data buffer includes a n-bit-wide (n<N) data path and logic configurable to, in response to the second module control signals, enable the n-bit-wide data path to receive and regenerate signals carrying a respective n-bit-wide section of the N-bit-wide data communicated from/to a respective n-bit-wide section of the module data lines. The logic is further configurable to disable the n-bit-wide data path when the memory module is not being accessed for data.

Abstract: A novel memory device is provided. The memory device includes a plurality of first wirings extending in a first direction, a plurality of memory element groups, and an oxide layer extending along a side surface of the first wiring. Each of the memory element groups includes a plurality of memory elements. Each of the memory elements includes a first transistor and a capacitor. A gate electrode of the first transistor is electrically connected to the first wiring. The oxide layer includes a region in contact with a semiconductor layer of the first transistor. A second transistor is provided between the adjacent memory element groups. A high power supply potential is supplied to one or both of a source electrode and a drain electrode of the second transistor.

Abstract: The present disclosure relates to a memory device comprising an array of memory cells arranged in a multideck configuration comprising a plurality of superimposed decks, a plurality of access lines comprising at least a first plurality of access lines arranged in a first level, a second plurality of access lines arranged in a second level, and a third plurality of access lines arranged in a third level between the first plurality of access lines and the second plurality of access lines, the third plurality of access lines being arranged between two decks of the plurality of decks, a plurality of drivers configured to drive signals to the access lines, and connection elements configured to electrically connect the access lines to the respective drivers. The connections elements and the access lines are arranged so that a single driver of the plurality of drivers is configured to drive at least one access line of each level of the at least three levels. Related memory systems and methods are also disclosed.

Abstract: A semiconductor device according to an aspect of the present disclosure includes: a plurality of line layers; a first line; and a second line that is not connected to the first line and is redundantly provided to transfer a signal having a level same as a level of a signal transferred through the first line. The first line and the second line are included in different layers out of the plurality of line layers, and a distance between the first line and the second line is longer than an interlayer distance between line layers next to each other out of the plurality of line layers.

Abstract: Systems, methods, and apparatuses for widened conductive line structures and staircase structures for semiconductor devices are described herein. One memory device includes an array of vertically stacked memory cells, the array including a vertical stack of horizontally oriented conductive lines. Each conductive line comprises a first portion extending in a first horizontal direction and a second portion extending in a second horizontal direction, wherein the second portion of each conductive line is of a width greater than the first portion of each conductive line.

Abstract: Memory subword driver circuits with common transistors are disclosed. In some examples, a subword driver block of a memory device includes a plurality of subword drivers each having an output configured to be coupled to a word line coupled to a plurality of memory cells. The outputs of a first subword driver and a second subword driver of the plurality of subword drivers are coupled to a common transistor and a common word driver line, where the first subword driver and the second subword driver are respectively coupled to a first main word line and a second main word line. In such configuration, the first and second subword drivers are coupled in cascade connection so that, responsive to an active first main word line and an inactive common word driver line, a non-active potential is provided to the first subword driver from the second subword driver via the common transistor.

Abstract: Methods, apparatuses, and systems for in- or near-memory processing are described. Strings of bits (e.g., vectors) may be fetched and processed in logic of a memory device without involving a separate processing unit. Operations (e.g., arithmetic operations) may be performed on numbers stored in a bit-parallel way during a single sequence of clock cycles. Arithmetic may thus be performed in a single pass as numbers are bits of two or more strings of bits are fetched and without intermediate storage of the numbers. Vectors may be fetched (e.g., identified, transmitted, received) from one or more bit lines. Registers of a memory array may be used to write (e.g., store or temporarily store) results or ancillary bits (e.g., carry bits or carry flags) that facilitate arithmetic operations. Circuitry near, adjacent, or under the memory array may employ XOR or AND (or other) logic to fetch, organize, or operate on the data.

Abstract: Methods, systems, and devices for a decoding architecture for memory devices are described. Word line plates of a memory array may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. Memory cells coupled with a word line plate, or a subset thereof, may represent a logical page for accessing memory cells. Each word line plate may be coupled with a corresponding word line driver via a respective electrode. A memory cell may be accessed via a first voltage applied to a word line plate coupled with the memory cell and a second voltage applied to a pillar electrode coupled with the memory cell. Parallel or simultaneous access operations may be performed for two or more memory cells within a same page of memory cells.

Abstract: In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.

Abstract: A semiconductor structure includes a gate structure, a source region, a drain region, and an isolation structure. The gate structure includes a first portion, a second portion and a third portion. The first portion extends in a first direction, and the second portion and the third portion extend in a second direction. The second portion and the third portion are disposed at opposite ends of the first portion. The source region and the drain region are separated by the gate structure. The isolation structure surrounds the gate structure, the source region and the drain region. The first portion has a first sidewall, the second portion has a second sidewall, and the third portion has a third sidewall. The first sidewall, the second sidewall and the third sidewall are parallel to the first direction and aligned with each other to form a straight line.

Abstract: Disclosed herein are related to a memory array. In one aspect, the memory array includes a set of resistive storage circuits including a first subset of resistive storage circuits connected between a first local line and a second local line in parallel. The first local line and the second local line may extend along a first direction. In one aspect, for each resistive storage circuit of the first subset of resistive storage circuits, current injected at a first common entry point of the first local line exits through a first common exit point of the second local line, such that each resistive storage circuit of the first subset of resistive storage circuits may have same or substantial equal resistive loading.

Abstract: NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.

Abstract: Methods, devices, and systems for testing a number of combinations of memory in a computer system. A modular memory device is installed in a memory channel in communication with a processor. The modular memory device includes a number of memory storage devices. The number of memory storage devices include a number of pins. For each of a number of subsets of the number of memory storage devices, a subset of the number of memory storage devices is selected, each pin of a subset of the number of pins which do not correspond to the subset of the number of memory storage devices is configured with a termination impedance, and the subset of the number of memory storage devices is tested.

Abstract: The disclosure provides a sense amplifier and a control method thereof. The sense amplifier includes: a pre-charge module, a first input and output terminal, a second input and output terminal, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit, a sixth switch unit, a seventh switch unit, an eighth switch unit, a first energy storage unit and a second energy storage unit. The sense amplifier can compensate for the offset voltage. The result is a sense amplifier with greatly reduced offset voltage, thereby improving the sensitivity and resolution of the sense amplifier.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip has a magnetic tunnel junction (MTJ) disposed on a first electrode that is within a dielectric structure over a substrate. A first unipolar selector is disposed within the dielectric structure and is coupled to the first electrode. A second unipolar selector is disposed within the dielectric structure and is coupled to the first electrode. The first unipolar selector and the second unipolar selector have different widths.

Abstract: A wafer manufacturing method includes a wafer preparing step of preparing a wafer including a semiconductor device formed in each of a plurality of regions demarcated by a plurality of streets intersecting each other, a support substrate fixing step of fixing the wafer to a support substrate, a removing step of removing, from the wafer, a defective device region including a semiconductor device determined to be a defective product among a plurality of the semiconductor devices formed in the wafer, and a fitting step of fitting, into a removed region formed by removing the defective device region from the wafer, a device chip including a semiconductor device as a non-defective product having same functions as those of the semiconductor device determined to be a defective product and having a size capable of being fitted into the removed region, and fixing the device chip to the support substrate.

Abstract: A wafer manufacturing method includes a wafer preparing step of preparing a wafer including a semiconductor device formed in each of a plurality of regions demarcated by a plurality of streets intersecting each other, a removing step of removing, from the wafer, a defective device region including a semiconductor device determined to be a defective product among a plurality of the semiconductor devices formed in the wafer, a support substrate fixing step of fixing the wafer to a support substrate, and a fitting step of fitting, into a removed region formed by removing the defective device region from the wafer, a device chip including a semiconductor device as a non-defective product having same functions as those of the semiconductor device determined to be a defective product and having a size capable of being fitted into the removed region, and fixing the device chip to the support substrate.

Abstract: A memory device includes a first cell block on a substrate at a first level, and a second cell block on the substrate at a second level different from the first level. Each of the first and second cell blocks includes a word line extending in a first direction that is parallel to a top surface of the substrate, a word line contact connected to a center point of the word line, a bit line extending in a second direction that is parallel to the top surface of the substrate and intersects the first direction, a bit line contact connected to a center point of the bit line, and a memory cell between the word and bit lines. The second cell block is offset from the first cell block in at least one of the first and second directions.

Abstract: According to one embodiment, a semiconductor memory device includes first to second areas, a plurality of conductive layers, first to fourth members, and a plurality of pillars. The second area includes a first contact area including first to third sub-areas. The conductive layers include first to fourth conductive layers. The first conductive layer includes a first terrace portion in the first sub-area. The second conductive layer includes a second terrace portion in the third sub-area. The third conductive layer includes a third terrace portion in the first sub-area. The fourth conductive layer includes a fourth terrace portion in the third sub-area.

Abstract: A structure includes a first transistor of a first type, the first transistor including a first channel, a first conductive segment, and a second conductive segment, a second transistor of a second type, the second transistor including a second channel, a third conductive segment, and a fourth conductive segment, and a gate. The first channel extends through the gate between the first and second conductive segments, the second channel extends through the gate between the third and fourth conductive segments and is aligned with the first channel at a center of the first transistor, the first and third conductive segments extend away from the center of the first transistor in opposite directions, and the second and fourth conductive segments extend away from the center of the first transistor in opposite directions.

Abstract: A pixel circuit and a display device including the same are disclosed. The pixel circuit includes: a first driving element including a first electrode connected to a 1-1 th node, a gate electrode connected to a 1-2 th node, and a second electrode connected to a 1-3 th node; and a second driving element including a first electrode connected to a 2-1 th node, a gate electrode connected to a 2-2 th node, and a second electrode connected to a second-third node. A second electrode voltage of the first driving element is transmitted to the gate electrode of the second driving element, and a second electrode voltage of the second driving element is transmitted to the gate electrode of the first driving element.

Abstract: A memory device includes an active region with a drain; a plurality of memory blocks arranged in a first direction; and a plurality of pass transistors formed in the active region and sharing the drain, each one of the plurality of pass transistors configured to transfer an operating voltage from the drain to a corresponding one of the plurality of memory blocks in response to a block select signal. The plurality of pass transistors is divided into first pass transistors and second pass transistors. A channel length direction of the first pass transistors and a channel length direction of the second pass transistors are different from each other.

Abstract: Methods, systems, and devices related to multiplexed signal development in a memory device are described. In one example, an apparatus in accordance with the described techniques may include a set of memory cells, a sense amplifier, and a set of signal development components each associated with one or more memory cells of the set of memory cells. The apparatus may further include a selection component, such as a signal development component multiplexer, that is coupled with the set of signal development components. The selection component may be configured to selectively couple a selected signal development component of the set of signal development components with the sense amplifier, which may support examples of signal development during overlapping time intervals.

Abstract: Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.

Abstract: Systems, methods, and apparatus including multi-direction conductive lines and staircase contacts for semiconductor devices. One memory device includes an array of vertically stacked memory cells, the array including: a vertical stack of horizontally oriented conductive lines, each conductive line comprising: a first portion extending in a first horizontal direction; and a second portion extending in a second horizontal direction at an angle to the first horizontal direction.

Abstract: A memory cell array includes a first and second memory cell, a first and second word line and a first bit line. The first memory cell is in a first row in a first direction. The second memory cell is in a second row in the first direction, and is separated from the first memory cell in a second direction. The first word line extends in the first direction and is coupled to the first memory cell. The second word line extends in the first direction and is coupled to the second memory cell. The first bit line extends in the second direction and is coupled to the first and second memory cell. The first memory cell corresponds to a five transistor memory cell. The first memory cell includes a first active region having a first length, and a second active region having a second length.

Abstract: An apparatus and/or system is described including a memory device or a controller for the memory device to perform heating of the memory device. In embodiments, a controller is to receive a temperature of the memory device and determine that the temperature is below a threshold temperature. In embodiments, the controller activates a heater for one or more memory die to assist the memory device in moving the temperature towards the threshold temperature, to assist the memory device when reading data. In embodiments, the heater comprises a plurality of conductive channels included in the one or more memory die or other on-board heater. Other embodiments are disclosed and claimed.

Abstract: Provided herein may be a memory device, a method of operating the same and a page buffer. The memory device may include a plurality of memory cells and a plurality of page buffers. The plurality of page buffers may be coupled to the plurality of memory cells through a plurality of bit lines. The plurality of page buffers may perform a bit line precharge operation of precharging first bit lines coupled to first memory cells, among the plurality of memory cells, to a first voltage, the bit line precharge operation being included in a memory operation of detecting threshold voltages of the first memory cells, and clamp potentials of second bit lines coupled to second memory cells, among the plurality of memory cells, to a second voltage during the memory operation.

Abstract: Memory subword driver circuits with common transistors are disclosed. In some examples, a subword driver block of a memory device includes a plurality of subword drivers each having an output configured to be coupled to a word line coupled to a plurality of memory cells. The outputs of a first subword driver and a second subword driver of the plurality of subword drivers are coupled to a common transistor and a common word driver line, where the first subword driver and the second subword driver are respectively coupled to a first main word line and a second main word line. In such configuration, the first and second subword drivers are coupled in cascade connection so that, responsive to an active first main word line and an inactive common word driver line, a non-active potential is provided to the first subword driver from the second subword driver via the common transistor.

Abstract: A semiconductor memory device includes a plurality of memory blocks including a plurality of word lines; a plurality of sense amplifying circuits, each being shared by adjacent memory blocks among the memory blocks; a refresh counter suitable for generating a counting address, a value of which increases according to a refresh command; an address storing circuit suitable for storing first and second target addresses by sampling an active address at different times; and a control circuit suitable for activating a word line corresponding to one of the counting address and the first target address according to the refresh command, and activating at least one word line corresponding to one or more of the active address and the second target address according to an active command.

Abstract: A memory circuit includes: memory cells each including a storage transistor corresponding to a predetermined configuration; and a tracking circuit configured to elapse a variable waiting period during which a voltage on a first node decreases from a first level to a second level, the tracking circuit including a first finger circuit coupled between a first node of a tracking bit line and a reference voltage node, the first finger circuit including a first set of first tracking cells, each first tracking cell including a first shadow transistor corresponding to the predetermined configuration, gate terminals of the first shadow transistors being coupled with a tracking word line; and a second finger circuit coupled between the first node and the reference voltage node; and a first switch configured to adjust the variable waiting period by selectively coupling the second finger circuit in parallel with the first finger circuit.

Abstract: A magnetoresistive random-access memory (MRAM) device includes a first cell selectively connected to a first bit line and a second cell selectively connected to a second bit line. The MRAM device further includes a shared transistor connected to the first cell and connected to the second cell. The MRAM device further includes a first selector device and a second selector device. The first selector device is configured to permit current to flow through the first cell to the shared transistor when a voltage applied to the first selector device is larger than a threshold activation voltage. The second selector device is configured to permit current to flow through the second cell to the shared transistor when a voltage applied to the second selector device is larger than a threshold activation voltage. The MRAM cell further includes a word line connected to a gate of the shared transistor.

Abstract: A layout for a 6T SRAM cell is disclosed. The cell layout takes a conventional 6T SRAM cell layout and restructures the layout into a more square cell layout with a single p-channel and a single n-channel across the width of the cell. Restructuring the cell layout reduces the height of wordlines and allows dual wordlines to be placed in the cell to reduce wordline resistance in the cell. Dual pairs of bitlines may also be placed in separate metal layers in the cell layout to reduce bitline resistance.

Abstract: A memory device provides for a multiple-port read operation, and includes an array of bitcells and a control circuit. Each bitcell of the array includes a write wordline port and a first read wordline port. The control circuit provides an output to the write wordline port, and includes as inputs a write select port and a second read wordline port. In a write mode, the control circuit couples the write select port to the output and disables the second read port. In a read mode, the control circuit couples the second read wordline port to the output and disables the write select port, thereby enabling a multiple-port read operation to the array of bitcells.

Abstract: In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.

Abstract: Systems and methods disclosed herein are related to a memory system. In one aspect, the memory system includes a first set of memory cells and a second set of memory cells; a first group of switches, each including: a first electrode connected to first electrodes of the first subset of memory cells, and a second electrode; a second group of switches, each including: a first electrode connected to first electrodes of the second subset of memory cells, and a second electrode; and a third group of switches, each including: a first electrode connected to a first global bit line, and a second electrode connected to the second electrodes of the first group of switches and the second electrodes of the second group of switches.

Abstract: A first transistor, a second transistor, a capacitor, and first to third conductors are included. The first transistor includes a first gate, a source, and a drain. The second transistor includes a second gate, a third gate over the second gate, first and second low-resistance regions, and an oxide sandwiched between the second gate and the third gate. The capacitor includes a first electrode, a second electrode, and an insulator sandwiched therebetween. The first low-resistance region overlaps with the first gate. The first conductor is electrically connected to the first gate and is connected to a bottom surface of the first low-resistance region. The capacitor overlaps with the first low-resistance region. The second conductor is electrically connected to the drain. The third conductor overlaps with the second conductor and is connected to the second conductor and a side surface of the second low-resistance region.

Abstract: A semiconductor storage device includes a plurality of memory cells, bit lines respectively connected to the third memory cells, sense circuits respectively connected to the bit lines, latch circuits respectively connected to the sense circuits, and an input and output circuit connected to a first set of latch circuits via a first data line, a second set of latch circuit via a second data line, and a third set of latch circuits via a third data line. The bit lines are disposed in sequence in a first direction and a group of the sense circuits is disposed in sequence in a second direction crossing the first direction, and two bit lines that are not adjacent in the first direction are connected respectively to two sense circuits in the group that are adjacent in the second direction.

Abstract: A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the

Abstract: Substrates, assemblies, and techniques for an apparatus, where the apparatus includes a gate, where the gate includes a first gate side and a second gate side opposite to the first gate side, a gate dielectric on the gate, where the gate dielectric includes a first gate dielectric side and a second gate dielectric side opposite to the first gate dielectric side, a first dielectric, where the first dielectric abuts the first gate side, the first gate dielectric side, the second gate side, and the second gate dielectric side, a channel, where the gate dielectric is between the channel and the gate, a source coupled with the channel, and a drain coupled with the channel, where the first dielectric abuts the source and the drain. In an example, the first dielectric and the gate dielectric help insulate the gate from the channel, the source, and the drain.

Abstract: An electronic device may include an information signal storage circuit and a write data selection circuit. The information signal storage circuit may be configured to store an information signal during a mode register set operation, and may be configured to output the stored information signal as a mode register information signal. The write data selection circuit may be configured to receive the mode register information and output the mode register information signal as write data.

Abstract: NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.