Transistors Or Diodes Patents (Class 365/72)
  • Patent number: 10971219
    Abstract: A semiconductor device capable of improving operating margins is provided. The semiconductor device comprises a memory circuit including a memory cell comprised of a SOTB transistor, and a mode designation circuit switching operation modes of the memory circuit for a first mode or a second mode. The memory circuit includes a substrate bias generation circuit supplying a substrate bias voltage to the SOTB transistor and a timing signal generation circuit generating a timing signal used for a reading operation or a writing operation of the memory circuit. The substrate bias generation circuit does not supply the substrate bias voltage to the SOTB transistor in the second mode.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: April 6, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Makoto Yabuuchi, Shinji Tanaka
  • Patent number: 10943646
    Abstract: A memory device includes a memory cell, a replica cell, a read circuit, a write wordline, a read wordline, a dummy read wordline, a write bitline, a read bitline, a reference bitline, a sourceline, and a first wiring. The memory cell is electrically connected to the write wordline, the read wordline, the write bitline, the read bitline, and the sourceline. The read circuit outputs a potential based on the result of comparing the potential of the reference bitline and the potential of the read bitline. The replica cell includes a first transistor and a second transistor. The first transistor and the second transistor are electrically connected to each other in series between the bitline and the sourceline. A gate of the first transistor and a gate of the second transistor are electrically connected to a dummy read wordline and the first wiring, respectively.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: March 9, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiko Ishizu, Shuhei Nagatsuka
  • Patent number: 10930510
    Abstract: A method is provided which includes forming a semiconductor substrate having one or more fins. The method includes forming over the fins a plurality of gate structures. The method includes forming gate spacers on sidewalls of the gate structure. The method includes forming a source/drain region on the semiconductor substrate between each adjacent gate spacer. The method includes depositing an interlevel dielectric layer on the source/drain regions and over the gate structures. The method includes depositing a hardmask on the interlevel dielectric layer. The method includes patterning the hardmask to form a plurality of openings and exposing the top surface of each of the source/drain regions. The method includes depositing an optical planarization layer in a portion of the openings and above the top surface of the gate structures. The method includes etching the interlevel dielectric layer in the opening to form an undercut region below the hardmask.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: February 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chanro Park, Kangguo Cheng, Ruilong Xie, Juntao Li
  • Patent number: 10790360
    Abstract: The present disclosure relates to the technical field of semiconductor processes, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method includes: providing a substrate structure including a substrate and a first material layer on the substrate, wherein a recess is formed in the substrate and the first material layer includes a nanowire; forming a base layer on the substrate structure; selectively growing a graphene layer on the base layer; forming a second dielectric layer on the graphene layer; forming an electrode material layer on the substrate structure to cover the second dielectric layer; defining an active region; and forming a gate by etching at least a portion of a stack layer to at least the second dielectric layer so as to form a gate structure surrounding an intermediate portion of the nanowire, where the gate structure includes a portion of the electrode material layer and the second dielectric layer.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: September 29, 2020
    Assignees: Semiconductor Manufacturing (Beijing) International Corporation, Semiconductor Manufacturing (Shanghai) International Corporation
    Inventor: Ming Zhou
  • Patent number: 10783957
    Abstract: In a particular implementation, a method to perform a read operation on a voltage divider bit-cell having first and second transistors and first and second storage elements is disclosed. The method includes: providing a first voltage to a bit-line coupled to the second transistor of the voltage-divider bit-cell; providing a second voltage to a first word-line and providing an electrical grounding to a second word-line; where the first and second word-lines are coupled to the respective first and second resistive memory devices; and determining at least one of first and second data resistances in the respective first and second storage elements based on an output voltage on the bit-line.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: September 22, 2020
    Assignee: Arm Limited
    Inventors: Akhilesh Ramlaut Jaiswal, Mudit Bhargava
  • Patent number: 10726913
    Abstract: Disclosed is a semiconductor device having a memory cell which comprises a transistor having a control gate and a storage gate. The storage gate comprises an oxide semiconductor and is able to be a conductor and an insulator depending on the potential of the storage gate and the potential of the control gate. Data is written by setting the potential of the control gate to allow the storage gate to be a conductor, supplying a potential of data to be stored to the storage gate, and setting the potential of the control gate to allow the storage gate to be an insulator. Data is read by supplying a potential for reading to a read signal line connected to one of a source and a drain of the transistor and detecting the change in potential of a bit line connected to the other of the source and the drain.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: July 28, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideki Uochi, Koichiro Kamata
  • Patent number: 10729012
    Abstract: Methods, systems, and devices for buried lines and related fabrication techniques are described. An electronic device (e.g., an integrated circuit) may include multiple buried lines at multiple layers of a stack. For example, a first layer of the stack may include multiple buried lines formed based on a pattern of vias formed at an upper layer of the stack. The pattern of vias may be formed in a wide variety of spatial configurations, and may allow for conductive material to be deposited at a buried target layer. In some cases, buried lines may be formed at multiple layers of the stack concurrently.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: July 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Stephen W. Russell, Stephen H. Tang
  • Patent number: 10706917
    Abstract: Provided is a semiconductor memory device having a low power consumption write assist circuit. The semiconductor memory device includes multiple word lines, multiple bit line pairs, multiple memory cells, multiple auxiliary line pairs, a write driver circuit, a write assist circuit, and a select circuit. The memory cells are coupled to the word lines and the bit line pairs in such a manner that one memory cell is coupled to one word line and one bit line pair. The auxiliary line pairs run parallel to the bit line pairs in such a manner that one auxiliary line pair runs parallel to one bit line pair. The select circuit couples, to the write driver circuit, one bit line pair selected from the bit line pairs in accordance with a select signal, and couples, to the write assist circuit, an associated auxiliary line pair running parallel to the selected bit line pair.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Nii, Yuichiro Ishii, Yohei Sawada, Makoto Yabuuchi
  • Patent number: 10699766
    Abstract: Word-line drivers, memories, and methods of operating word-line drivers are provided. A word-line driver coupled to an array of memory cells includes a decoder powered by a first power supply. The decoder is configured to decode an address to provide a plurality of word-line signals. The word-line driver also includes a plurality of output stages powered by a second power supply that is different than the first power supply. Each of the output stages includes a first transistor having a gate controlled by a first control signal and an inverter. The inverter is coupled between the first transistor and a ground and has an input coupled to the decoder to receive one of the word-line signals. The word-line driver also includes pull-down circuitry coupled between the gates of the first transistors and the ground and activated by a second control signal.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ali Taghvaei, Atul Katoch
  • Patent number: 10658033
    Abstract: A non-volatile memory device is provided that uses one or more volatile elements. In some embodiments, the non-volatile memory device can include a resistive two-terminal selector that can be in a low resistive state or a high resistive state depending on the voltage being applied. A MOS (“metal-oxide-semiconductor”) transistor in addition to a capacitor or transistor acting as a capacitor can also be included. A first terminal of the capacitor can be connected to a voltage source, and the second terminal of the capacitor can be connected to the selector device. A floating gate of an NMOS transistor can be connected to the other side of the selector device, and a second NMOS transistor can be connected in series with the first NMOS transistor.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: May 19, 2020
    Assignee: CROSSBAR, INC.
    Inventors: Hagop Nazarian, Sung Hyun Jo
  • Patent number: 10643674
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a plurality of sensing components coupled to a controller. The controller is configured to selectively activate a first control line and a second control line to invert signals stored on a latch.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: May 5, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Glen E. Hush
  • Patent number: 10644160
    Abstract: The present disclosure relates to a thin film transistor, a method for fabricating the same, an array substrate, a method for fabricating the same, and a display device. The thin film transistor includes an active layer disposed on a base substrate and a gate stack disposed on the active layer. The gate stack includes: a gate insulating layer disposed on the active layer; a gate electrode disposed on the gate insulating layer; a capping layer disposed on the gate electrode, wherein the capping layer capturing oxygen atoms more easily than the gate electrode.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: May 5, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jiangbo Chen, Young Suk Song, Hongda Sun, Guoying Wang, Wei Liu
  • Patent number: 10593683
    Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. [Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j?2, the jth sub memory cell is arranged over the j-1th sub memory cell.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: March 17, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoaki Atsumi, Shuhei Nagatsuka, Tamae Moriwaka, Yuta Endo
  • Patent number: 10545526
    Abstract: A circuit includes a current mirror circuit (CM circuit) including first and second transistors, a third transistor whose drain is electrically connected to a drain of the second transistor, a switch controlling the current output from the circuit, and first and second memory circuits. A reference current of the CM circuit is input to a drain of the first transistor; a current that is a copy of the reference current is output from the drain of the second transistor. When a current is output from the circuit, the reference current is not input to the CM circuit. A drain current corresponding to a voltage stored in the first memory circuit flows through the second transistor; a drain current corresponding to a voltage stored in the second memory circuit flows through the third transistor. The difference between the two drain currents corresponds to the output current of the circuit.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: January 28, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Inoue, Yoshiyuki Kurokawa, Takashi Nakagawa, Fumika Akasawa
  • Patent number: 10497453
    Abstract: A memory device includes a page buffer unit including a plurality of latches latching each of a plurality of pieces of dummy data of selected memory cells according to a plurality of dummy signals provided by a word line of the selected memory cells, and a control logic comparing a count value of a first count latch among the plurality of latches with a reference count value, determining whether to count a second count latch other than the first count latch according to a result of the comparison, and correcting a level of a read signal provided by the word line of the selected memory cells in a read operation.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: December 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Bae Bang, Joon Suc Jang
  • Patent number: 10490266
    Abstract: A memory in which a write cycle time is longer than time for one clock cycle can be mounted on a processor. The processor includes a processor core, a bus, and a memory section. The memory section includes a first memory. A cell array of the first memory is composed of gain cells. The processor core is configured to generate a write enable signal. The first memory is configured to generate a wait signal on the basis of the write enable signal. The processor core is configured to delay access to the memory section by time for n clock cycles, on the basis of the wait signal. (n+1) clock cycles can be assigned to a write cycle of the first memory.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: November 26, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiko Ishizu, Hikaru Tamura
  • Patent number: 10468421
    Abstract: Some embodiments include memory cells having four transistors supported by a base, and vertically offset from the base. The four transistors are incorporated into first and second inverters having first and second inverter outputs, respectively. A first access transistor gatedly couples the first inverter output to a first comparative bitline, and second access transistor gatedly couples the second inverter output to a second comparative bitline. The first and second access transistors have first and second gates coupled to one another through a wordline. The four transistors are along a first side of the wordline, and are vertically displaced from the wordline. The first and second comparative bitlines are laterally adjacent to one another along a second side of the wordline, and are vertically displaced from the wordline. Some embodiments include memory arrays.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: November 5, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Debra M. Bell, Scott J. Derner
  • Patent number: 10438640
    Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: October 8, 2019
    Assignee: Intel Corporation
    Inventors: Liqiong Wei, Fatih Hamzaoglu, Yih Wang, Nathaniel J. August, Blake C. Lin, Cyrille Dray
  • Patent number: 10236071
    Abstract: A read-only memory (ROM) device includes memory cells, bit-line pairs, a virtual ground line, and a programmable metal track. The memory cells are arranged in an array of rows and columns. Each memory cell stores two bits of data. The virtual ground line is disposed vertically and shared by two adjacent columns. The programmable metal track connects a memory cell to the virtual ground line based on a value of the two bits of data stored in the memory cell.
    Type: Grant
    Filed: September 10, 2017
    Date of Patent: March 19, 2019
    Assignee: NXP B.V.
    Inventors: Rajat Kohli, Patrick Van De Steeg, Jwalant Kumar Mishra, Pankaj Agarwal
  • Patent number: 10153421
    Abstract: Piezoelectric transistors with Schottky contacts and power conversion applications utilizing such piezoelectric transistors are disclosed. A piezoelectric transistor configured in accordance with the inventive concepts disclosed herein may be fabricated to behave as a controllable/switchable active device with an intrinsic anti-parallel diode. Piezoelectric transistors configured in this manner may be utilized in power amplifiers, power converters, as well as in a variety of electronic systems/applications.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: December 11, 2018
    Assignee: Rockwell Collins, Inc.
    Inventor: David W. Cripe
  • Patent number: 10134453
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a plurality of sensing components coupled to a controller. The controller is configured to selectively activate a first control line and a second control line to invert signals stored on a latch.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: November 20, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Glen E. Hush
  • Patent number: 10096684
    Abstract: A metal oxide film includes indium, M, (M is Al, Ga, Y, or Sn), and zinc and includes a region where a peak having a diffraction intensity derived from a crystal structure is observed by X-ray diffraction in the direction perpendicular to the film surface. Moreover, a plurality of crystal parts is observed in a transmission electron microscope image in the direction perpendicular to the film surface. The proportion of a region other than the crystal parts is higher than or equal to 20% and lower than or equal to 60%.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: October 9, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuharu Hosaka, Toshimitsu Obonai, Yukinori Shima, Masami Jintyou, Daisuke Kurosaki, Takashi Hamochi, Junichi Koezuka, Kenichi Okazaki, Shunpei Yamazaki
  • Patent number: 10037294
    Abstract: A semiconductor device including a memory which can perform a pipeline operation is provided. The semiconductor device includes a processor core, a bus, and a memory section. The memory section includes a first memory. The first memory includes a plurality of local arrays. The local array includes a sense amplifier array and a local cell array stacked thereover. The local cell array is provided a memory cell including one transistor and one capacitor. The transistor is preferably an oxide semiconductor transistor. The first memory is configured to generate a wait signal. The wait signal is generated when a request for writing data to the same local array is received over two successive clock cycles from the processor core. The wait signal is sent to the processor core via the bus. The processor core stands by for a request for the memory section on the basis of the wait signal.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: July 31, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Onuki, Wataru Uesugi
  • Patent number: 9997217
    Abstract: Various implementations described herein are directed to an integrated circuit having core circuitry with an array of memory cells arranged in columns. The integrated circuit may include write assist circuitry having a column selector that accesses the memory cells via a bitline coupled to each of the columns. The write assist circuitry may include a first node that couples the column selector to a discharge circuit and a feedback circuit. The write assist circuitry may include a second node that couples a trigger circuit to the discharge circuit and the feedback circuit. The trigger circuit enables the discharge circuit, discharges the second node, and is disabled after discharging the second node. The discharge circuit discharges the first node, and the feedback circuit tracks the first node and disables the discharge circuit.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: June 12, 2018
    Assignee: ARM Limited
    Inventors: Ankur Goel, Munish Kumar, Nitin Jindal, Rahul Mathur, Shruti Aggarwal, Bikas Maiti, Yew Keong Chong
  • Patent number: 9978450
    Abstract: A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: May 22, 2018
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 9865337
    Abstract: A write driver is provided that includes a first write driver inverter that inverts a data signal to drive a gate of a second write driver transistor. The write driver transistor has a terminal coupled to a bit line and another terminal coupled to a boost capacitor. A ground for the first write driver inverter floats during a write assist period to choke off leakage of boost charge from the boost capacitor through the write driver transistor.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: January 9, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Fahad Ahmed, Mukund Narasimhan, Raghav Gupta, Pradeep Raj, Rahul Sahu, Po-Hung Chen, Chulmin Jung
  • Patent number: 9852778
    Abstract: To provide a small, highly reliable memory device with a large storage capacity. A semiconductor device includes a circuit for retaining data and a circuit for reading data. The circuit for retaining data includes a transistor and a capacitor. The circuit for reading data is configured to supply a potential to the circuit for retaining data and read a potential from the circuit for retaining data. The circuit for retaining data and the circuit for reading data are provided in different layers, so that the semiconductor device with a large storage capacity is manufactured.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: December 26, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kiyoshi Kato
  • Patent number: 9842992
    Abstract: A transistor includes: a piezoresistor through which carriers conduct; a source that injects the carriers into the piezoresistor; a drain that receives the carriers from the piezoresistor; a piezoelectric material that is located so as to surround the piezoresistor and applies a pressure to the piezoresistor; and a gate that applies a voltage to the piezoelectric material so that the piezoelectric material applies a pressure to the piezoresistor.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: December 12, 2017
    Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Satoshi Sugahara, Yusuke Shuto, Minoru Kurosawa, Hiroshi Funakubo, Shuichiro Yamamoto
  • Patent number: 9825148
    Abstract: A method of manufacturing a semiconductor device includes forming a transistor in a semiconductor substrate having a first main surface. The transistor is formed by forming a source region, forming a drain region, forming a channel region, forming a drift zone, and forming a gate electrode adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface, between the source region and the drain region. Forming the semiconductor device further includes forming a conductive layer, a portion of the conductive layer being disposed beneath the gate electrode and insulated from the gate electrode.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: November 21, 2017
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Till Schloesser, Thorsten Meyer
  • Patent number: 9818750
    Abstract: Provided is a semiconductor device capable of holding data for a long period. The semiconductor device includes first to third transistors, a capacitor, and a circuit. The third transistor includes a first gate and a second gate. A gate of the first transistor is electrically connected to a first terminal of the capacitor. A first terminal of the first transistor is electrically connected to the second gate. A second terminal of the first transistor is electrically connected to the circuit. A gate of second transistor is electrically connected to a first terminal of the second transistor. A first terminal of the second transistor is electrically connected to the second gate. A second terminal of the second transistor is electrically connected to a first terminal of the capacitor. The circuit is configured to generate a negative potential. A channel formation region of the first transistor preferably includes an oxide semiconductor.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: November 14, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuaki Ohshima, Kiyoshi Kato, Tomoaki Atsumi
  • Patent number: 9666725
    Abstract: A semiconductor device excellent in writing operation is provided. In a structure where a data voltage supplied to a source line is supplied to a node of a memory cell via a bit line, a switch is provided between memory cells connected to the bit line. During a period in which the data voltage is supplied to the node of the memory cell, the switch on the bit line, which is provided between the memory cells, is off. With such a structure, parasitic capacitance of the bit line during a period in which the data voltage is supplied to the node of the memory cell can be reduced. As a result, writing of the data voltage into the memory cell can be performed fast.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: May 30, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takanori Matsuzaki, Tatsuya Onuki
  • Patent number: 9589966
    Abstract: A static random access memory (SRAM) is disclosed. The SRAM includes a plurality of SRAM cells on a substrate, in which each of the SRAM cells comprises: a gate structure on the substrate; a first interlayer dielectric (ILD) layer around the gate structure; a first contact plug in the first ILD layer; a second ILD layer on the first ILD layer; and a second contact plug in the second ILD layer and electrically connected to the first contact plug.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: March 7, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Chao-Hung Lin, Yu-Hsiang Hung, Ssu-I Fu, Jyh-Shyang Jenq
  • Patent number: 9553204
    Abstract: A semiconductor device excellent in writing operation is provided. In a structure where a data voltage supplied to a source line is supplied to a node of a memory cell via a bit line, a switch is provided between memory cells connected to the bit line. During a period in which the data voltage is supplied to the node of the memory cell, the switch on the bit line, which is provided between the memory cells, is off. With such a structure, parasitic capacitance of the bit line during a period in which the data voltage is supplied to the node of the memory cell can be reduced. As a result, writing of the data voltage into the memory cell can be performed fast.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: January 24, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takanori Matsuzaki, Tatsuya Onuki
  • Patent number: 9502103
    Abstract: A semiconductor memory device according to an embodiment includes: a semiconductor substrate; and a memory cell array which is arranged above the semiconductor substrate in a first direction. The memory cell array includes: a semiconductor layer which extends in the first direction; a first conductive line which extends in a second direction crossing the first direction; a variable resistance film which is arranged at an intersection between the semiconductor layer and the first conductive line; a plurality of second conductive lines which are arranged in the second direction sandwiching the semiconductor layer and extend in the first direction; and a plurality of third conductive lines which are electrically connected to the second conductive lines. Two of the second conductive lines neighboring to each other in the second direction with the semiconductor layer interposed therebetween are electrically connected to different third conductive lines.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: November 22, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyoshi Tanimoto, Takashi Izumida
  • Patent number: 9461162
    Abstract: A semiconductor integrated circuit device includes a semiconductor substrate; a plurality of word lines extending parallel to one another on the semiconductor substrate; a plurality of bit lines extending parallel to one another on the semiconductor substrate and arranged to intersect the word lines, thereby delimiting a plurality of crossing regions and a plurality of unit memory cells; a plurality of gate electrodes formed to control respective pairs of unit memory cells adjacent to each other with the word lines interposed therebetween and to contact corresponding word lines on one sides of the crossing regions; storage node contacts respectively formed in spaces of the unit memory cells; and a plurality of bit line contacts formed to contact the respective bit lines on one sides of the crossing regions.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: October 4, 2016
    Assignee: SK HYNIX INC.
    Inventor: Myoung Jin Lee
  • Patent number: 9378776
    Abstract: A semiconductor device with a small cell area and excellent data read/write capability is achieved. In the semiconductor device, a wiring for writing data is provided, and a first transistor with a low off-state current is turned on to supply data to a gate of a second transistor and is turned off so that electric charge corresponding to data is retained. Moreover, a wiring for reading data is provided, and a third transistor is turned on so that data is read out in accordance with the on/off state of the second transistor retaining the electric charge. With this configuration, data write and data read are achieved in the same cycle.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: June 28, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Jun Koyama
  • Patent number: 9349446
    Abstract: A plurality of word lines extend in a first direction and are disposed in a second direction and a third direction. A plurality of bit lines extend in the third direction and are disposed in the first direction and the second direction. A global bit line is coupled in common to the plurality of bit lines. A selection elements is disposed between the bit line and the global bit line. A control circuit is able to perform respective operations of reading, writing, and deletion on the storage element. A resistive element is disposed on the global bit line side with respect to the selection element. The resistive element adjusts a magnitude of a voltage to be applied to the selection element according to a magnitude of a current flowing through the selection element.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: May 24, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kenichi Murooka
  • Patent number: 9318170
    Abstract: A memory cell (1) includes a first storage circuit (2) with a write time t1 and a data retention time ?1 and a second storage circuit (3) with a write time t2 and a data retention time ?2 (t1<t2 and ?1<?2). A row decoder supplies write data to the memory cell (1) via a word line (WL) to write the data on the first storage circuit (2) over a write time tW that is longer than the write time t1 and that is shorter than the write time t2. A PL control circuit (4) supplies power to the memory cell (1) for a time that is longer than the write time t2 when the write data is supplied to the memory cell (1), writes, on the second storage circuit (3), the data written on the first storage circuit (2) once the supply of the write data is stopped, and stops the supply of the power to the memory cell (1) after a lapse of the write time t2 following start of the supply of the write data.
    Type: Grant
    Filed: December 25, 2013
    Date of Patent: April 19, 2016
    Assignee: Tohoku University
    Inventors: Takashi Ohsawa, Tetsuo Endoh
  • Patent number: 9312269
    Abstract: A semiconductor device with a novel structure in which storage capacity needed for holding data can be secured even with miniaturized elements is provided. In the semiconductor device, electrodes of a capacitor are an electrode provided in the same layer as a gate of a transistor and an electrode provided in the same layer as a source and a drain of the transistor. Further, a layer in which the gate of the transistor is provided and a wiring layer connecting the gates of the transistors in a plurality of memories are provided in different layers. With this structure, parasitic capacitance formed around the gate of the transistor can be reduced, and the capacitor can be formed in a larger area.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: April 12, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Tatsuya Onuki
  • Patent number: 9293207
    Abstract: An integrated circuit including data and code non-volatile memory configuration is provided. The integrated circuit comprises a first non-volatile memory array for storing code and a second non-volatile memory array for storing data. The first non-volatile memory array comprises a plurality of first non-volatile memory cells, the first non-volatile memory cells each having a first channel width. The second non-volatile memory array comprises a plurality of second non-volatile memory cells, the second non-volatile memory cells each having a second channel width. The second channel width of the second non-volatile memory cells is larger than the first channel width of the first non-volatile memory cells. This allows the data non-volatile memory cells to have a higher transconductance than the code non-volatile memory cells.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: March 22, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Craig T. Swift
  • Patent number: 9196626
    Abstract: A semiconductor device with a novel structure in which storage capacity needed for holding data can be secured even with miniaturized elements is provided. In the semiconductor device, electrodes of a capacitor are an electrode provided in the same layer as a gate of a transistor and an electrode provided in the same layer as a source and a drain of the transistor. Further, a layer in which the gate of the transistor is provided and a wiring layer connecting the gates of the transistors in a plurality of memories are provided in different layers. With this structure, parasitic capacitance formed around the gate of the transistor can be reduced, and the capacitor can be formed in a larger area.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: November 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Tatsuya Onuki
  • Patent number: 9183341
    Abstract: Some embodiments relate to a system that pre-colors word lines and control lines within a memory cell to avoid timing delays that result from processing variations introduced through multiple patterning lithography processes. The system has a memory element that stores a graphical IC layout with a memory circuit having layout features including a plurality of word lines and a plurality of Y-control lines. A pre-coloring element pre-colors one or more of the plurality of word lines and Y-control lines, to indicate that pre-colored word lines and Y-control lines are to be formed on a same mask of a multiple mask set used for a multiple patterning lithography process. A decomposition element assigns different colors to uncolored layout features of the memory circuit, to indicate that different colored memory features are to be formed on different masks of the multiple mask set.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: November 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Huei Chen, Hung-Jen Liao, Jonathan Tsung-Yung Chang
  • Patent number: 9177614
    Abstract: Some embodiments include apparatuses and methods having a first set of data lines, a second set of data lines, and memory cells located in different levels of the apparatus. In at least one of such embodiments, the memory cells can be arranged in memory cell strings between the first and second set of data lines. Other embodiments including additional apparatuses and methods are described.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: November 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 9135958
    Abstract: An object of the present invention is to provide a semiconductor device combining transistors integrating on a same substrate transistors including an oxide semiconductor in their channel formation region and transistors including non-oxide semiconductor in their channel formation region. An application of the present invention is to realize substantially non-volatile semiconductor memories which do not require specific erasing operation and do not suffer from damages due to repeated writing operation. Furthermore, the semiconductor device is well adapted to store multivalued data. Manufacturing methods, application circuits and driving/reading methods are explained in details in the description.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: September 15, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato
  • Patent number: 9105313
    Abstract: A memory cell includes a first transistor controlling writing of the first date by being in an on state, and holding of the first data by being in an off state, a second transistor in which a potential of one of a source and a drain is a potential of the second data and a potential of a gate is a potential of the first data, and a third transistor which has a conductivity type opposite to that of the second transistor, which has one of a source and a drain electrically connected to the other of the source and the drain of the second transistor, and in which a potential of a gate is a potential of the first data.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: August 11, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Daisuke Matsubayashi
  • Patent number: 9047939
    Abstract: A non-volatile memory device includes an array of memory units, each having resistive memory cells and a local word line. Each memory cell has a first and a second end, the second ends are coupled to the local word line of the corresponding memory unit. Bit lines are provided, each coupled to the first end of each resistive memory cell. A plurality of select transistors is provided, each associated with one memory unit and having a drain terminal coupled to the local word line of the associated memory unit. First and second global word lines are provided, each coupled to a control terminal of at least one select transistor. First and second source lines are provided, each coupled to a source terminal of at least one select transistor. The memory device is configured to concurrently read out all resistive memory cells in one selected memory unit in a read operation.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: June 2, 2015
    Assignee: Crossbar, Inc.
    Inventors: Harry Kuo, Hagop Nazarian
  • Publication number: 20150146470
    Abstract: A circuit comprises a first memory cell, a second memory cell, and a disturb control circuit. The first memory cell has a first port and a second port. The first port is associated with a first write assist circuit. The second port is associated with a second write assist circuit. The second memory cell has a third port and a fourth port. The third port is associated with a third write assist circuit. The fourth port is associated with a fourth write assist circuit. The disturb control circuit is configured to selectively turn on at least one of the first write assist circuit, the second write assist circuit, the third write assist circuit, or the fourth write assist circuit according to whether the first port, the second port, the third port, or the fourth port is determined to be write disturbed.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Atul KATOCH
  • Publication number: 20150138864
    Abstract: Systems and methods presented herein provide a memory system which includes a memory cell array. The memory cell array includes first and second segments with corresponding local bitlines connected to one or more memory cells. The memory cell array also includes first and a second metallization layers. The second metallization layer includes first and second global bitlines. The first metallization layer includes local bitlines. In each of the first segments, local bitlines are connected to one of the first global bitlines. In each of the second segments, local bitlines are connected to one of the second global bitlines.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 21, 2015
    Applicant: LSI CORPORATION
    Inventors: Donald Albert Evans, Rasoju Veerabadra Chary, Rajiv Kumar Roy, Rahul Sahu
  • Publication number: 20150138865
    Abstract: A semiconductor memory device in which capacitance of a capacitor is lower and integration degree is higher. A plurality of memory blocks is connected to one bit line BL_m. A memory block MB_n_m includes a sub bit line SBL_n_m, a write switch, and a plurality of memory cells. A sub bit line SBL_n+1_m adjacent to the sub bit line SBL_n_m is connected to an amplifier circuit AMP_n/n+1_m including two inverters and two selection switches. A circuit configuration of the amplifier circuit can be changed with the selection switches. The amplifier circuit is connected to the bit line BL_m through a read switch. Because of a sufficiently low capacitance of the sub bit line SBL_n_m, potential change due to electric charges of the capacitor in each memory cell can be amplified by the amplifier circuit AMP_n/n+1_m without an error, and the amplified data can be output to the bit line BL_m.
    Type: Application
    Filed: December 4, 2014
    Publication date: May 21, 2015
    Inventor: Yasuhiko TAKEMURA
  • Publication number: 20150138863
    Abstract: An SRAM device includes a plurality of memory cells and a first metallization layer comprising a first pair of bitlines operable to couple to a first segment of the memory cells. The device also includes a second metallization layer comprising a second pair of bitlines operable to couple to a second segment of the memory cells and a write assist line interleaved with the first and second metallization layers to provide a substantially constant coupling capacitance with each of the first and second pairs of bitlines.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 21, 2015
    Applicant: LSI CORPORATION
    Inventors: Rajiv Kumar Roy, Donald Albert Evans, Rasoju Veerabadra Chary, Rahul Sahu