Precharge Patents (Class 365/203)
  • Patent number: 10957408
    Abstract: A non-volatile memory device is disclosed. The non-volatile memory device includes a memory array, a plurality of word lines, a plurality of dummy word lines, a first control circuit and a second control circuit. The plurality of word lines are connected to a plurality of top memory cells and bottom memory cells of a memory string of the memory array. The plurality of dummy word lines are connected to a plurality of dummy memory cells connected between the plurality of top memory cells and bottom memory cells. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a selected word line signal to a selected word line, apply an unselected word line signal to unselected word lines and apply a negative pre-pulse signal to the plurality of dummy word lines.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: March 23, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jianquan Jia, Kaikai You, Ying Cui, Kaiwei Li, Yali Song, Shan Li, An Zhang
  • Patent number: 10949738
    Abstract: A memristor matrix comprising a crossbar array, a multiplexer and a noise control circuit. The noise control circuit may comprise a threshold comparator and a threshold feedback circuit to receive a first threshold and a second threshold and output a threshold signal based, in part, on an output of the threshold comparator.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: March 16, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Suhas Kumar, John Paul Strachan
  • Patent number: 10943667
    Abstract: A memory device is provided. The memory device includes a shift register array having a plurality of shift registers arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of rows comprises a first plurality of shift registers and each of the plurality of columns comprises a second plurality of shift registers. Each of the plurality of rows are associated with a read word line and a write word lines. Each of the plurality of rows are associated with a data input line and a data output line. Each of the plurality of shift arrays comprises a static random access memory.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Hiroki Noguchi, Wei-Chang Zhao
  • Patent number: 10943644
    Abstract: Apparatuses and methods including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example apparatus includes first and second pull-up transistors coupled to a first power supply node, and first and second pull-down transistors coupled to a second power supply node. A first isolation transistor is coupled to a gate of the second pull-down transistor and to a first sense node to which the first pull-up and first pull-down transistors are also coupled. A second isolation transistor is coupled to a gate of the first pull-down transistor and to a second sense node to which the second pull-up and second pull-down transistors are also coupled. An equalization transistor is coupled to gates of the first and second pull-down transistors, and a precharge transistor is coupled to the second power supply node and to the gate of either the first or second pull-down transistors.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Kyuseok Lee
  • Patent number: 10937489
    Abstract: A pre-charge circuit of a static random access memory (SRAM) controller and a pre-charging method thereof are provided. The pre-charge circuit of the SRAM controller includes a first switch, a second switch and a third switch. A first terminal of the first switch is coupled to a working voltage, a second terminal of the first switch is coupled to a first bit line of the SRAM controller, and the first switch is controlled by a first turn-on signal. A first terminal of the second switch is coupled to the working voltage, a second terminal of the second switch is coupled to a second bit line of the SRAM controller, and the second switch is controlled by a second turn-on signal. The third switch is coupled between the first bit line and the second bit line, and the third switch is controlled by a third turn-on signal.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: March 2, 2021
    Assignee: Novatek Microelectronics Corp.
    Inventors: Pin-Han Su, Jen-Hao Liao
  • Patent number: 10923182
    Abstract: A memory device includes an array of memory cells, a bit line connected to the memory cells, and a power supply voltage input terminal configured to receive a power supply voltage at a first voltage level to operate the memory cells at the first voltage level. A bit line precharge circuit has an input terminal configured to receive the power supply voltage at the first voltage level, and the bit line precharge circuit is configured to precharge the bit lines to a second voltage level lower than the first voltage level.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: February 16, 2021
    Inventors: Atul Katoch, Adrian Earle
  • Patent number: 10923185
    Abstract: A memory is provided that is configured to practice both a conventional normal read operation and also a burst mode read operation. During the normal read operation, the memory pre-charges the bit lines in a group of multiplexed columns. Each column has a sense amplifier that latches a bit decision for the column during the normal read operation. If a subsequent read operation addresses the same group of multiplexed columns, the memory invokes the burst-mode read operation during which the bit lines are not pre-charged.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: February 16, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Changho Jung, Keejong Kim, Chulmin Jung, Ritu Chaba
  • Patent number: 10916275
    Abstract: A method for operating a pseudo-dual port (PDP) memory is described. The method includes pre-charging bitline pairs BL and BLB coupled to unselected columns of the PDP memory according to a write operation during a pre-charge operation after a read operation of the PDP memory. The method also includes concurrently pulling-down a bitline pair BL and BLB coupled to a selected column of PDP memory according to the write operation.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: February 9, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Sonia Ghosh, Changho Jung
  • Patent number: 10916303
    Abstract: A resistive memory apparatus and a method of operating a resistive memory apparatus are disclosed. In an embodiment, a resistive memory apparatus can include a memory cell that includes at least two transistors and a resistive element. The resistive memory apparatus can further include a bit line through which data is exchanged with the memory cell, wherein the bit line electronically interconnects with the memory cell, and a bit line regulator connected to the bit line. The bit line regulator can regulate the bit line based on the state of the resistive element. The forming signals and voltage settings can be transmitted over the bit line regulator and across the bit line to the memory cell.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: February 9, 2021
    Assignee: NXP USA, Inc.
    Inventors: Anirban Roy, Yanzhe Tang
  • Patent number: 10896701
    Abstract: A data readout apparatus may include a counter array including an address decoder and a counter circuit, the address decoder being configured to receive an address, the counter circuit being coupled to the address decoder and perform a counting operation based on a column address, a sense amplifier array coupled to the counter array to read out the data from the counter array, a clock driver arranged adjacent to the center of the counter array to distribute clock pulses, a first precharge circuit arranged at one side of the counter array and structured to receive the clock pulses from the clock driver and perform a precharge operation, and a second precharge circuit arranged at the other side of the counter array and structured to receive the clock pulses from the clock driver and perform the precharge operation.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: January 19, 2021
    Assignee: SK hynix Inc.
    Inventor: Min-Seok Shin
  • Patent number: 10896706
    Abstract: A FX phase driver for a memory device having a first driver circuit including a first pull-up circuit configured to drive a first phase signal to a first high state value and a first pull-down circuit configured to drive the first phase signal to a first low state value. The phase driver also including a second driver circuit including a second pull-up circuit configured to drive a second phase signal to a second high state value that is higher than an active state voltage level of a word line in the memory device and a second pull-down circuit configured to drive the second phase signal to a second low state value. The second pull-down circuit includes a stabilization circuit configured to provide a resistive path for a leakage current in the second pull-down circuit when the second pull-up circuit drives the second phase signal to the second high state value.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: January 19, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Charles L. Ingalls, Tae H. Kim
  • Patent number: 10878879
    Abstract: A refresh control method for a memory controller of a memory system is provided. The memory controller is connected with a memory. The memory includes plural memory banks. The refresh control method includes the following steps. Firstly, a refresh state of the memory device is read, and thus a refresh window is realized. Then, a refresh command is issued to the memory device according to the refresh state. The refresh command contains a memory bank number field and a memory bank count field. The memory bank count field indicates a first count. The first count of memory banks are selected from the plural memory banks of the memory device according to the memory bank number field and the first count. Moreover, a refresh operation is performed on the first count of memory banks.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: December 29, 2020
    Assignee: MediaTek Inc.
    Inventors: Der-Ping Liu, Bo-Wei Hsieh
  • Patent number: 10872648
    Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a sense amplifier configured to, during a precharge phase, couple a first gut node of the sense amplifier to a second gut node of the sense amplifier and to a precharge voltage while the first gut node and the second gut node are coupled to a first digit line and a second digit line, respectively, at a first time. The sense amplifier is further configured to, during the precharge phase, decouple the first gut node from the first digit line and decouple the second gut node from the second digit line at a second time that is after the first time. The sense amplifier is further configured to transition to an activation phase in response to an activate command at a third time after the second time to perform a sense operation.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: December 22, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Charles L. Ingalls
  • Patent number: 10867668
    Abstract: A memory and method of performing a write operation in a memory are disclosed. In one aspect of the disclosure, the memory includes a memory cell, a pair of bit lines coupled to the memory cell, a multiplexer, and a pull-up circuit coupled to the multiplexer. The multiplexer may be configured to select the pair of bit lines coupled to the memory cell during the write operation. To increase the write performance of the memory cell, the pull-up circuit is configured to select which of the pair of bit lines is a non-zero bit line during the write operation and to clamp the non-zero bit line through the multiplexer to approximately a power rail voltage. Thus, the pull-up circuit may increase the voltage difference between the non-zero bit line and the zero bit line during the write operation and thus decrease the area and power consumed by a boost capacitance.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: December 15, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Sharad Kumar Gupta, Pradeep Raj, Rahul Sahu, Mukund Narasimhan
  • Patent number: 10861520
    Abstract: Memory device provided with a set of memory cells having a first inverter and a second inverter each connected to a supply line from a first supply line and a second supply line, the memory device being provided with a circuit element configured for: during a start-up phase consecutive to a powering on, applying a first pair of potentials, respectively to the first supply line and the second supply line, in order to pre-load a logic data to some cells depending on the manner in which said cells are respectively connected to said supply lines, then during a second phase, applying a second pair of potentials respectively to said first supply line and the second supply line, so as to symmetrically supply the inverters of each cell.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: December 8, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Adam Makosiej, David Coriat
  • Patent number: 10854273
    Abstract: Apparatuses and methods for controlling the discharge of subword lines are described. The rate of discharge and/or the voltage level discharged to may be controlled. In some embodiments, a main word line may be driven to multiple low potentials to control a discharge of a subword line. In some embodiments, a first word driver line signal and/or a second word driver line signal may be reset to control a discharge of a subword line. In some embodiments, a combination of driving the main word line and the first word driver line signal and/or the second word driver line signal resetting may be used to control a discharge of the subword line.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: December 1, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Toshiyuki Sato
  • Patent number: 10855295
    Abstract: Methods, systems, and devices for section-based data protection in a memory device are described. In one example, a memory device may include a set memory sections each having memory cells configured to be selectively coupled with access lines of the respective memory section. A method of operating the memory device may include selecting at least one of the sections for a voltage adjustment operation based on a determined value of a timer, and performing the voltage adjustment operation on the selected section by activating each of a plurality of word lines of the selected section. The voltage adjustment operation may include applying an equal voltage to opposite terminals of the memory cells, which may allow built-up charge, such as leakage charge accumulating from access operations of the selected memory section, to dissipate from the memory cells of the selected section.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: December 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Richard E. Fackenthal, Daniele Vimercati, Jahanshir Javanifard
  • Patent number: 10848149
    Abstract: A channel circuit of source driver and an operation method thereof are provided. The channel circuit includes a digital-to-analog converter (DAC), a first switch, an output buffer circuit and a pre-charge circuit. The terminals of the first switch are coupled to the first output terminal of the DAC and the first input terminal of the output buffer circuit, respectively. The pre-charge circuit is coupled to the first input terminal of the output buffer circuit. The pre-charge circuit pre-charges the first input terminal of the output buffer circuit when the first switch is turned off during a pre-charge period, and not to pre-charge the first input terminal of the output buffer circuit when the first switch is turned on during a normal operation period.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: November 24, 2020
    Assignee: Novatek Microelectronics Corp.
    Inventors: Yen-Cheng Cheng, Kuang-Feng Sung
  • Patent number: 10811088
    Abstract: Methods and apparatuses to adjust wordline voltage level are presented. An apparatus includes multiple memory cells arranged in multiple rows. A wordline is configured to couple to one row of the multiple rows for a read or write operation. A wordline driving circuit is configured to provide a voltage level to the wordline to facilitate the read or write operation. A tracking circuit is configured to emulate a characteristic of one of the multiple memory cells. A pull-down circuit is configured to lower the voltage level of the wordline by an amount, based on the tracking circuit, to access the one row of the multiple rows in the read or write operation. A method includes emulating a characteristic of one of multiple of memory cells and lowering a voltage level of the wordline by an amount to access one row of the multiple rows in the read or write operation.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: October 20, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Pradeep Raj, Rahul Sahu, Sharad Kumar Gupta
  • Patent number: 10810139
    Abstract: A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: October 20, 2020
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Frederick A. Ware
  • Patent number: 10783938
    Abstract: A memory device Input/Output includes a memory cell having a local bit line. A first IO circuit is coupled to the local bit line and is configured to output a local IO signal to a global bit line. A second IO circuit is coupled to the global bit line and is configured to output a global IO signal. A latch circuit is configured to latch the local IO signal in response to a data signal on the local bit line.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Atul Katoch, Ali Taghvaei
  • Patent number: 10777262
    Abstract: A read register is provided that captures and stores the read result on a read bit line connected to a set of computational memory cells. The read register may be implemented in the set of computational memory cell to enable the logical XOR, logical AND, and/or logical OR accumulation of read results in the read register. The set of computational memory cells with the read register provides a mechanism for performing complex logical functions across multiple computational memory cells connected to the same read bit line.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: September 15, 2020
    Assignee: GSI Technology, Inc.
    Inventors: Bob Haig, Eli Ehrman, Chao-Hung Chang, Mu-Hsiang Huang
  • Patent number: 10770126
    Abstract: A memory device having a plurality sections of memory cells, such as ferroelectric memory cells (hybrid RAM (HRAM) cells) may provide for concurrent access to memory cells within independent sections of the memory device. A first memory cell may be activated, and it may be determined that a second memory cell is independent of the first memory cell. If the second memory cell is independent of the first memory cell, the second memory cell may be activated prior to the conclusion of operations at the first memory cell. Latching hardware at memory sections may latch addresses at the memory sections in order to allow a new address to be provided to a different section to access the second memory cell.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: September 8, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Richard E. Fackenthal
  • Patent number: 10762935
    Abstract: A semiconductor device includes a burst end signal generation circuit and an auto-pre-charge control circuit. The burst end signal generation circuit generates a write burst end signal based on a write flag and a latched burst mode signal in a first burst mode and generates the write burst end signal based on an internal write flag and an internal latched burst mode signal in a second burst mode. The auto-pre-charge control circuit performs an auto-pre-charge operation based on the write burst end signal.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: September 1, 2020
    Assignee: SK hynix Inc.
    Inventors: Myung Kyun Kwak, Woongrae Kim, Seung Hun Lee
  • Patent number: 10755790
    Abstract: A memory device is described with NAND strings and corresponding BL connected to SSL, a first power supply circuit, a second power supply circuit to distribute a higher supply voltage than the first power supply circuit, and a page buffer that generates program/inhibit outputs having a level between the first power supply voltage and a first reference voltage. Data line drivers drive nodes coupled to corresponding BL with a first voltage or a second voltage between the second power supply voltage and a second reference voltage. A data line driver includes a first switch transistor connected between the data line node and the second power supply circuit, a second switch transistor between the data line node and the second voltage reference, and a boost circuit to boost the gate of the first switch transistor above the first supply voltage level to turn on the first switch transistor.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: August 25, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Teng-Hao Yeh, Yi Ching Liu
  • Patent number: 10755771
    Abstract: Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Muhammad M. Khellah, Somnath Paul, Charles Augustine, Turbo Majumder, Suyoung Bang
  • Patent number: 10748604
    Abstract: Circuit for triggering the end of a read operation, for a SRAM memory device, comprising: a plurality of pairs of transistors connected to a bit line and an additional bit line, the transistors each having a source connected to a node, the node and the bit lines being, prior to the activation of said given word line, respectively pre-charged via the pre-charging means, then, when said word line is activated, at least the bit lines are disconnected from the pre-charging means, in such a way as to modify the conduction state of certain transistors and consequently cause a variation in the potential of said node until reaching a determined threshold potential that triggers the emission of an end-of-phase signal.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: August 18, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Adam Makosiej, Pablo Royer
  • Patent number: 10748633
    Abstract: Provided herein is a semiconductor memory device. The semiconductor memory device may include: a memory cell array including a plurality of pages; a voltage supply unit configured to provide operating voltages to the plurality of pages; a plurality of page buffers coupled to a plurality of bit lines of the memory cell array and configured to control and sense currents flowing through the plurality of bit lines in response to a page buffer sensing signal; and a control logic configured to control the voltage supply unit and the plurality of page buffers such that the plurality of pages are successively programmed, and to control a potential level of the page buffer sensing signal depending on a program sequence of the plurality of pages during a program verify operation of a program operation.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: August 18, 2020
    Assignee: SK hynix Inc.
    Inventor: Won Hee Lee
  • Patent number: 10748590
    Abstract: A semiconductor device may include a power supply circuit, a word line control circuit, and a memory circuit. The power supply circuit may drive a pre-charge voltage to a level of an external voltage based on a write initialization signal which is enabled if a command has a predetermined level combination. The word line control circuit may generates two or more word line selection signals that are sequentially counted based on the write initialization signal. The memory circuit may sequentially select a plurality of word lines based on the word line selection signals. The memory circuit may drive bit lines of memory cells connected to the selected word line to the pre-charge voltage. The memory circuit may store data, which are loaded on the bit lines to have a level of the pre-charge voltage, into the memory cells connected to the selected word line.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: August 18, 2020
    Assignee: SK hynix Inc.
    Inventor: Kibong Koo
  • Patent number: 10726906
    Abstract: An operation method of a memory device includes sequentially receiving an active command and a precharge command from an external device, during a first time interval, applying a first activation voltage to a selected wordline in response to the active command, applying a second activation voltage to the selected wordline after the first time interval elapses from a first time point when the first active command is received, and applying a first deactivation voltage to the selected wordline in response to the precharge command. The second activation voltage is lower than the first activation voltage and is higher than the first deactivation voltage.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: July 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyeoungwon Seo
  • Patent number: 10726886
    Abstract: A memory circuit and a memory device including the same are provided. The memory circuit may be connected to a bit line and a complementary bit line and configured to perform precharging on the bit line and the complementary bit line. The memory circuit may include: an equalizer configured to equalize voltage levels of the bit line and the complementary bit line by connecting the bit line with the complementary bit line in response to an equalizing signal; and a precharger configured to precharge the bit line and the complementary bit line to a precharge voltage in response to a precharge signal. The equalizing signal and the precharge signal may be received via separate lines.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: July 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Yong Choi, Sang-Yun Kim, Soo-Bong Chang
  • Patent number: 10720576
    Abstract: A semiconductor device includes: a first switch that uses a first selection signal and a second selection signal to select one of a first voltage and a third voltage or a second voltage and a fourth voltage from the first voltage, the second voltage lower than the first voltage, the third voltage lower than the first voltage, and the fourth voltage lower than the third voltage; a second switch that selects one of a first input signal or a second input signal from the first input signal being the first voltage or the third voltage and the second input signal being the second voltage or the fourth voltage; a third switch that outputs the third voltage in a case where the first voltage and the third voltage are selected by the first switch and the first input signal, which is the first voltage, is selected by the second switch, outputs the first voltage in a case where the first voltage and the third voltage are selected by the first switch and the first input signal, which is the third voltage, is selected by t
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: July 21, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Yusuke Niki
  • Patent number: 10714158
    Abstract: Apparatus and methods are disclosed, including an apparatus having a first transistor configured to be coupled to a first bit line, and a control circuit configured to supply a gate of the first transistor with a first voltage to turn on the first transistor, and to supply the gate of the first transistor with a second voltage higher than the first voltage to strengthen a current drive capability of the first transistor.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: July 14, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Shinichi Miyatake
  • Patent number: 10686634
    Abstract: Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: June 16, 2020
    Assignee: Micron Technology, Inc
    Inventors: Timothy M. Hollis, Markus Balb, Ralf Ebert
  • Patent number: 10672435
    Abstract: Apparatuses for signal boost are disclosed. An example apparatus includes: first and second digit lines coupled to memory cells; a sense amplifier including: first and second transistors having gates operatively coupled to the first digit line and drains coupled to a first node, sources of the first and second transistors coupled to first and second control lines providing first and second power supply voltage respectively; and third and fourth transistors having gates coupled to the second digit line and drains coupled to a second node, sources of the third and fourth transistors coupled to the first and second control lines respectively; a power line coupled to the first node and the second node; and a power switch providing either the first power supply voltage or a third power supply voltage smaller than the first power supply voltage to the power line.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Charles Ingalls, Christopher Kawamura
  • Patent number: 10665292
    Abstract: Devices and methods for sensing a memory cell using a charge transfer device are described. In some examples, the charge transfer device may be coupled with an input transistor of a differential transistor pair that may be coupled with a sense component. The differential transistor pair may be configured to isolate the sense component from the charge transfer device during a read operation. To read the memory cell, a gate of the charge transfer device may be charged to a first voltage. Subsequently, a digit line may be biased to a second voltage by discharging the memory cell onto the digit line. A charge may be transferred, using the charge transfer device, between the digit line and a gate of the input transistor such that the sense component may determine a logic state stored on the memory cell based on the first voltage and the second voltage.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: May 26, 2020
    Assignee: Micron Technology, Inc.
    Inventors: George B. Raad, John F. Schreck
  • Patent number: 10650867
    Abstract: A multi-level sensing circuit for a multi-level memory device configured to “recognize” more than two different voltages. The multi-level voltage sensing circuit may include a pre-charge controller configured to pre-charge a pair of bit lines with a bit-line pre-charge voltage level in response to an equalizing signal during a sensing mode. The multi-level voltage sensing circuit may include a read controller configured to maintain a voltage of the pair of bit lines at the bit-line pre-charge voltage level in response to a read control signal during a sensing operation. The multi-level voltage sensing circuit may include a sense-amplifier configured to generate data of the pair of bit lines during the sensing mode. The multi-level voltage sensing circuit may include a voltage sensor configured to generate the equalizing signal by comparing a bit-line voltage with a reference voltage.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: May 12, 2020
    Assignee: SK hynix Inc.
    Inventors: Hyung Sik Won, Tae Hun Kim
  • Patent number: 10650888
    Abstract: Techniques are provided for tuning the voltages of a circuit for reading a memory cell capable of storing three or more logic states. To read the memory cell, a charge may be transferred between a digit line and a sense component using a charge transfer device. The gate of the charge transfer device may initially be biased to a first voltage and subsequently tuned to a second voltage to optimize the sense window. After biasing the gate of the charge transfer device to the second voltage, the memory cell may discharge its charge onto the digit line, which may result in the digit line being biased to a third voltage. Based on whether the third voltage exceeds the second voltage, the charge transfer device may transfer the charge associated with the memory cell.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: May 12, 2020
    Assignee: Micron Technology, Inc.
    Inventors: George B. Raad, John F. Schreck
  • Patent number: 10634713
    Abstract: A method for testing a semiconductor die is provided. The method includes the following steps: charging a die pad of the semiconductor die to a precharge level; stopping charging the die pad to detect a period of time required for a voltage level of the die pad to change from the precharge level to a reference level, and accordingly generating a detection result; and determining a leakage current of the die pad according to the detection result.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: April 28, 2020
    Assignee: Piecemakers Technology, Inc.
    Inventor: Der-Min Yuan
  • Patent number: 10629590
    Abstract: A resistor-capacitor (RC) delay circuit includes a first capacitor at a first level, a resistor at a second level and a second capacitor at a third level. The second capacitor is electrically connected in parallel with the first capacitor. The second capacitor has a footprint within a footprint of the first capacitor. The resistor is coupled in shunt with the first capacitor and the second capacitor.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: April 21, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Ye Lu, Chao Song, Haitao Cheng
  • Patent number: 10614891
    Abstract: A memory device can include a memory block operatively connected to a common source line and a plurality of bit lines, wherein the memory block includes first and second sub-blocks each having a respective position in the memory block relative to the common source line and the plurality of bit lines. The memory device can be operated by receiving a command and an address from outside the memory device and performing a precharge operation on the memory block in response to the command, using a first precharge path through the memory block or a second precharge path through the memory block based on the respective position of the first or second sub-block that includes a word line that is configured to activate responsive to the address.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: April 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-Hwan Park, Wan-Dong Kim
  • Patent number: 10614876
    Abstract: A memory device include one or more sections of memory banks. Each of the one or more sections may include multiple sensing amplifiers and a digit line to supply voltages to the sensing amplifiers during a refresh of the respective section. The memory device may also include transmission circuitry configured to transmit excess charge remaining on a first digit line of a first section to a second digit line of a second section after a refresh of the first section and before a refresh of the second section.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: April 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Scott E. Smith
  • Patent number: 10614884
    Abstract: A logic circuit is provided including at least two input cells and a sense circuit. The input cells are connected to a common result line. Further, the input cells are operable for influencing an electrical quantity at the result line. The sense circuit is connected to the result line, and is adapted to output a discrete value out of more than two possible values based on the electrical quantity.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin Eckert, Alexander Fritsch
  • Patent number: 10600483
    Abstract: An object of the present disclosure is to provide a content addressable memory realizing higher speed of a search access. A content addressable memory includes: a plurality of memory cells; a match line coupled to the plurality of memory cells; a search line coupled to each of the plurality of memory cells; a match line output circuit coupled to the match line; and a potential changing circuit coupled to the match line and changing the potential of the match line.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: March 24, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Makoto Yabuuchi
  • Patent number: 10600479
    Abstract: A memory device including a first memory sector and a second memory sector, each of which includes a respective plurality of local bit lines, which may be selectively coupled to a plurality of main bit lines. The memory device further includes a first amplifier and a second amplifier, and a routing circuit, arranged between the main bit lines and the first and second amplifiers. The routing circuit includes: a first lower switch, arranged between a first lower main bit line and a first input of the first amplifier; a second lower switch, arranged between the first lower main bit line and a first input of the second amplifier; a first upper switch, arranged between a first upper main bit line and the first input of the first amplifier; and a second upper switch, arranged between the first upper main bit line and the first input of the second amplifier. The second inputs of the first and second amplifiers are coupled to a second lower main bit line and to a second upper main bit line, respectively.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: March 24, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Fabio Enrico Carlo Disegni, Cesare Torti, Davide Manfré
  • Patent number: 10573380
    Abstract: There are provided a memory system and an operating method thereof. A memory system includes: a memory device configured to generate first read voltages and second read voltages, based on initial read voltages and first and second offset voltages, in response to a user read command, and output first data and second data, which are acquired by performing read operations on multi-bit memory cells, based on the first read voltages and the second read voltages; and a memory controller configured to output the user read command, wherein the memory controller includes a state counter configured to count numbers of data bits respectively corresponding to a plurality of threshold voltage states from the first data and the second data, and extract numbers of memory cells respectively included in a plurality of threshold voltage regions divided by the first read voltages and the second read voltages by calculating the counted result.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: February 25, 2020
    Assignee: SK hynix Inc.
    Inventor: Nam Oh Hwang
  • Patent number: 10566073
    Abstract: A test apparatus may be provided. The test apparatus may include a delay compensator configured to generate delayed read data by delaying read data according to a difference between an external turnaround delay value provided externally from the test apparatus and a turnaround delay detection value detected within the test apparatus. The test apparatus may include a determination circuit configured to perform a test result determination operation by comparing the delayed read data with reference data. The turnaround delay detection value may be generated by detecting a time of from a point of time when write data including a read command as the reference data is output to a point of time when the read data is received.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: February 18, 2020
    Assignee: SK hynix Inc.
    Inventor: Jong Ho Jung
  • Patent number: 10559330
    Abstract: A memory device may include a first half memory block, a second half memory block, a row decoder group, and a read/write circuit which may be disposed between the first half memory block and the second half memory block. The read/write circuit may be coupled to the first half memory block and the second half memory block through a first bit line and a second bit line. The row decoder group may be configured to simultaneously select the first half memory block and the second half memory block in response to a single block selection signal.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: February 11, 2020
    Assignee: SK hynix Inc.
    Inventor: Dae Sung Eom
  • Patent number: 10559333
    Abstract: A memory macro includes a first memory cell array, first tracking circuit, first pre-charge circuit coupled to a first end of the first tracking bit line and a second pre-charge circuit coupled to a second end of the first tracking bit line. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first set of control signals, a second set of memory cells configured as a first set of pull-down cells responsive to a second set of control signals, and a first tracking bit line. The first set of pull-down cells and first set of loading cells are configured to track a memory cell of the first memory cell array. The first and second pre-charge circuit are configured to charge the first tracking bit line to a voltage level responsive to a third set of control signals.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: February 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Kuo Su, Cheng Hung Lee, Chiting Cheng, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Pankaj Aggarwal, Jhon Jhy Liaw
  • Patent number: 10553271
    Abstract: Method and Apparatuses for transmitting and receiving commands for a semiconductor device are described. An example apparatus includes: a memory device including a plurality of banks, each bank including a plurality of memory cells; and a memory controller that transmits a first command and a plurality of address signals indicative of a memory cell in a first bank of the plurality of banks at a first time. The first command is indicative of performing a first memory operation, and a second memory operation different from the first memory operation. The memory device receives the first command and the plurality of address signals and further performs the second memory operation to the first bank responsive, at least a part, to the plurality of address signals and the first command.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: February 4, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Michael Richter