Precharge Patents (Class 365/203)
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Patent number: 12190990Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.Type: GrantFiled: September 26, 2023Date of Patent: January 7, 2025Assignee: Rambus Inc.Inventors: James E. Harris, Thomas Vogelsang, Frederick A. Ware, Ian P. Shaeffer
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Patent number: 12190956Abstract: A memory device including a plurality of memory cells, a peripheral circuit configured to perform a read operation of reading data from memory cells connected to a selected word line, and a read operation controller configured to apply a plurality of read voltages to the selected word line, apply a first pass voltage to unselected word lines while first read voltages for determining a program state of memory cells having a threshold voltage higher than a reference voltage among the plurality of read voltages are applied to the selected word line, and apply a second pass voltage higher than the first pass voltage to the unselected word line while second read voltages for determining a program state of memory cells having a threshold voltage lower than the reference voltage among the plurality of read voltages are applied to the selected word line.Type: GrantFiled: April 14, 2022Date of Patent: January 7, 2025Assignee: SK hynix Inc.Inventor: Jae Woong Kim
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Patent number: 12165739Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit may include a memory array with a plurality of memory cells, first logic circuitry, first switching circuitry, first latch circuitry, and second switching circuitry. The first logic circuitry may be configured to generate a first bit line pre-charge signal for a first memory cell of the plurality of memory cells, where the first bit line pre-charge signal is generated in response to a sleep signal. The first switching circuitry may be configured to provide power to one or more bit line of the first memory cell in response to the first bit line pre-charge signal. The first latch circuit may receive the sleep signal and the first bit line pre-charge signal and generate a delayed sleep signal.Type: GrantFiled: August 9, 2023Date of Patent: December 10, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sanjeev Kumar Jain, Sahil Preet Singh, Atul Katoch
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Patent number: 12165731Abstract: A method of operating a memory device is provided. A clock signal is received. Each clock cycle of the clock signal initiates a write operation or a read operation in a memory device. A power nap period is then determined. The power nap period is compared with a clock cycle period to determine that the power nap period is less than the clock cycle period of the clock signal. A header control signal is generated in response to determining that the power nap period is less than the clock cycle period. The header control signal turns off a header of a component of the memory device.Type: GrantFiled: August 10, 2023Date of Patent: December 10, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Chen Lin, Wei Min Chan
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Patent number: 12080340Abstract: A control circuit, a method for reading and writing and a memory are provided. The control circuit includes a pre-charge circuit, an amplification circuit and an equalization circuit. The pre-charge circuit is directly electrically connected to at least one of a bit line or a complementary bit line. The amplification circuit has a first node and a second node. The equalization circuit is connected between the first node and the bit line and between the second node and the complementary bit line.Type: GrantFiled: May 5, 2022Date of Patent: September 3, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Sungsoo Chi, Shuyan Jin, Fengqin Zhang
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Patent number: 12080333Abstract: A semiconductor system including: an operation period adjusting circuit configured to generate operation information for adjusting an operation period, when an input count of an active command during a test mode period is equal to or more than a preset count; and a command generation circuit configured to adjust the input count of the active command applied to a semiconductor device during a preset period, by adjusting the operation period on the basis of the operation information.Type: GrantFiled: January 17, 2022Date of Patent: September 3, 2024Assignee: SK hynix Inc.Inventor: Choung Ki Song
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Patent number: 12080342Abstract: A memory device is provided. The memory device includes a memory cell array having a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of columns include a first plurality of memory cells connected to a first bit line and a second bit line. A pre-charge circuit is connected to the memory cell array. The pre-charge circuit pre-charges each of the first bit line and the second bit line from a first end. A pre-charge assist circuit is connected to the memory cell array. The pre-charge assist circuit pre-charges each of the first bit line and the second bit line from a second end, the second end being opposite the first end.Type: GrantFiled: March 18, 2022Date of Patent: September 3, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Hao Pao, Kian-Long Lim, Chih-Chuan Yang, Jui-Wen Chang, Chao-Yuan Chang, Feng-Ming Chang, Lien-Jung Hung, Ping-Wei Wang
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Patent number: 12071508Abstract: Provided is a novel polymer capable of being used as a hole transfer material for an organic electronic device, particularly, an organic EL device. The polymer of the present disclosure includes a repeating unit represented by Formula (1) as follows in 40 mol % to 100 mol % of the whole repeating unit forming the polymer, wherein at least one of R4 and R5 is an aromatic amino group.Type: GrantFiled: August 14, 2019Date of Patent: August 27, 2024Assignee: LG Chem, Ltd.Inventor: Hisayuki Kawamura
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Patent number: 12068054Abstract: An SRAM controller for performing sequential accesses using internal ports that operate concurrently on different rows. Each internal port includes a row address strobe (RAS) timer that generates clock signals controlling the timing of operations during a RAS phase in which word line decoding is performed once for a group of bit cells being accessed. The RAS phase can involve additional conditioning operations, such as precharging of local bits lines associated with the group of bit cells. The RAS phase is followed by an input/output (IO) phase in which individual bit cells are accessed in sequential address order using a column select signal generated by an IO timer. The RAS phase of a first internal port can be at least partially overlapped by the IO phase of a second internal port to hide the RAS latency of the first internal port. The IO timer can be shared among internal ports.Type: GrantFiled: May 5, 2022Date of Patent: August 20, 2024Assignee: META PLATFORMS TECHNOLOGIES, LLCInventors: Huichu Liu, Daniel Henry Morris, Edith Dallard
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Patent number: 12046287Abstract: A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first and second metal pads, a memory cell array in the memory cell region including cell strings including memory cells, word lines respectively connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings, a control logic in the peripheral circuit region including a precharge control circuit for controlling precharge on partial cell strings among the cell strings and controlling a plurality of data program steps on the memory cells, and a row decoder in the peripheral circuit region for activating at least some of the word lines in response to a control of the control logic.Type: GrantFiled: February 23, 2023Date of Patent: July 23, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Min Joe, Kang-Bin Lee
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Patent number: 11996163Abstract: A circuit includes a memory cell column coupled to a bit line pair and a write circuit that alternately biases a first end of the bit lines toward power supply and reference voltage levels in a write operation. Each of first and second switching circuits at second ends of the bit lines includes first and second logic circuits, each including an input terminal coupled to a corresponding bit line, and first and second switching devices, each including a gate coupled to the corresponding logic circuit. The first logic circuit and switching device couple the corresponding bit line to a power supply node simultaneously with the write circuit biasing the corresponding bit line toward the power supply voltage level, and the second logic circuit and switching device couple the corresponding bit line to a reference node simultaneously with the write circuit biasing the corresponding bit line toward the reference voltage level.Type: GrantFiled: January 12, 2023Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shang-Chi Wu, Yangsyu Lin, Chiting Cheng, Jonathan Tsung-Yung Chang, Mahmut Sinangil
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Patent number: 11978493Abstract: Methods, systems, and devices for deck-level shunting in a memory device are described. A memory device may include memory arrays arranged in a stack of decks over a substrate, and a combination of deck selection circuitry and shunting circuitry may be distributed among the decks to leverage common substrate-based circuitry, such as logic or addressing circuitry. For example, each memory array of a stack may include a set of digit lines and deck selection circuitry, such as deck selection transistors or other switching circuitry, operable to couple the set of digit lines with a column decoder that may be shared among multiple decks. Each memory array of a stack also may include shunting circuitry, such as shunting transistors or other switching circuitry operable to couple the set of digit lines with a plate node, thereby equalizing a voltage across the memory cells of the respective memory array.Type: GrantFiled: December 20, 2022Date of Patent: May 7, 2024Assignee: Micron Technology, Inc.Inventor: Daniele Vimercati
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Patent number: 11961551Abstract: A bitline sense amplifier including: an amplifier which is connected between a first sensing bitline and a second sensing bitline, and detects and amplifies a voltage difference between a first bitline and a second bitline in response to a first control signal and a second control signal; and an equalizer which is connected between a first supply line through which the first control signal is supplied and a second supply line through which the second control signal is supplied, and pre-charges the first bitline and the second bitline with a precharge voltage in response to an equalizing control signal, wherein the equalizer includes an equalizing enable transistor in which a source terminal is connected to the first supply line and performs equalizing in response to the equalizing control signal.Type: GrantFiled: January 27, 2022Date of Patent: April 16, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Soo Bong Chang, Young-Il Lim, Bok-Yeon Won, Seok Jae Lee, Dong Geon Kim, Myeong Sik Ryu, In Seok Baek, Kyoung Min Kim, Sang Wook Park
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Patent number: 11935588Abstract: A memory device according to the present invention may comprise: a memory cell array in which memory cells of a latch structure are connected in matrix form to word lines and bit line pairs composed of bit lines and inverted bit lines; and a driving circuit which, during an ON period in which the word lines activate first memory cells connected to the corresponding word lines, continuously programs or reads n (n is a natural number of 2 or more) second memory cells among the first memory cells through n first bit line pairs.Type: GrantFiled: August 25, 2020Date of Patent: March 19, 2024Inventors: Young Seung Kim, Seung Moon Yoo, Min Chul Jung
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Patent number: 11908542Abstract: Prior knowledge of access pattern is leveraged to improve energy dissipation for general matrix operations. This improves memory access energy for a multitude of applications such as image processing, deep neural networks, and scientific computing workloads, for example. In some embodiments, prior knowledge of access pattern allows for burst read and/or write operations. As such, burst mode solution can provide energy savings in both READ (RD) and WRITE (WR) operations. For machine learning or inference, the weight values are known ahead in time (e.g., inference operation), and so the unused bytes in the cache line are exploited to store a sparsity map that is used for disabling read from either upper or lower half of the cache line, thus saving dynamic capacitance.Type: GrantFiled: December 23, 2019Date of Patent: February 20, 2024Assignee: Intel CorporationInventors: Charles Augustine, Somnath Paul, Turbo Majumder, Iqbal Rajwani, Andrew Lines, Altug Koker, Lakshminarayanan Striramassarma, Muhammad Khellah
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Memory device having improved program and erase operations and operating method of the memory device
Patent number: 11880582Abstract: A method for operating a memory device includes providing a memory block including at least one source select transistor coupled between a source line and a bit line, a plurality of memory cells, and a drain select transistor, controlling a source select line coupled to the at least one source select transistor and a plurality of word lines coupled to the plurality of memory cells to be in a floating state, and applying an erase voltage to the source line and the bit line.Type: GrantFiled: February 11, 2021Date of Patent: January 23, 2024Assignee: SK hynix Inc.Inventors: Byung In Lee, Hee Joung Park, Keon Soo Shim, Sang Heon Lee, Jae Il Tak -
Patent number: 11862241Abstract: A variable resistive memory device includes a memory cell, a first current-applying block, a second current-applying block and a mode setting circuit. The memory cell includes a first electrode, a second electrode, and a memory layer, the memory layer interposed between the first electrode and the second electrode. The first current-applying block is configured to flow a first current to the first electrode that flows from the first electrode to the second electrode. The second current-applying block is configured to flow a second current to the second electrode that flows from the second electrode to the first electrode. The mode setting circuit is configured to selectively provide any one of the first electrode of the first current-applying block and the second electrode of the second current-applying block with a first voltage. When the memory cell is selected, the selected current-applying block, among the first current-applying block and the second current-applying block, is driven.Type: GrantFiled: November 29, 2021Date of Patent: January 2, 2024Assignee: SK hynix Inc.Inventors: Seung Min Baek, Min Chul Shin
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Patent number: 11848045Abstract: Embodiments of the present invention provide a semiconductor integrated circuit of a memory. The semiconductor integrated circuit can comprise a column selection module, a local read-write conversion module, and an amplifier module. The column selection module can be configured to couple a first data line to a bit line and couple a complementary data line to a complementary bit line. The local read-write conversion module can be configured to perform data transmission from at least one of the first data line or the first complementary data line to a second data line. The data transmission can occur during a memory read-write operation and in response to the local read-write conversion module receiving a read write control signal. The amplifier module can be configured to amplify data of the second data line based on a reference signal of a reference data line. The reference signal can serve as a reference for amplifying the data of the second data line.Type: GrantFiled: August 7, 2021Date of Patent: December 19, 2023Assignee: Changxin Memory Technologies, Inc.Inventors: Weibing Shang, Jixing Chen, Xianjun Wu
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Patent number: 11842075Abstract: A storage device comprises a nonvolatile memory configured to store data that is written in size units of a mapping size, and a storage controller configured to transmit a command to the nonvolatile memory. The storage controller includes a host interface configured to receive a write command from a host device, the write command including a command to write first data to a first address, the first data having a first size smaller than the mapping size. The storage controller includes processing circuitry configured to transmit a read command to the nonvolatile memory, to cause the nonvolatile memory to read second data stored in the nonvolatile memory addressed based on the first address, in response to a determination that the first size is smaller than the mapping size and before the first data is received at the storage controller through the host interface.Type: GrantFiled: August 25, 2021Date of Patent: December 12, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Yun Seok Kang, Jae Sub Kim, Yang Woo Roh, Jeong Beom Seo, Kyung Wook Ye
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Patent number: 11790965Abstract: A semiconductor device includes an operation flag generation circuit configured to generate an operation flag at a time when a flag period elapses from a time when an internal setting signal is generated to perform a write operation accompanied by an auto-precharge operation; and an auto-precharge pulse generation circuit configured to generate an auto-precharge pulse by shifting the operation flag by a pulse generation period set by a period code based on divided docks generated by dividing an internal dock.Type: GrantFiled: August 26, 2022Date of Patent: October 17, 2023Assignee: SK hynix Inc.Inventor: Woongrae Kim
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Patent number: 11783877Abstract: A read-write conversion circuit includes: a read-write conversion module, performing a read-write operation in response to a read-write control signal to implement data transmission between each of a local data line, a local complementary data line, and a global data line, data signals of the local data line and data signals of the local complementary data line being opposite in phase during the read-write operation, and a control module, outputting a variable read-write control signal in response to a read-write speed configuration signal to control a speed of the read-write operation of the read-write conversion module to be variable.Type: GrantFiled: August 22, 2021Date of Patent: October 10, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Weibing Shang
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Patent number: 11763862Abstract: An electronic device includes a pre-charge control circuit configured to generate first and second pre-charge signals with pulses that are selectively generated based on a first and second output control signals that are generated during a read operation, and a data processing circuit configured to pre-charge one of first and second internal nodes based on the first and second pre-charge signals, latch internal data based on first and second input control signals, and output data that is generated from the latched internal data to an external device based on the first and second output control signals. The data is generated from the internal data that is transmitted through one of the first and second internal nodes.Type: GrantFiled: July 14, 2021Date of Patent: September 19, 2023Assignee: SK hynix Inc.Inventor: Kwang Soon Kim
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Patent number: 11763863Abstract: Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit may include a memory array with a plurality of memory cells, first logic circuitry, first switching circuitry, first latch circuitry, and second switching circuitry. The first logic circuitry may be configured to generate a first bit line pre-charge signal for a first memory cell of the plurality of memory cells, where the first bit line pre-charge signal is generated in response to a sleep signal. The first switching circuitry may be configured to provide power to one or more bit line of the first memory cell in response to the first bit line pre-charge signal. The first latch circuit may receive the sleep signal and the first bit line pre-charge signal and generate a delayed sleep signal.Type: GrantFiled: April 18, 2022Date of Patent: September 19, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sanjeev Kumar Jain, Sahil Preet Singh, Atul Katoch
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Patent number: 11670357Abstract: Methods, systems, and devices for cell data bulk reset are described. In some examples, a logic state (e.g., a first logic state) may be written to one or more memory cells based on an associated memory device transitioning power states. To write the first logic state to the memory cells, a first subset of digit lines may be driven to a first voltage and a plate may be driven to a second voltage. While the digit lines and plate are driven to the respective voltages, one or more word lines may be driven to the second voltage. In some instances, the word lines may be driven to the second voltage based on charge sharing occurring between adjacent word lines.Type: GrantFiled: June 17, 2021Date of Patent: June 6, 2023Assignee: Micron Technology, Inc.Inventors: Angelo Visconti, Jahanshir J. Javanifard
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Patent number: 11657864Abstract: An in-memory computing apparatus and a computing method thereof are provided. A memory array includes a shifted weight storage area that stores shifted weight values, a shift information storage area that stores the number of shift units, and a shift unit amount storage area that stores a shift unit amount. A shift restoration circuit restores a weight shift amount of a shifted sum-of-products according to the number of shift units of the shifted weight values and a column shift unit amount, so as to generate multiple restored sum-of-products.Type: GrantFiled: December 17, 2021Date of Patent: May 23, 2023Assignee: Winbond Electronics Corp.Inventors: Chi-Shun Lin, Ming-Huei Shieh
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Patent number: 11574689Abstract: A non-volatile memory device, including a non-volatile memory cell array, a sense amplifier, a random access memory (RAM), and a buffer circuit, is provided. The sense amplifier is configured to generate readout data. The RAM is configured to store write-in data. The buffer circuit generates a detection result according to target data and the readout data, and writes the detection result to the RAM.Type: GrantFiled: April 20, 2021Date of Patent: February 7, 2023Assignee: Winbond Electronics Corp.Inventors: Hsing-Yu Liu, Jyun-Yu Lai
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Patent number: 11521673Abstract: A memory device includes an array of memory cells, a bit line connected to the memory cells, and a power supply voltage input terminal configured to receive a power supply voltage at a first voltage level to operate the memory cells at the first voltage level. A bit line precharge circuit has an input terminal configured to receive the power supply voltage at the first voltage level, and the bit line precharge circuit is configured to precharge the bit lines to a second voltage level lower than the first voltage level.Type: GrantFiled: February 15, 2021Date of Patent: December 6, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Atul Katoch, Adrian Earle
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Patent number: 11507280Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of a data interface circuit of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.Type: GrantFiled: May 15, 2020Date of Patent: November 22, 2022Assignee: RAMBUS INC.Inventors: Frederick A. Ware, Robert E. Palmer, John W. Poulton
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Patent number: 11495301Abstract: In one example a semiconductor device has a data latch that includes first and second transmission gates and first and second inverters. The first inverter is connected between a first terminal of the first transmission gate and a first terminal of the second transmission gate. The second inverter is connected between a second terminal of the first transmission gate and a second terminal of the second transmission gate. The data latch is configured to store a datum received at the connection between the first transmission gate and the second inverter, and to store a datum received at the connection between the second transmission gate and the first inverter.Type: GrantFiled: March 31, 2021Date of Patent: November 8, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiaowei Deng, Yunchen Qiu, David Joseph Toops
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Patent number: 11475948Abstract: A memory device and a method of operating the same. The memory device includes a memory cell array including a plurality of memory cells disposed in an area where a plurality of word lines and a plurality of bit lines cross each other; a row decoder including row switches and configured to perform a selection operation on the plurality of word lines; a column decoder including column switches and configured to perform a selection operation on the plurality of bit lines; and a control logic configured to control, in a data read operation, a precharge operation to be performed on a selected word line in a word line precharge period, and to control a precharge operation to be performed on a selected bit line in a bit line precharge period; wherein a row switch connected to the selected word line is weakly turned on in the bit line precharge period.Type: GrantFiled: August 21, 2020Date of Patent: October 18, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Jongryul Kim, Jinyoung Kim, Taehui Na
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Patent number: 11475928Abstract: Embodiments provide a read operation circuit, a semiconductor memory, and a read operation method. The read operation circuit includes: a DBI encoder configured to read read data from a memory bank, and determine whether to invert the read data according to the number of bits of high data in the read data to output global bus data for transmission through a global bus and DBI data for transmission through a DBI signal line, a DBI port being configured to receive the DBI data; a parallel-to-serial conversion circuit configured to perform parallel-to-serial conversion on the global bus data to generate output data of the DQ port; a data buffer module connected to the memory bank through the global bus; and a precharge module connected to a precharge signal line and configured to set an initial state of the global bus to Low.Type: GrantFiled: April 27, 2021Date of Patent: October 18, 2022Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Liang Zhang
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Patent number: 11450363Abstract: The memory device includes a memory cell array including a plurality of memory blocks each including a plurality of strings, wherein the plurality of memory blocks are controlled to have a set temperature; a peripheral circuit for performing a read operation on a selected memory block among the plurality of memory blocks; a temperature detection circuit for detecting a temperature of the memory cell array and generating a temperature detection signal based on the temperature of the memory cell array; and a control logic for controlling the peripheral circuit during the read operation and configured to generate a heating control signal that may control the selected memory block to have the set temperature in response to the temperature detection signal.Type: GrantFiled: May 7, 2021Date of Patent: September 20, 2022Assignee: SK hynix Inc.Inventor: Jae Woong Kim
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Patent number: 11442530Abstract: A memory includes writable memory units. Each memory unit is configurable: in a retention state wherein the memory unit is capable of retaining data until a subsequent power-off of the memory unit, and in a non-retention state wherein the memory unit does not retain data and consumes less power than in the first state. A controller configures any memory unit of the memory having undergone at least one write access since its last power-up to be in the retention state. The controller further configures at least one memory unit of the memory that has not undergone any write access since its last power-up in the non-retention state.Type: GrantFiled: December 2, 2020Date of Patent: September 13, 2022Assignee: STMicroelectronics (Grenoble 2) SASInventor: Michael Giovannini
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Patent number: 11423975Abstract: A novel memory device is provided. A first cell array including a plurality of memory cells and a second cell array including a plurality of memory cells are provided to overlap with each other. Two bit lines included in the first bit line pair are electrically connected to part of the memory cells included in the first cell array and to part of the memory cells included in the second cell array. Two bit lines included in the second bit line pair are electrically connected to part of the memory cells included in the first cell array and to part of the memory cells included in the second cell array. In the first cell array, one of the bit lines included in the second bit line pair includes a region overlapping with part of the first bit line pair. In the second cell array, the other of the bit lines included in the second bit line pair includes a region overlapping with part of the first bit line pair.Type: GrantFiled: February 13, 2019Date of Patent: August 23, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yuki Okamoto, Tatsuya Onuki
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Patent number: 11422713Abstract: Methods, systems, and devices for a memory error indicator related to high-reliability applications are described. A memory device may perform error detection procedures to monitor trends in the quantity of bit errors as an indication of the health of the memory device. A memory device may perform error detection procedures concurrently with refresh procedures to detect a quantity of errors (e.g., in a memory array) without degrading the performance of the device or the memory array. The memory device may compare a quantity of errors detected (e.g., in the memory array) with one or more previously detected quantities of errors to determine one or more differences in the quantities of errors. The memory device may generate an error metric based on the differences, and may determine whether the error metric satisfies a threshold. The memory device may output a status indicator (e.g., to a host device) based on whether the error metric satisfies the threshold.Type: GrantFiled: January 25, 2021Date of Patent: August 23, 2022Assignee: Micron Technology, Inc.Inventors: Erika Prosser, Aaron P. Boehm, Debra M. Bell
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Patent number: 11423977Abstract: The disclosed write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.Type: GrantFiled: August 3, 2020Date of Patent: August 23, 2022Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Hidehiro Fujiwara, Chih-Yu Lin, Sahil Preet Singh, Hsien-Yu Pan, Yen-Huei Chen, Hung-Jen Liao
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Patent number: 11417400Abstract: Techniques are described for optimizing the peak current during a program operation by controlling a timing and ramp rate of a program-inhibit voltage signal as a function of a program loop number and/or program progress. A transition voltage between a regulated ramp up rate and an unregulated ramp up rate can also be adjusted. For initial and final sets of program loops in a program operation, the ramp up of the program-inhibit voltage signal can occur early so that it overlaps with operations of sense circuits in updating their latches based on results from a verify test in a previous program loop. For an intermediate set of program loops, the overlap is avoided. The ramp up rate can be larger and the transition voltage smaller for the initial and final sets of program loops compared to the intermediate set of program loops.Type: GrantFiled: January 31, 2020Date of Patent: August 16, 2022Assignee: SanDisk Technologies LLCInventors: Yu-Chung Lien, Huai-Yuan Tseng, Deepanshu Dutta
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Patent number: 11404115Abstract: The disclosure introduces a write assist scheme that boost the word line of a selected memory cell by using a parasitic capacitor element coupled between the word line and a bit line of at least one unselected memory cell. The SRAM includes a word line, a first bit line, a second bit line, a first memory cell coupled to the first bit line and the word line, a second memory cell coupled to the second bit line and the word line, and a write assist circuit coupled to the second bit line. The write assist circuit is configured to clamp the second bit line to the word line during a write operation of the first memory cell.Type: GrantFiled: October 30, 2020Date of Patent: August 2, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Yen-Huei Chen
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Patent number: 11379187Abstract: A semiconductor device includes a cell array, a computation circuit, and a control circuit. The cell array includes a plurality of unit cells configured to store a plurality of first signals by a write operation and to output a plurality of output signals corresponding to the first signals by a read operation. The computation circuit includes a plurality of unit computation circuits receiving the plurality of output signals and being set according to a plurality of second signals during a computation operation. The control circuit is configured to control the cell array and the computation circuit during the write operation, the read operation, and the computation operation.Type: GrantFiled: March 30, 2020Date of Patent: July 5, 2022Assignees: SK hynix Inc., Korea Advanced Institute of Science and Technology (KAIST)Inventors: Jin-O Seo, Hyuk-Jin Lee, SeongHwan Cho
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Patent number: 11367496Abstract: The reference cells used for reading out data are tested efficiently so as to improve the reliability of the readout data. A memory circuit includes multiple memory arrays, a selection circuit, and a sense amplifier. The selection circuit selects values output from memory cells in any of the multiple memory arrays so as to supply a first value and a second value. A sense amplifier has a first input terminal and a second input terminal. The sense amplifier amplifies and outputs the first value supplied to the first input terminal in reference to the second value supplied to the second input terminal.Type: GrantFiled: July 25, 2019Date of Patent: June 21, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hiroyuki Tezuka, Masami Kuroda
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Patent number: 11360704Abstract: Methods, systems, and devices related to multiplexed signal development in a memory device are described. In one example, an apparatus in accordance with the described techniques may include a set of memory cells, a sense amplifier, and a set of signal development components each associated with one or more memory cells of the set of memory cells. The apparatus may further include a selection component, such as a signal development component multiplexer, that is coupled with the set of signal development components. The selection component may be configured to selectively couple a selected signal development component of the set of signal development components with the sense amplifier, which may support examples of signal development during overlapping time intervals.Type: GrantFiled: December 2, 2019Date of Patent: June 14, 2022Assignee: Micron Technology, Inc.Inventors: Dmitri A. Yudanov, Shanky Kumar Jain
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Patent number: 11348624Abstract: Embodiments herein describe a multi-port memory system that includes one or more single port memories (e.g., a memory that can perform only one read or one write at any given time, referred to as a 1W or 1R memory). That is, the multi-port memory system can perform multiple read and writes in parallel (e.g., 1R/1W, 1R/3W, 2R/2W, 3R/1W, etc.) even though the memory in the system can only perform one read or one write at any given time. The advantage of doing so is a reduction in area and power.Type: GrantFiled: March 23, 2021Date of Patent: May 31, 2022Assignee: XILINX, INC.Inventors: Richard Lewis Walke, John Edward Mcgrath
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Patent number: 11342022Abstract: Multi-stage content addressable memory devices are described. Some embodiments relate to memory devices including a plurality of rows of memory cells, multiple match lines and multiple pre-charge circuits. A first row of the plurality of rows includes a first segment and a second segment. The first segment may include a first subset of the memory cells of the first row and the second segment may include a second subset of the memory cells of the first row. The first match line is coupled to the memory cells of the first subset, and the second match line is coupled to the memory cells of the second subset. The first pre-charge circuit is configured to pre-charge the first match line to a first pre-charge voltage, and the second pre-charge circuit is configured to pre-charge the second match line to a second pre-charge voltage different from (e.g., greater than) the first pre-charge voltage.Type: GrantFiled: November 3, 2020Date of Patent: May 24, 2022Assignee: MEDIATEK Singapore Pte. Ltd.Inventors: Chetan Deshpande, Gajanan Sahebrao Jedhe, Ritesh Garg, Gaurang Prabhakar Narvekar, Yi-Wei Chen
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Patent number: 11328774Abstract: The present disclosure discloses a ternary content addressable memory based on a memory diode, which includes a plurality of kernel units having functions of storing data, erasing/writing data, and comparing data; the kernel units are arranged in an array, all kernel units in a unit of row are connected to a same matching line, and all kernel units in a unit of column are connected to a same pair of complementary search signal lines; the kernel unit includes two memory diodes; top electrodes of a first memory diode and a second memory diode are respectively connected to a pair of complementary search signal lines, and bottom electrodes of the first memory diode and the second memory diode are connected to a same matching line.Type: GrantFiled: July 16, 2018Date of Patent: May 10, 2022Assignee: ZHEJIANG UNIVERSITYInventors: Yi Zhao, Bing Chen
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Patent number: 11295799Abstract: A device for performing a refresh operation includes a row control circuit and a row decoder. The row control circuit is configured to generate a bank active signal and a row address for controlling an active operation for a first memory bank based on a refresh signal. The row control circuit is also configured to generate the bank active signal for controlling the active operation for a second memory bank based on a power control signal. The row decoder is configured to receive the bank active signal and the row address to control the active operation for the first memory bank and the second memory bank.Type: GrantFiled: July 16, 2020Date of Patent: April 5, 2022Assignee: SK hynix Inc.Inventors: Kyung Mook Kim, Do Hong Kim, Woongrae Kim, Sang Il Park, Sang Woo Yoon, Jong Seok Han
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Patent number: 11296716Abstract: A multi-branch analog multiplexer (anamux) includes protection circuitry to help dissipate both positive and negative injected current without increasing the size of hardening transistors in each branch, thereby avoiding increased leakage current and enabling an analog to digital converter to operate with the required accuracy. The protection circuitry is tied to the body of the hardening transistor to lower the threshold voltage of the hardening device, thereby enabling the hardening device to handle more of the injected current.Type: GrantFiled: December 4, 2020Date of Patent: April 5, 2022Assignee: NXP USA, Inc.Inventor: Wenzhong Zhang
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Patent number: 11289135Abstract: Apparatuses for controlling precharge timings in a semiconductor device are described. An example apparatus includes first and second memory and a precharge timing circuit. The first memory includes a first memory bank including a first data line and a second memory bank including a second data line. The second memory includes a third memory bank including a third data line and a fourth memory bank memory bank including a fourth data line. The precharge timing circuit provides first, second, third and fourth precharge activation signals. The first, second, third and fourth precharge activation signals activate precharge of the first, second, third and fourth data lines, respectively. The precharge timing circuit provides the first and second precharge activation signals at different times from each other. The precharge timing circuit provides the third and fourth precharge activation signals at different times from each other.Type: GrantFiled: December 8, 2020Date of Patent: March 29, 2022Assignee: Micron Technology, Inc.Inventor: Shigeyuki Nakazawa
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Patent number: 11270752Abstract: A semiconductor device includes a peripheral circuit and a core circuit. The peripheral circuit enters a smart refresh mode in which a smart refresh operation is performed based on a command. The peripheral circuit generates a latch address signal from a target address signal to output the latch address signal through a global input/output (I/O) line in the smart refresh mode. The core circuit performs an adding operation and a subtracting operation of the latch address signal to generate first and second internal address signals. The core circuit performs the smart refresh operation for first and second banks based on the first and second internal address signals.Type: GrantFiled: September 3, 2020Date of Patent: March 8, 2022Assignee: SK hynix Inc.Inventor: No Geun Joo
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Patent number: 11263946Abstract: Disclosed are a reference voltage generating circuit and a display device. The reference voltage generating circuit includes a timing control circuit, a digital-to-analog conversion circuit, an operational amplifier circuit, a drive circuit, a switch control circuit, a first switch circuit, and a second switch circuit. The switch control circuit generates a control signal according to a frame start signal and a clock signal provided by the timing control circuit, and outputs the control signal to the first switch circuit and the second switch circuit to control the channels inside the first switch circuit and the second switch circuit to be turned on sequentially, such that an analog voltage signal output by the digital-to-analog conversion circuit can be output to the drive circuit through the first switch circuit, the operational amplifier circuit and the second switch circuit, to provide a reference voltage signal for the drive circuit.Type: GrantFiled: May 21, 2021Date of Patent: March 1, 2022Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Gege Peng, Xiaoyu Huang
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Patent number: 11257528Abstract: A memory device includes memory cells operably connected to column signal lines and to word signal lines. The column signal lines associated with one or more memory cells to be accessed (e.g., read) are precharged to a first voltage level. The column signal lines not associated with the one or more memory cells to be accessed are precharged to a second voltage level, where the second voltage level is less than the first voltage level.Type: GrantFiled: December 7, 2020Date of Patent: February 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Ed McCombs