Precharge Patents (Class 365/203)
  • Patent number: 10332585
    Abstract: A semiconductor memory apparatus includes a driving voltage providing circuit suitable for selectively providing a first driving voltage, a second driving voltage, a third driving voltage, a ground voltage, and a precharge voltage to a first driving line and a second driving line in response to an active signal, a cell characteristic information signal, and a precharge signal. The semiconductor memory apparatus also includes a sense amplifier suitable for operating by being applied with voltages provided from the first and second driving lines.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: June 25, 2019
    Assignee: SK hynix, Inc.
    Inventors: Jung Hwan Lee, Dae Yong Shim, Kang Seol Lee
  • Patent number: 10325650
    Abstract: A semiconductor storage device includes an SRAM memory cell composed of a drive transistor, a transfer transistor and a load transistor, an I/O circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the I/O circuit between a resume standby mode and a normal operation mode, wherein the I/O circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: June 18, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yuichiro Ishii
  • Patent number: 10325649
    Abstract: A ternary sense amplifier and an SRAM array realized by the ternary sense amplifier are provided. The ternary sense amplifier comprises the 1st CNFET transistor, the 2nd CNFET transistor, the 3rd CNFET transistor, the 4th CNFET transistor, the 5th CNFET transistor, the 6th CNFET transistor, the 7th CNFET transistor, the 8th CNFET transistor, the 9th CNFET transistor, the 10th CNFET transistor, the 11th CNFET transistor, the 12th CNFET transistor and the 13th CNFET transistor; the SRAM array comprises a ternary sense amplifier, a ternary memory array, the 1st inverter, the 2nd inverter, the 3rd inverter, the 4th inverter, the 14th CNFET transistor, the 15th CNFET transistor, the 16th CNFET transistor, the 17th CNFET transistor, the 18th CNFET transistor and the 19th CNFET transistor; it features in low power consumption, less postponement and high yield of chips.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: June 18, 2019
    Assignee: Ningbo University
    Inventors: Pengjun Wang, Daohui Gong, Yaopeng Kang, Huihong Zhang
  • Patent number: 10320591
    Abstract: A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals. Equalization signals generated based, at least in part, on contents of the shift-register storage elements are used to adjust respective signal levels representative of one or more bits of the second sequence of data bits.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: June 11, 2019
    Assignee: Rambus Inc.
    Inventors: Thomas J. Giovannini, Abhijit Abhyankar
  • Patent number: 10304523
    Abstract: A memory device with low power consumption is provided. The memory device includes a sense amplifier, bit lines, memory cells, and first transistors. The bit lines are provided over a layer comprising the sense amplifier. The memory cells are provided over a layer comprising the bit lines. The memory cell includes a second transistor and a capacitor. The sense amplifier and the bit lines are electrically connected to each other through the first transistors. The sense amplifier may include at least one layer of a conductor.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: May 28, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Tatsuya Onuki
  • Patent number: 10269410
    Abstract: A semiconductor device is disclosed, which relates to a technology for a sense-amplifier (sense-amp) configured to compensate for mismatch of a sensing bit-line. The semiconductor device includes a sense-amplifier configured to selectively control connection between a pair of bit lines and a pair of sensing bit lines in response to a connection control signal in an offset compensation period, and precharge a pull-down power-supply line with a bit line precharge voltage level in the offset compensation period. The semiconductor device also includes a pull-down voltage controller configured to increase a voltage of the pull-down power-supply line by a predetermined level in response to a pull-down control signal in the offset compensation period.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: April 23, 2019
    Assignee: SK hynix Inc.
    Inventors: Hyung Sik Won, Jae Jin Lee
  • Patent number: 10236053
    Abstract: Methods, devices, and systems are disclosed that generally perform a time delay determination of a voltage change on a signal node to determine a corresponding signal value on another node causing the voltage change. In an example the circuit device includes a first circuit configured to couple, when enabled, a signal value onto a first node, and a read circuit having an input coupled to the first node. The read circuit is configured to effect a voltage transition of a signal node at a variable rate corresponding to the voltage of the first node, and to determine the signal value based upon a time-to-transition measurement of the signal node.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: March 19, 2019
    Inventor: Ravindraraj Ramaraju
  • Patent number: 10209837
    Abstract: According to one embodiment, a display device comprises pixel electrodes formed in a display area, drive electrodes opposed to the pixel electrodes, first and second line groups formed in a non-display area, a first switch configured to apply a voltage for display or a drive signal to the drive electrodes, and a scanner configured to control the first switch. In the above structure, the first and second line groups are disposed with a space between the first line group and the second line group, and at least a part of the scanner is disposed in the space between the first line group and the second line group.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: February 19, 2019
    Assignee: Japan Display Inc.
    Inventors: Toshiaki Fukushima, Hiroshi Mizuhashi
  • Patent number: 10186207
    Abstract: A display device includes pixels at respective crossing regions of scan lines and data lines, a scan driver that is configured to supply a scan signal to the scan lines, and a data driver that is configured to supply a pre-emphasis voltage to the data lines using a first constant for controlling a voltage value of the pre-emphasis voltage, and using a second constant for controlling a supply time of the pre-emphasis voltage, and supply data signals to the data lines after the supply of the pre-emphasis voltage, wherein at least one of the first or second constants is stored in each channel corresponding to each of the data lines.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: January 22, 2019
    Assignees: Samsung Display Co., Ltd., Korea Advanced Institute of Science and Technology
    Inventors: Oh Jo Kwon, Ji Woong Kim, Choong Sun Shin, Joo Hyung Lee, Jun Suk Bang, Gyu Hyeong Cho
  • Patent number: 10170175
    Abstract: A memory device with low power consumption is provided. The memory device includes a sense amplifier, bit lines, memory cells, and first transistors. The bit lines are provided over a layer comprising the sense amplifier. The memory cells are provided over a layer comprising the bit lines. The memory cell includes a second transistor and a capacitor. The sense amplifier and the bit lines are electrically connected to each other through the first transistors. The sense amplifier may include at least one layer of a conductor.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: January 1, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Tatsuya Onuki
  • Patent number: 10157654
    Abstract: A device includes memory cells, a reference circuit, and a sensing unit. The reference circuit includes a first reference switch, a second reference switch, and reference storage units. The first reference switch is turned on when a reference word line is activated. The second reference switch is turned on when the reference word line is activated. The reference storage units include a first reference storage unit and a second reference storage unit. The first reference storage unit generates a first signal having a first logic state when the first reference switch is turned on. The second reference storage unit generates a second signal having a second logic state when the second reference switch is turned on. The sensing unit determines a logic state of the bit data of one of the memory cells according to the first signal and the second signal.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Fu Lee, Yu-Der Chih, Hon-Jarn Lin, Yi-Chun Shih
  • Patent number: 10141070
    Abstract: A semiconductor device may be provided. The semiconductor device may include sense-amplifier test device. The sense-amplifier test device may include a drive signal generator configured to generate a test voltage applying signal for supplying a ground voltage to a pull-up power-supply line of a sense-amplifier. The sense-amplifier test device may include a sense-amplifier driver configured to supply a ground voltage to the pull-up power-supply line of the sense-amplifier, based on the test voltage applying signal.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: November 27, 2018
    Assignee: SK hynix Inc.
    Inventors: Jong Seok Han, Byeong Cheol Lee
  • Patent number: 10133493
    Abstract: A Dynamic Random Access Memory (DRAM) controller includes a memory interface and a processor. The memory interface is configured to communicate with a DRAM including one or more memory banks. The processor is configured to receive Input/Output (I/O) commands, each I/O command addressing a respective memory bank and a respective row within the memory bank to be accessed in the DRAM, to further receive one or more indications, indicative of likelihoods that a subsequent I/O command will address a same row in a same memory bank as a previous I/O command, to adaptively set, based on the indications, a policy of deactivating rows of the DRAM, and to execute the I/O commands in the DRAM in accordance with the policy.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: November 20, 2018
    Assignee: Marvell World Trade Ltd.
    Inventors: Michael Weiner, Hunglin Hsu, Nadav Klein, Junhua Xu, Chia-Hung Chien
  • Patent number: 10102900
    Abstract: A semiconductor device may include a word line selector configured to generate an active signal for selecting a word line, based on a row address. The active signal may be divided into a read active signal generated based on a read command and a write active signal generated based on a write command.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: October 16, 2018
    Assignee: SK hynix Inc.
    Inventor: Sun Hye Shin
  • Patent number: 10095577
    Abstract: Provided herein is a memory system and an operation method thereof. The memory system may include a memory controller including a read retry table in which a plurality of codes are stored, and configured to output a selected code among the plurality of codes during a read retry operation. The memory system may include a memory device configured to store data, and perform the read retry operation according to the codes received from the memory controller.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: October 9, 2018
    Assignee: SK hynix Inc.
    Inventor: Heon Jin Choo
  • Patent number: 10083755
    Abstract: A discharge circuit includes first and second transistors of a first polarity, third and fourth transistors of a second polarity, and first and second current sources having first ends electrically connected to first end of the third transistor and first end of the fourth transistor, respectively, and second ends supplied with a first voltage. First end of the first transistor is supplied with a second voltage higher than the first voltage. First end of the second transistor is electrically separated from the first end of the first transistor. Gate and second end of the first transistor, gate of the second transistor, and second end of the third transistor are electrically connected to one another. Second end of the second transistor, gate of the third transistor, and second end and gate of the fourth transistor are electrically connected to one another.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: September 25, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hicham Haibi, Katsuaki Sakurai
  • Patent number: 10074641
    Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: September 11, 2018
    Assignee: Taiwan Semicondcutor Manufacturing Company
    Inventors: Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang, Kuo-Nan Yang, Chung-Hsing Wang
  • Patent number: 10074413
    Abstract: According to one embodiment, a semiconductor storage device includes: a first bank that includes a first memory cell group and writes data into the first memory cell group upon receipt of a first command; a second bank that includes a second memory cell group and writes data into the second memory cell group upon receipt of the first command; and a delay controller that issues the first command for the first bank upon receipt of a second command, and issues the first command for the second bank after an interval of at least a first period.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: September 11, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Fumiyoshi Matsuoka
  • Patent number: 10068641
    Abstract: A semiconductor storage device includes an SRAM memory cell composed of a drive transistor, a transfer transistor and a load transistor, an I/O circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the I/O circuit between a resume standby mode and a normal operation mode, wherein the I/O circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: September 4, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yuichiro Ishii
  • Patent number: 10068514
    Abstract: An electronic paper display apparatus including a display driving unit, an electronic paper display panel and a detection circuit unit is provided. The display driving unit generates at least one driving signal. The electronic paper display panel is coupled to the display driving unit. The display driving unit drives the electronic paper display panel to display an image by the at least one driving signal, and the electronic paper display panel outputs the at least one driving signal. The detection circuit unit is coupled to the electronic paper display panel to receive the at least one driving signal outputted by the electronic paper display panel, and detect a display status of the electronic paper display panel according to the at least one driving signal. Besides, a detection method of an electronic paper display apparatus is also provided.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: September 4, 2018
    Assignee: E Ink Holdings Inc.
    Inventors: Sheng-Long Lin, Yao-Te Tseng, Ian French, Pei-Sheng Lee, Feng-Chuan Yeh, Po-Sen Chen
  • Patent number: 10055288
    Abstract: A controller device and an operation method for a non-volatile memory with 3-dimensional architecture are provided. The controller device includes an error checking and correcting (ECC) circuit and a controller. The controller is coupled to the non-volatile memory and the ECC circuit. The controller may access a target wordline of the non-volatile memory in accordance with a physical address. The controller groups a plurality of wordlines of the non-volatile memory into a plurality of wordline groups, wherein different wordline groups have different codeword structures. The controller controls the ECC circuit according to the codeword structure of the wordline group of the target wordline, and the ECC circuit generates a codeword to be stored in the target wordline or check a codeword from the target wordline under control of the controller.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: August 21, 2018
    Assignee: VIA Technologies, Inc.
    Inventors: Ying Yu Tai, Jiin Lai, Jiangli Zhu
  • Patent number: 10037819
    Abstract: A semiconductor memory device may include a row address generating circuit, a row active pulse generating circuit and a word line activating circuit. The row address generating circuit may generate a row address in response to a refresh command, a row active pulse, and a normal address. The row active pulse generating circuit may generate a row active pulse in response to a refresh signal and an active signal. The word line activating circuit may selectively enable a word line in response to the row address and the row active pulse.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: July 31, 2018
    Assignee: SK hynix Inc.
    Inventor: Jae II Kim
  • Patent number: 10026468
    Abstract: This description is directed to a dynamic random access memory (DRAM) array having a plurality of rows and a plurality of columns. The array further includes a plurality of cells, each of which are associated with one of the columns and one of the rows. Each cell includes a capacitor that is selectively coupled to a bit line of its associate column so as to share charge with the bit line when the cell is selected. There is a segmented word line circuit for each row, which is controllable to cause selection of only a portion of the cells in the row.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: July 17, 2018
    Assignee: NVIDIA CORPORATION
    Inventor: William James Dally
  • Patent number: 10014033
    Abstract: Apparatus include an array of memory cells, a controller to perform access operations on the array of memory cells, a clock signal node, a counter having an input selectively connected to the clock signal node, and a clock generator having an output connected to the input of the counter.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: July 3, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Terry Grunzke
  • Patent number: 10008247
    Abstract: A memory device has a burst length “b”, performs “k” core accesses per command, and receives a command, where “b” is an integer of at least 2 and “k” is an integer of at least 2 and at most “b”. The memory device includes a memory cell array including a plurality of bank groups, a plurality of bank group control units respectively corresponding to the plurality of bank groups, each of the bank group control units configured to generate a multiplexer control signal for selecting part of data read from a corresponding bank group, and a multiplexer configured to sequentially output data read from the plurality of bank groups according to the multiplexer control signal output from the plurality of bank group control units. Data items included in output data of the multiplexer have a same time space.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: June 26, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae Young Oh, Ho Sung Song
  • Patent number: 9997216
    Abstract: A nonvolatile random access memory including a memory cell array including banks, each bank including rows; an address latch circuit; and a control circuit receiving a first set of signals including a precharge command and a first row address, and a second set of signals including an active command and a second row address. The control circuit executes a first operation in which one of the banks is deactivated when the first set of signals is loaded, executes a second operation in which the first row address is loaded when the first set of signals is loaded, and executes a third operation in which at least one of the rows in the bank is selected and activated based on the second row address when the second set of signals is loaded after the first set of signals.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: June 12, 2018
    Assignees: TOSHIBA MEMORY CORPORATION, SK HYNIX INC.
    Inventors: Yutaka Shirai, Naoki Shimizu, Kenji Tsuchida, Yoji Watanabe, Ji Hyae Bae, Yong Ho Kim
  • Patent number: 9995821
    Abstract: An apparatus includes an array of pixels, each pixel including in-cell pixel logic and a piezoelectric micromechanical ultrasonic transducer (PMUT) element, each in-cell pixel logic being communicatively coupled with at least one adjacent pixel in the array. Transceiver electronics may operate the array in a selectable one of a first mode and a second mode. In the first mode, the array may generate a substantially plane ultrasonic wave. In the second mode, the array may generate, from at least one superpixel region, a focused beam of relatively high acoustic pressure, each superpixel region including at least one inner pixel disposed in a central portion of the superpixel region and at least a first group of outer pixels disposed in an outer portion of the superpixel region. The transceiver electronics may be configured to operate the array by configuring at least one in-cell pixel logic.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: June 12, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Hao-Yen Tang, Yipeng Lu, Hrishikesh Vijaykumar Panchawagh
  • Patent number: 9990963
    Abstract: A word line voltage generator circuit, a semiconductor device, and an electronic device are provided. The word line voltage generator circuit includes a switch circuit connected to a high-level signal and a low-level signal and configured to output the high-level signal or the low-level signal as a word line voltage signal based on an input signal, and a drive signal control circuit configured to provide a drive signal connected to the switch circuit in response to the input signal. A voltage rising speed of the word line voltage signal is controlled by the drive signal.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: June 5, 2018
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Yijin Kwon, Hao Ni, Zijian Zhao, Yu Cheng
  • Patent number: 9984739
    Abstract: Apparatuses and methods for controlling word lines and sense amplifiers in a semiconductor device are described. An example apparatus includes: a sub word line selection signal decoder which activates at least one of a plurality of sub word selection signals responsive to row address signals; a column segment selection signal decoder which activates at least one of a plurality of column segment signals responsive to a portion of column address signals and a portion of the row address signals; a column segment selection circuit which activates at least one of a plurality of column-subword selection signals responsive to the activated column segment signal and the activated sub word selection signal; and a sub word line driver which activates at least one of a plurality of sub word lines responsive to an activated main word line and the activated sub word selection signal.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: May 29, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Kazuhiko Kajigaya
  • Patent number: 9984643
    Abstract: A data driver includes a first data voltage generator, a data converter and a second data voltage generator. The first data voltage generator is configured to generate a first data voltage based on first pixel data and configured to output the first data voltage to a first data line, the first pixel data being generated based on a first gamma curve. The data converter is configured to convert second pixel data to first converted pixel data, the second pixel data being generated based on the first gamma curve, the first converted pixel data being generated based on a second gamma curve different from the first gamma curve. The second data voltage generator is configured to generate a second data voltage based on the first converted pixel data and configured to output the second data voltage to a second data line.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: May 29, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Young-Il Ban, Sun-Koo Kang, Tae-Gon Kim
  • Patent number: 9978429
    Abstract: An address decoder circuit is designed to address and bias memory cells of a memory array of a non-volatile memory device. The address decoder circuit includes a charge-pump stage configured to generate a boosted negative voltage. A control stage is operatively coupled to the charge-pump stage for controlling switching on/off thereof as a function of a configuration signal that determines the value of the boosted negative voltage. A decoding stage is configured so as to decode address signals received at its input and generate biasing signals for addressing and biasing the memory cells. A negative voltage management module has a regulator stage, designed to receive the boosted negative voltage from the charge-pump stage and generate a regulated negative voltage for the decoding stage, having a lower ripple as compared to the boosted negative voltage generated by the charge-pump stage.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: May 22, 2018
    Assignee: STMicroelectronics S.r.l.
    Inventors: Fabio Enrico Carlo Disegni, Giuseppe Castagna, Maurizio Francesco Perroni
  • Patent number: 9959915
    Abstract: The present disclosure describes a system, a circuit, and method for process and temperature compensation in an integrated circuit. For example, the system includes a bus, a data latch, and a voltage generator. The data latch includes a plurality of transistors coupled to the bus. The voltage generator includes a tracking transistor with one or more physical characteristics that substantially match one or more respective physical characteristics—e.g., gate width and gate length dimensions—of at least one of the plurality of transistors in the data latch. The voltage generator is configured to adjust a pre-charged voltage on the bus based on an electrical characteristic of the tracking transistor.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: May 1, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Amul Desai, Hao Nguyen, Man Mui, Ohwon Kwon
  • Patent number: 9953688
    Abstract: A precharge control device includes a pulse generator, a bank address controller, and a precharge signal generator. The pulse generator generates a write precharge signal in response to a write burst end signal activated after a write burst operation and a read precharge signal in response to a read burst end signal activated after a read burst operation. The bank address controller generates a write address and a read address designating an address for the precharge operation in response to a write bank address and a read bank address. The precharge signal generator generates a precharge signal for performing the precharge operation in a bank selected in response to the write address when the write precharge signal is activated, or generates a precharge signal for performing the precharge operation in a bank selected in response to the read address when the read precharge signal is activated.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: April 24, 2018
    Assignee: SK hynix Inc.
    Inventors: Jin Yong Min, Dong Yoon Ka
  • Patent number: 9940988
    Abstract: A method of controlling a wordline by a driver decoder circuit includes generating a first control signal having a first logically high level and a first logically low level, and generating a second control signal having a second logically high level when the first control signal has the first logically high level and a second logically low level when the first control signal has the first logically low level. The first logically high level is different from the second logically high level, and the first logically low level is different from the second logically low level. The method includes coupling the wordline to a first node having a first voltage value in response to the first control signal having the first logically low level and decoupling the wordline from a second node having a second voltage value in response to the second control signal having the second logically low level.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: April 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Adrian Earle, Atul Katoch
  • Patent number: 9940990
    Abstract: The present disclosure includes data shift apparatuses and methods. An example apparatus includes a memory device. The example memory device includes an array of memory cells and sensing circuitry coupled to the array via a plurality of sense lines. A first shared input/output (I/O) line is configured to selectably couple a first subset of the plurality of sense lines and a second shared I/O line is configured to selectably couple a second subset of the plurality of sense lines. A shift element is configured to selectably couple the first shared I/O line to the second shared I/O line to enable a data shift operation. A controller is configured to direct selectable coupling of the array, the sensing circuitry, and the shift element to enable a shift of a data value from the first shared I/O line to the second shared I/O line.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: April 10, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Jeremiah J. Willcock
  • Patent number: 9934857
    Abstract: An example ternary content addressable memory. A bit cell of the memory may include a first memristor that has a first terminal that is connected to a first data line and a second terminal that is selectively connected to a second data line via a first switching transistor. The bit cell may also include a second memristor that has a first terminal that is connected to a third data line and a second terminal that is selectively connected to a fourth data line via a second switching transistor. The bit cell may also include a first match-line transistor and a second match-line transistor that are connected in series between a first rail and a match line, with a gate of the first match-line transistor being connected to the second terminal of the first memristor, and a gate of the second match-line transistor being connected to the second terminal of the second memristor.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: April 3, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Le Zheng, Brent Buchanan, John Paul Strachan
  • Patent number: 9929728
    Abstract: A CMOS device is formed in an FDSOI integrated circuit die. By retrieving the MOS functionality for gate voltage levels higher than its stress limits, second gate availability in these devices is being used, and hence removing the additional circuitry that would have been used for protecting the devices from such stress. Implementation in an inverter includes a PMOS transistor and an NMOS transistor. The PMOS and NMOS transistors each include a first gate coupled to the respective source terminal of the transistor. The PMOS and NMOS transistors each include a back gate coupled to the input of the inverter.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: March 27, 2018
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventor: Ankit Agrawal
  • Patent number: 9916261
    Abstract: An embodiment relates to a device for a memory access, the device having a first component for conducting operations on the memory and a second component for accessing the memory in a randomized manner, wherein the first component conducts at least a portion of the operations via the second component.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: March 13, 2018
    Assignee: Infineon Technologies AG
    Inventors: Berndt Gammel, Tomaz Felicijan, Stefan Mangard, Walter Mergler
  • Patent number: 9916896
    Abstract: The present disclosure relates to a pre-charge circuit including a first inverter which receives an early pre-charge signal and outputs an inverted early pre-charge signal, a first gate which receives a late pre-charge signal and a match line output signal and outputs an AND output signal, and a second gate which receives the inverted early pre-charge signal and the AND output signal and outputs an effective pre-charge signal.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: March 13, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Igor Arsovski, Robert M. Houle, Michael T. Fragano, Akhilesh Patil, Van D. Butler
  • Patent number: 9916875
    Abstract: A memory apparatus includes an array of bit cells arranged in rows and columns, multiple pairs of complementary bit lines, multiple power lines, and multiple voltage control circuits. Each column of the array is selectable by a corresponding pair of complementary bit lines. Each power line is coupled to the bit cells in a corresponding column. The voltage control circuits are coupled to respective columns of the array. Each voltage control circuit is configured to set a voltage level of a respective one of the power lines responsive to logic levels of the pair of complementary bit lines corresponding to the respective column.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: March 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9911475
    Abstract: A semiconductor device includes an information signal conversion circuit suitable for generating a flag signal from an external control signal in response to an information signal, and an implicit precharge signal generation circuit suitable for generating an implicit precharge signal for performing a precharge operation between successive active operations, in response to the flag signal.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: March 6, 2018
    Assignee: SK hynix Inc.
    Inventors: Ki Hun Kwon, Jae Il Kim
  • Patent number: 9905301
    Abstract: A nonvolatile memory device includes a memory cell, a bit line, a page buffer, and a control logic. The page buffer is connected to the memory cell through the bit line and the page buffer is configured to precharge the bit line to perform a desired operation. The desired operation may be one of a read operation and a verify operation. The control logic is configured to control bit line development time differently according to a temperature after precharging the bit line during the desired operation. The control logic is configured to determine the bit line development time according to a period of a reference clock signal that includes a different frequency depending on the temperature and/or a temperature compensation pulse signal including a pulse width that varies based on the temperature.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: February 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Pil Seon Yoo, Ji-Sang Lee, Gyosoo Choo
  • Patent number: 9892797
    Abstract: Apparatuses and methods for charging a global access line prior to accessing a memory are described. An example apparatus may include a memory array of a memory. A plurality of global access lines may be associated with the memory array. The global access line may be charged to a ready-access voltage before any access command has been received by the memory. The global access line may be maintained at the ready-access voltage during memory access operations until the receipt of a post-access command. The post-access command may reset the global access line to an inactive voltage.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: February 13, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 9886206
    Abstract: The present invention discloses a replica bit-line circuit, comprising a replica unit, the 1st inverter, the 2nd inverter, the 3rd inverter, the 4th inverter, the 5th inverter, the 6th inverter, the 7th inverter, the 8th inverter, the 9th inverter, the 1st NAND gate, the 2nd NAND gate, the 3rd NAND gate, the 1st NOR gate, the 2nd NOR gate and the 1st PMOS tube; the 2nd NOR gate is provided with the 1st input terminal, the 2nd input terminal, a set terminal and an output terminal; advantages of the present invention are stated as follows: It can inhibit feedback oscillation incurred by replica bit-line and replica wordline signal to obtain accurate wordline control signal; it can save switching power consumption of memory array by 53.7% under the power voltage of 1.2V.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: February 6, 2018
    Assignee: Ningbo University
    Inventors: Pengjun Wang, Keji Zhou, Huihong Zhang, Daohui Gong
  • Patent number: 9875774
    Abstract: A semiconductor device includes: a sense amplifier; a branched line selectively connectable to the sense amplifier; a recycling arrangement selectively connectable to the branched line; an array of bit lines connected to corresponding memory cells; a multiplexer configured to selectively connect the branched line to a selected one of the memory cells through a corresponding line amongst the array of bit lines; and a controller. The controller is configured to: permit, during a recovery phase in which a gleaned amount of charge (gleaned charge) is recovered, flow of charge (charge-flow) between the recycling arrangement and the branched line; interrupt, during a drainage phase in which the gleaned charge is preserved, charge-flow between the recycling arrangement and the branched line; and permit, during a reuse phase in which the gleaned charge is reused, charge-flow between the recycling arrangement and the branched line.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: January 23, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Chang Yu, Ta-Ching Yeh
  • Patent number: 9854531
    Abstract: An integrated circuit system includes a first integrated circuit for which signal modes set to a plurality of first I/O ports in the active mode are maintained in the sleep mode and a second integrated circuit for which a plurality of second I/O ports are placed in a floating state in the sleep mode, wherein the first integrated circuit transmits a first notification signal that indicates an operation mode to the second integrated circuit, wherein the second integrated circuit transmits a second notification signal that indicates an operation mode to the first integrated circuit, and wherein the signal modes of the plurality of first I/O ports and the plurality of second I/O ports are set such as to suppress steady currents persistently flowing between the first I/O ports and the second I/O ports, and to suppress through currents flowing.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: December 26, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Kentaro Kawakami
  • Patent number: 9842654
    Abstract: A nonvolatile memory includes a memory cell array, a row decoder circuit, and a page buffer circuit. The row decoder circuit applies a turn-on voltage to string selection lines, which are connected to string selection transistors of a selected memory block, at a first precharge operation in response to a write command received from an external device. The page buffer circuit applies, in response to the write command, a first voltage to bit lines, which are connected to the string selection transistors, through a first precharge circuit at the first precharge operation regardless of loaded data and applies the first voltage and a second voltage to the bit lines through a second precharge circuit at a second precharge operation based on the loaded data. During the first precharge operation, write data is loaded onto the page buffer circuit.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: December 12, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Sang Lee, Donghun Kwak, Daeseok Byeon, Chiweon Yoon
  • Patent number: 9830959
    Abstract: A semiconductor memory apparatus may include a memory cell circuit, a data latch circuit, and a first stage amplification circuit. The data latch circuit may be electrically coupled to the memory cell circuit by a bit line. The data latch circuit may latch data transferred through the bit line. The data latch circuit may output latched data to an input/output line in response to a cell select signal. The data first stage amplification circuit may generate driving data to a voltage level of an external power supply voltage in response to a voltage level of the input/output line. The data first stage amplification circuit may precharge the input/output line to a voltage level lower than the external power supply voltage and higher than a ground voltage in response to a precharge signal.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: November 28, 2017
    Assignee: SK hynix Inc.
    Inventors: Kang Woo Park, Eun Ji Choi
  • Patent number: 9818490
    Abstract: A semiconductor device includes a word line coupled to a mask ROM memory cell, a bit line pair coupled to the memory cell, a differential sense amplifier for amplifying the potential difference of the bit line pair, and a logic circuit for detecting whether the logic states of the bit line pair match or not. In this way, when there is a failure in the memory cell, it is possible to prevent the semiconductor device from passing the test as a result of the determination that the actual value is the same as the expected value in the test even if there is no potential difference in the bit line pair.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: November 14, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshiki Tsujihashi
  • Patent number: 9812181
    Abstract: A memory circuit includes a memory cell, a data line configured to be coupled with the memory cell, a node, a precharge circuit, a first transistor of a first type, and a second transistor of the first type. The precharge circuit is configured to charge the node toward a predetermined voltage level. The first transistor of the first type has a drain coupled with the node and a source coupled with the data line, and the first transistor has a first threshold voltage. The second transistor of the first type has a drain coupled with the node and a source coupled with the data line, and the second transistor having a second threshold voltage different from the first threshold voltage.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: November 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chou-Ying Yang, Yi-Cheng Huang, Shang-Hsuan Liu