SEMICONDUCTOR DEVICE HAVING A P-MOS TRANSISTOR WITH SOURCE-DRAIN EXTENSION COUNTER-DOPING
A method for forming a semiconductor device is provided. The method includes forming a n-type well region. The method further includes forming a gate corresponding to the semiconductor device on top of the n-type well region. The method further includes forming a source-drain extension region on each side of the gate in the n-type well region using a p-type dopant. The method further includes doping the source-drain extension region on each side of the gate in the n-type well region using a n-type dopant such that the n-type dopant is substantially encompassed within the source-drain extension region. The method further includes forming a source and a drain corresponding to the semiconductor device.
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The present invention relates generally to semiconductor devices, and more particularly to a semiconductor device with source-drain extension counter-doping.
RELATED ARTIncreasingly lower-power semiconductor devices are needed to reduce power requirements of integrated circuits, such as memories. Memory devices, such as SRAMS, are typically implemented using bitcells, whose performance is a function of many parameters including semiconductor techniques used to implement the bitcells. SRAM bitcell functionality and performance, among other things, depends on the write margin of the bitcell. Higher write margin enables one to change the status of a bitcell using a lower voltage. Lower voltage correspondingly results in lower power consumption by the bitcell and thus the memory using the bitcell. However, conventional memory devices require higher voltage to perform a status change of the bitcell resulting in higher power consumption.
Thus, there is a need for an improved semiconductor device that results in a higher write margin for bitcells for memory devices, such as SRAMs.
BRIEF DESCRIPTION OF THE DRAWINGSThe present invention is illustrated by way of example and not limited by the accompanying figures, in which like references indicate similar elements, and in which:
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.
DETAILED DESCRIPTION OF THE EMBODIMENTSIn one aspect, a method for forming a semiconductor device is provided. The method includes forming a n-type well region. The method further includes forming a gate corresponding to the semiconductor device on top of the n-type well region. The method further includes forming a source-drain extension region on each side of the gate in the n-type well region using a p-type dopant. The method further includes doping the source-drain extension region on each side of the gate in the n-type well region using a n-type dopant such that the n-type dopant is substantially encompassed within the source-drain extension region. The method further includes forming a source and a drain corresponding to the semiconductor device.
In another aspect, a semiconductor device including a n-type well region and a gate corresponding to the semiconductor device on top of the n-type well region is provided. The semiconductor device may further include a source-drain extension region on each side of the gate in the n-type well region formed using a p-type dopant, where the source-drain extension region on each side of the gate in the n-type well region is further doped using a n-type dopant such that the n-type dopant is substantially encompassed within the source-drain extension region. The semiconductor device may further include a source and a drain corresponding to the semiconductor device.
In yet another aspect, a semiconductor device including a p-type well region and a gate corresponding to the semiconductor device on top of the p-type well region is provided. The semiconductor device may further include a source-drain extension region on each side of the gate in the p-type well region formed using a n-type dopant, where the source-drain extension region on each side of the gate in the p-type well region is further doped using a p-type dopant such that the p-type dopant is substantially encompassed within the source-drain extension region. The semiconductor device may further include a source and a drain corresponding to the semiconductor device.
In one embodiment, only certain selected semiconductor devices in an integrated circuit may be subjected to this processing step. Thus, for example, non-selected semiconductor devices may not be doped using the n-type dopant as part of this processing step. In one embodiment, the selected semiconductor devices may relate to a SRAM formed as part of a microprocessor. By selectively doping the pMOS load devices that are part of the SRAM, the write margin for the SRAM may be improved without affecting other pMOS devices comprising the microprocessor. In particular, the minimum voltage required to change a state of the SRAM may be lowered. The minimum voltage may be lowered because of lowering of the on-state current of the pMOS device. This process step, however, has minimum effect on other pMOS device parameters, such as threshold voltage, off-state leakage current, and overlap capacitance. Thus, this allows a SRAM employing this pMOS device to perform other operations, such as read operation normally.
In one embodiment, the n-type dopant used as part of this step may be arsenic. Alternatively, phosphorus, antimony, or similar suitable dopants may be used. By way of example, the implantation energy of the n-type dopant may be in a range between 1 to 6 keV. By way of example, the dosage of the n-type dopant may be in a range between 5e13 atoms per square centimeter to 1e14 atoms per square centimeter.
Although the above process and the semiconductor device is described using exemplary counter-doping of a pMOS device, a nMOS device may also be counter-doped using a similar process. The counter-doping may result in a lowering of the on-state current of the nMOS device. The source-drain extension region of the nMOS device may be counter-doped using a p-type dopant, such as boron, BF2, indium, gallium, and other suitable dopants. By way of example, the implantation energy of the p-type dopant may be in a range between 1 to 6 keV. By way of example, the dosage of the p-type dopant may be in a range between 5e13 atoms per square centimeter to 1e14 atoms per square centimeter. The weaker nMOS device may improve the write margin of a SRAM that employs the weaker nMOS device as a load device.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Claims
1.-18. (canceled)
19. A method of making a semiconductor device comprising:
- forming a n-type well region;
- forming a gate corresponding to the semiconductor device on top of the n-type well region;
- forming a source-drain extension region on each side of the gate in the n-type well region using a p-type dopant;
- selectively doping the source-drain extension region on each side of the gate in the n-type well region using a n-type dopant such that the n-type dopant is substantially encompassed within the source-drain extension region, wherein the step of selectively doping comprises doping only p-type devices corresponding to a memory; and
- forming a source and a drain corresponding to the semiconductor device.
20. The method of claim 19, wherein the n-type dopant is arsenic.
21. The method of claim 19, wherein an implantation energy of the n-type dopant is in a range between 1 to 6 keV.
22. The method of claim 19, wherein a dopant dosage of the n-type dopant is in a range between 5e13 atoms per square centimeter to 1e14 atoms per square centimeter.
23. The method of claim 19, wherein the n-type dopant is at least one of phosphorous and antimony.
24. The method of claim 19, wherein doping the source-drain extension region on each side of the gate in the n-type well region using the n-type dopant step is performed using a mask used to form the source-drain extension region on each side of the gate in the n-type well region using the p-type dopant.
25. A method of making a semiconductor device comprising:
- forming a n-type well region;
- forming a gate corresponding to the semiconductor device on top of the n-type well region;
- forming a source-drain extension region on each side of the gate in the n-type well region using a p-type dopant;
- selectively doping the source-drain extension region on each side of the gate in the n-type well region using a n-type dopant such that the n-type dopant is substantially encompassed within the source-drain extension region, wherein the step of selectively doping comprises doping only p-type devices corresponding to a memory and wherein selectively doping the source-drain extension region on each side of the gate in the n-type well region using the n-type dopant step is performed using a mask used to form the source-drain extension region on each side of the gate in the n-type well region using the p-type dopant; and
- forming a source and a drain corresponding to the semiconductor device.
26. The method of claim 25, wherein the n-type dopant is arsenic.
27. The method of claim 25, wherein an implantation energy of the n-type dopant is in a range between 1 to 6 keV.
28. The method of claim 25, wherein a dopant dosage of the n-type dopant is in a range between 5e13 atoms per square centimeter to 1e14 atoms per square centimeter.
29. The method of claim 25, wherein the n-type dopant is at least one of phosphorous and antimony.
30. A method of making a semiconductor device comprising:
- forming a n-type well region;
- forming a gate corresponding to the semiconductor device on top of the n-type well region;
- forming a source-drain extension region on each side of the gate in the n-type well region using a p-type dopant;
- selectively doping the source-drain extension region on each side of the gate in the n-type well region using a n-type dopant such that the n-type dopant is substantially encompassed within the source-drain extension region, wherein the step of selectively doping comprises doping only p-type devices corresponding to a memory and wherein selectively doping the source-drain extension region on each side of the gate in the n-type well region using the n-type dopant step is performed using a mask used to form the source-drain extension region on each side of the gate in the n-type well region using the p-type dopant and wherein an implantation energy of the n-type dopant is in a range between 1 to 6 keV; and
- forming a source and a drain corresponding to the semiconductor device.
31. The method of claim 30, wherein the n-type dopant is arsenic.
32. The method of claim 30, wherein a dopant dosage of the n-type dopant is in a range between 5e13 atoms per square centimeter to 1e14 atoms per square centimeter.
33. The method of claim 30, wherein the n-type dopant is at least one of phosphorous and antimony.
Type: Application
Filed: Dec 7, 2007
Publication Date: Apr 17, 2008
Applicant: Freescale Semiconductor, Inc. (Austin, TX)
Inventors: Sinan Goktepeli (Austin, TX), James Burnett (Austin, TX)
Application Number: 11/952,750
International Classification: H01L 21/8236 (20060101);