PRINTED CIRCUIT BOARD INCLUDING EMBEDDED CHIPS AND METHOD OF FABRICATING THE SAME
A printed circuit board having embedded chips, composed of a central layer having an embedded chip, an insulating layer formed on one surface or both surfaces of the central layer and having a via hole filled with conductive ink, and a circuit layer formed on the insulating layer and having a via hole and a circuit pattern electrically connected to the chip of the central layer through the via hole of the insulating layer. In addition, a method of fabricating a printed circuit board including embedded chips is provided.
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The present application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 2004-116805 filed on Dec. 30, 2004. The content of the application is incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates, generally, to a printed circuit board (PCB) including embedded chips, and a fabricating method thereof. More particularly, the present invention relates to a PCB including embedded chips, which comprises a central layer having an embedded chip, an insulating layer formed on one surface or both surfaces of the central layer and having a through hole filled with conductive ink, and a circuit layer formed on the insulating layer and having a via hole and a circuit pattern electrically connected to the chip of the central layer through the through hole of the insulating layer, and a method of fabricating such a PCB. The method of fabricating the PCB according to the present invention includes forming a circuit layer having a predetermined circuit pattern, vertically forming a via hole through a base substrate having a cured resin layer and a non-cured resin layer, filling the via hole with conductive ink, instead of a plating process, superimposing a passive component or an active component on the base substrate, and heating and compressing the circuit layers and the insulating layers on the base substrate at one time, to manufacture a multi-layered PCB.
2. Description of the Related Art
With the great improvement of electronic industries, to correspond to electronic products requiring miniaturization and high functionality, electronic technologies have been developed to insert resistors, capacitors, ICs (integrated circuits), etc., into substrates.
Although discrete chip resistors or discrete chip capacitors have long since been mounted on PCBs, PCBs including embedded chips, such as resistors or capacitors, have only recently been developed.
In techniques of manufacturing PCBs including embedded chips, the chips, such as resistors or capacitors, are inserted into an outer layer or an inner layer of the substrate using novel materials and processes, to substitute for conventional chip resistors and chip capacitors.
That is, the PCB including embedded chips means that the chips, for example, capacitors, are embedded in the inner layer of the substrate itself or outer layer thereof. Regardless of the size of the substrate itself, if the chip is incorporated into the PCB, this is called an ‘embedded chip’. Such a substrate is referred to as an ‘embedded chip PCB’.
The major characteristic of the embedded chip PCB is that the chip is intrinsically provided in the PCB without the need to mount the chip on the substrate.
In general, fabrication techniques of the embedded chip PCB are largely classified into three types.
First, a method of manufacturing a polymer thick film type capacitor is provided, including applying a polymer capacitor paste, which is then heat cured, that is, dried. Specifically, this method includes applying a polymer capacitor paste onto an inner layer of a PCB, and drying the polymer capacitor paste, on which a copper paste is then printed and dried, to form electrodes, thereby obtaining an embedded capacitor.
Second, a method of manufacturing an embedded discrete type capacitor is provided, including coating a PCB with a ceramic filled photosensitive resin, which has been patented by Motorola Co. Ltd., USA (U.S. Pat. No. 6,606,793). The above method includes applying the photosensitive resin containing ceramic powder on the substrate, laminating a copper foil layer on the resin layer to form upper electrodes and lower electrodes, forming a circuit pattern, and then etching the photosensitive resin, thereby obtaining a discrete capacitor.
Third, a method of manufacturing an embedded capacitor is provided, including separately inserting a dielectric layer having capacitance properties into an inner layer of a PCB, so as to substitute for a decoupling capacitor mounted on a PCB, which has been patented by Zycon Corp. Ltd., USA (U.S. Pat. No. 5,079,069). In this method, the dielectric layer having power electrodes and ground electrodes is inserted into the inner layer of the PCB, thereby obtaining a power distributed decoupling capacitor.
To fulfill various functions and superb performance of electronic products, higher speed electronic components are increasingly required. Also, with the aim of increasing the speed of the component, a package bonding manner is changed from typical bonding manners, such as lead frame, wire bonding, pin type bonding, etc., into a small ball type bonding manner or a flip-chip bonding manner.
In the case of a high speed product that adopts a flip-chip bonding manner or in the case of a central processing unit (CPU) or a graphic chip set, a clock is operated at a speed of 2 GHz or more.
Such a CPU or chip set requires a short signal rising time and a high current, and is designed to further decrease intervals between signal lines of an IC, flip chip package and a main board for operation at high speeds.
However, as the speed of the component increases, voltage fluctuation of a power line occurs, resulting in the generation of a lot of high frequency noise, such as SSN (Simultaneous Switching Noise) or delta-I (ΔI).
The high frequency noise (e.g., SSN) causes system delay or a logic fault, thereby decreasing the performance and reliability of the system.
Therefore, the SSN may be effectively reduced by lowering the inductance of the power line when the current and the switching speed required for the operation of devices are unchangeable. In addition, the decoupling capacitor is used to reduce the voltage fluctuation of the power line.
The decoupling chip capacitor is mounted to the power line, whereby a current required for switching the circuit can be directly fed. Thus, the inductance of the power line is shielded, and hence, a voltage drop phenomenon is remarkably lowered and the SSN may be reduced, too.
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In such cases, the first and second conventional techniques are disadvantageous because the space between the electrical component and the insulating layer as the central layer is large, and thus, the resultant product has a large size.
Further, the first and second conventional techniques are disadvantageous because the space between the chip and the copper foil layer is large, and thus, efficient radiating effects cannot be obtained.
Furthermore, the second conventional technique is disadvantageous because a build-up process used for lamination takes a long time.
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Then, a hollow portion is formed through a film 8 and then the film 8 is further processed to have a predetermined circuit pattern 3 and through holes filled with conductive ink 9, to obtain a central layer. As such, the film 8 is provided in the number of layers corresponding to the thickness of an electrical component 5 to be inserted into the hollow portion thereof.
Finally, an upper circuit layer is formed by processing a film 8 to have a predetermined circuit pattern 3 and through holes filled with conductive ink 9, and then the upper and lower circuit layers are laminated on the central layer having an inserted electrical component 5 at one time.
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However, the third conventional technique is disadvantageous in that because the through holes filled with conductive ink adhere to the chip upon simultaneous lamination, the alignment of the layers cannot be accurately controlled.
Moreover, since the radiation takes place using the radiating pattern, limitations are imposed on fabricating a high density circuit due to the formation of a passage required for emission of the radiating pattern.
SUMMARY OF THE INVENTIONAccordingly, the present invention has been made keeping in mind the above problems occurring in the related art, and an object of the present invention is to provide a multi-layered PCB including embedded chips, and a method of fabricating the same, in which interlayer electrical connection is realized while constitutive layers of the PCB having chips such as active and passive components are simultaneously laminated, thereby drastically decreasing the number of processes.
Another object of the present invention is to provide a multi-layered PCB including embedded chips and a method of fabricating the same, in which the positions of the chips embedded in the PCB are fixed, and thus, are not moved even upon compression, whereby a highly reliable PCB can be obtained.
In order to accomplish the above objects, the present invention provides a method of fabricating a printed circuit board including embedded chips, including the steps of preparing a circuit layer having a circuit pattern on one surface or both surfaces thereof; forming an insulating layer having a via hole filled with conductive ink; preparing a copper clad laminate having a hollow portion into which a chip is to be inserted; preparing a material layer including an insulating layer and a copper foil layer; pre-laminating the circuit layer, the insulating layer, the chip, the copper clad laminate, and the material layer on the insulating layer; and compressing the pre-laminated layers, whereby the chip is connected to the circuit pattern of the circuit layer and the copper foil layer of the material layer through the via hole.
In accordance with an embodiment of the present invention, a method of fabricating a printed circuit board including embedded chips is provided, which includes the steps of forming a circuit layer having a circuit pattern on one surface or both surfaces thereof; forming an insulating layer having a via hole filled with conductive ink; preparing a material layer having a non-cured resin layer and a copper foil layer; pre-laminating a chip on a portion filled with the conductive ink; pre-laminating the circuit layer and the material layer on the insulating layer; and compressing the pre-laminated layers, whereby the chip is connected to the circuit pattern of the circuit layer through the via hole, and the chip is inserted into the non-cured resin layer of the material layer.
In accordance with another embodiment of the present invention, a method of fabricating a printed circuit board including embedded chips is provided, which includes the steps of forming a central layer having an embedded chip; forming an insulating layer having a via hole filled with conductive ink; forming a circuit layer having a via hole and a circuit pattern; pre-laminating the central layer, the insulating layer, and the circuit layer; and compressing the pre-laminated layers, whereby the chip of the central layer is connected to the circuit pattern of the circuit layer through the via hole.
Further, the present invention provides a printed circuit board including embedded chips, which includes a central layer having an embedded chip; an insulating layer formed on one surface or both surfaces of the central layer and having a through hole filled with conductive ink; and a circuit layer formed on the insulating layer and having a via hole and a circuit pattern electrically connected to the chip of the central layer through the through hole of the insulating layer.
BRIEF DESCRIPTION OF THE DRAWINGSThe above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
Hereinafter, embodiments of the present invention are described, with reference to the appended drawings.
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In this case, the CCL having the insulating resin layer 101 and the copper foil layers 102a and 102b formed on both surfaces thereof is exemplified by glass/epoxy CCLs, heat resistant resin CCLs, paper/phenol CCLs, high frequency CCLs, flexible CCLs, complex CCLs, etc., depending on its uses.
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Preferably, the hollow portion B is formed by a mechanical drilling process or a punching process. Also, it is possible to use a laser drilling process. In this case, the hollow portion B of the copper foil layer 205 is formed by an etching process, and the hollow portion B of the insulating layer 206 is formed by a laser-irradiation process.
Thereafter, the central layer, the circuit layers, and the insulating layers are simultaneously laminated, as described below.
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The central layer 207 including the hollow portions B shown in
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Alternatively, before the single-sided CCL 209 is laminated, the circuit pattern is previously formed on the copper foil layer 215 of the CCL 209, and also, the circuit layer 104 having circuit patterns on both surfaces thereof is used, instead of using the circuit layer 104 having the circuit pattern on either surface thereof, so that the process of separately forming the circuit patterns on the outer layers may be omitted.
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The insulating layer 204 obtained by the process shown in
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Subsequently, the insulating layers and the circuit layers are laminated on both surfaces of the central layer 308, in accordance with a simultaneous laminating process shown in
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Via holes of the insulating layer 313a are formed at positions which are connected to pads 311 and 312 of the active component 309 and the passive component 310, respectively, and are filled with conductive ink. After a compression process, the active component 309 and the passive component 310 are electrically connected to the circuit pattern 315a of the circuit layer 314a by the conductive ink.
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Alternatively, circuit patterns may be formed on one surface of each of the circuit layers 314a and 314b, after which the laminating process is completed, and then, circuit patterns may be further formed on outer copper foil layers 316a and 316b.
In the present embodiment, since the active component 309 and the passive component 310 are already inserted into the hollow portions C of the central layer 308 upon compression, displacement of the active component 309 and the passive component 310 from original positions due to the compression may be prevented. That is, the upper protrusions of the conductive ink of the insulating layers 313a and 313b can be accurately connected to the electrode pads 311 and 312 of the active and passive components 309 and 310, respectively, while the lower protrusions of the conductive ink thereof can be accurately connected to the circuit patterns 315a and 315b.
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As described above, the present invention provides a PCB including embedded chips and a fabrication method thereof. The method of fabricating the multi-layered PCB of the present invention is advantageous because interlayer electrical connection is realized while laminating the layers upon simultaneous lamination of the multi-layered PCB including embedded chips of active components and passive components, thereby drastically reducing the number of processes.
Further, the method of fabricating the multi-layered PCB of the present invention is advantageous because the positions of the chips embedded in the multi-layered PCB are fixed so as not to be moved even upon compression, and thus, it is possible to fabricate a highly reliable PCB.
Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.
Claims
1-13. (canceled)
14. A printed circuit board having embedded chips, comprising the steps of:
- a central layer having an embedded chip;
- an insulating layer formed on at least one of an upper and a lower surface of the central layer and having a via hole filled with conductive ink; and
- a circuit layer formed on the insulating layer having a via hole and a circuit pattern electrically connected to the embedded chip of the central layer through the via hole.
15. The printed circuit board as set forth in claim 14, wherein the insulating layer comprises a cured resin layer and a non-cured resin layer.
16. The printed circuit board as set forth in claim 14, wherein the chip comprises at least one of a passive component and an active component.
Type: Application
Filed: Oct 31, 2007
Publication Date: May 8, 2008
Applicant: Samsung Electro-Mechanism Co., Ltd. (Suwon-si)
Inventors: Chang Ryu (Daejeon), Doo Lee (Chungcheongbuk-do), Jin Ahn (Daejeon), Myung Kang (Daejeon), Suk Cho (Daejeon)
Application Number: 11/931,771
International Classification: H05K 7/00 (20060101);