Method of manufacturing semiconductor device

There is provided a dry etching method for forming wiring trenches in a first insulating layer and in a second insulating layer provided thereon. First, the second insulating layer is etched partway under first etching conditions using resist as a mask (first etching step). Next, the remnant of the second insulating layer and the first insulating layer are etched under second etching conditions different from the first etching conditions, without changing the etching conditions (second etching step).

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Description
BACKGROUND OF THE INVENTION

The present invention relates to a method of manufacturing a semiconductor device.

A dual damascene method that is a low-cost process of manufacture is used mainly when forming Cu wires on a device. The etch depth for wiring trench (film thickness of etching) directly relates to the cross-sectional area of Cu wires buried in subsequent processes and affects wiring resistance and/or capacitance. Accordingly, the etch uniformity and process stability of wiring trenches are especially important in a dual damascene method.

Japanese Patent Laid-Open No. 2003-332421 discloses a wire processing method using an etch stop layer. The problem of etch un-uniformity is solved by the use of an etch stop layer. However, this solution increases manufacturing costs since a process of forming the etch stop layer is added.

Japanese Patents Laid-Open Nos. 10-229122 and 2005-353698 disclose methods of etching insulating layers without using etch stop layers. In such methods of processing insulating layers as mentioned above, there arises a problem of etch un-uniformity originated from the instability of etching apparatus or from fluctuations in the ambient atmosphere within a chamber.

Japanese Patent Laid-Open No. 2004-71731 discloses an etching method not requiring the use of etch stop layers in a dual damascene method. In this method, a so-called low-k dielectric layer having relative permittivity lower than that of SiO2 and an SiO2 layer covering the dielectric layer (cap layer) are respectively etched under different conditions to form wiring trenches. Specifically, the SiO2 layer is etched under the condition with a higher selection ratio for the low-k dielectric layer, and then the low-k dielectric layer is etched under the condition with a lower selection ratio for the low-k dielectric layer.

However, the method disclosed in Japanese Patent Laid-Open No. 2004-71731 has not been able to solve the problem of etch un-uniformity. The inventor of the present application has newly discovered that the cause of this is that the thickness of a deposition layer formed in the bottom of each trench significantly varies within a wafer during the etching of a second insulating layer, if the etching of the second insulating layer is stopped at a point where a first insulating layer is exposed when successively etching a laminated layer composed of the first insulating layer and the second insulating layer formed thereon. This irregularity of thickness degrades the uniformity of processing shape resulting from the processing of the first insulating layer.

SUMMARY

A method of manufacturing a semiconductor device having a first insulating layer and a second insulating layer provided thereon in accordance with the present invention includes:

a first etching step of etching the second insulating layer partway under first etching conditions; and

a second etching step of etching the remnant of the second insulating layer left over in the first etching step and the first insulating layer under second etching conditions different from the first etching conditions.

In the manufacturing method described above, the etching of the second insulating layer is temporarily stopped partway, and then the remnant of the second insulating layer and the first insulating layer are etched collectively. By prohibiting the first insulating layer from being exposed immediately after the completion of the first etching step, as described above, it is possible to prevent a deposition layer having irregular thickness from being deposited. Accordingly, the uniformity of processing shape resulting from the processing of the first insulating layer improves.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a process drawing illustrating one embodiment of a method of manufacturing a semiconductor device in accordance with the present invention;

FIG. 2 is another process drawing illustrating one embodiment of a method of manufacturing the semiconductor device in accordance with the present invention;

FIGS. 3A and 3B are graphs intended to explain the advantages of the embodiments;

FIGS. 4A and 4B are graphs intended to explain the advantages of the embodiments;

FIGS. 5A and 5B are graphs intended to explain the advantages of the embodiments;

FIGS. 6A and 6B are graphs intended to explain the advantages of the embodiments;

FIGS. 7A and 7B are graphs intended to explain the advantages of the embodiments;

FIGS. 8A and 8B are graphs intended to explain the advantages of the embodiments;

FIGS. 9A and 9B are graphs intended to explain the advantages of the embodiments;

FIGS. 10A and 10B are graphs intended to explain the advantages of the embodiment;

FIGS. 11A and 11B are graphs intended to explain the advantages of the embodiments;

FIGS. 12A and 12B are graphs intended to explain the advantages of the embodiments;

FIGS. 13A and 13B are wafer map to explain the advantages of the embodiments;

FIGS. 14A and 14B are wafer map to explain the advantages of the embodiments;

FIG. 15 is a cross-sectional view intended to explain problems with a related art;

FIGS. 16A and 16B are cross-sectional views intended to explain problems with a related art;

FIGS. 17A and 17B are cross-sectional views intended to explain problems with a related art; and

FIGS. 18A and 18B are cross-sectional views intended to explain problems with a related art.

 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, the preferred embodiments of a method of manufacturing a semiconductor device in accordance with the present invention will be described while referring to the accompanying drawings. Note that in the description of the drawings, same components are denoted by same reference numerals and will not be explained again.

FIGS. 1 and 2 are process drawings illustrating one embodiment of a method of manufacturing a semiconductor device in accordance with the present invention. This manufacturing method is intended to manufacture a semiconductor device having a low-k dielectric layer 10 (first insulating layer) and a cap layer 20 (second insulating layer) provided thereon. No etch stop layer is interposed between the low-k dielectric layer 10 and the cap layer 20.

The relative permittivity of the low-k dielectric layer 10 is preferably no greater than 3.5. As materials for composing the low-k dielectric layer 10, polyorganosiloxane, aromatic-containing organic material, hydrogen silsesquioxane (HSQ), spin-on glass (SOG) or flowable oxide (FOX: registered trademark), for example, may be used. As examples of polyorganosiloxane, there may be mentioned SiOC, methylsilsesquioxane (MSQ), methylated hydrogen silsesquioxane (MHSQ), and the like. Low-k dielectric layers made of SiOC includes for example, Black Diamond (registered trademark, hereinafter referred to as “BD”) made by Applied Materials, Coral made by Novellus Systems Inc., and Aurola made by ASM International.

In addition, as examples of aromatic-containing organic material, there may be mentioned polyphenylene, polyarylether (PAE), divinylsiloxane-bis-benzocyclobutene, and the like. Low-k dielectric layers made of polyphenylene include, for example, SiLK (registered trademark) made by Dow Chemical Company. Furthermore, low-k dielectric layers made of polyarylether include, for example, Flare made by Honeywell Electric Materials. Note that the low-k dielectric layer 10 may be in a porous state.

As materials for composing the cap layer 20, there may be mentioned SiO2, SiC, SiCN, SiN, benzocyclobutene (BCB), and the like.

First, the cap layer 20 is etched (first etching step) under the first etching conditions using resist 30 as a mask (FIG. 1) without exposing the low-k dielectric layer 10. The first etching conditions are preferably such conditions as are suited to the processing of the cap layer 20, i.e., conditions whereby the cap layer 20 can be processed with excellent etch uniformity. In addition, the etching time in the first etching step is preferably no shorter than 60% but no longer than 90% of the etching time (end point) required to etch the cap layer 20 to the last. The etching time required to etch the cap layer 20 to the last can be determined using, for example, an end point detector (EPD) system. This etching time corresponds to a period of time for which etching is carried out so that “t1” is no shorter than 10% but no longer than 40% of t2 when etching the “t2”-thick cap layer 20 as a remnant 22 to a thickness of “t1” in the first etching step.

Next, the remnant 22 of the cap layer 20 and the low-k dielectric layer 10 are etched using the second etching conditions different from the first etching conditions, without changing the etching conditions (second etching step) (FIG. 2). In the present embodiment, the first and second etching steps are carried out using an etching apparatus provided with upper and lower electrodes having mutually different high-frequency outputs. In addition, these etching steps are carried out as part of, for example, a dual damascene process. Note that the second etching step may be started either immediately or a predetermined length of time (stabilization time) later after the completion of the first etching step. The stabilization time is, for example, approximately 3 seconds.

The second etching conditions are preferably such conditions as to virtually prohibit any selection ratio from being applied between the low-k dielectric layer 10 and the cap layer 20. In addition, the flow rate of oxygen is preferably higher under the second etching conditions than under the first etching conditions. The mixing ratio of oxygen in the second etching conditions is preferably no lower than 0.4% but no higher than 2.6%. Furthermore, the high-frequency output (hereinafter referred to as the “top power”) of the upper electrode is preferably higher under the second etching conditions than under the first etching conditions. The top power under the second etching conditions is preferably no lower than 1300 W but no higher than 2200 W.

A preferred example of the first etching conditions is as follows:.

  • A gas consisting primarily of CH4-nFn (“n” is a natural number equal to or smaller than 4) is used with a pressure being no lower than 30 mTorr but no higher than 60 mTorr, the top power being no lower than 200 W but no higher than 600 W, the bias output being no lower than 700 W but no higher than 1300 W, and the flow rate of argon (Ar) being no lower than 0.91/min (900 sccm) but no higher than 1.81/min (1800 sccm).

On the other hand, a preferred example of the second etching conditions is as follows:

  • A gas consisting primarily of CH4-nFn (“n” is a natural number equal to or smaller than 4) is used with a pressure being, no lower than 30 mTorr but no higher than 60 mTorr, the top power being no lower than 1300 W but no higher than 2200 W, the bias output being no lower than 600 W but no higher than 1200 W, and the flow rate of argon (Ar) being no lower than 0.21/min (200 sccm) but no higher than 0.61/min (600 sccm).

Note that in some cases, the gas flow rate may be higher (for example, 9:1 in terms of a partial pressure ratio) in the vicinity of the central part of a wafer than in the vicinity of the edge part thereof. In that case, gas flow rates exemplified in the present specification refer to those in the vicinity of the central part of a wafer.

Now, the advantages of the present embodiment will be described. In the present embodiment, the etching of the cap layer 20 is temporarily stopped halfway, and then the remnant 22 of the cap layer 20 and the low-k dielectric layer 10 are etched under different etching conditions. By prohibiting the low-k dielectric layer 10 from being exposed immediately after the completion of the first etching step, as described above, it is possible to prevent a deposition layer having irregular thickness from being deposited. Accordingly, the uniformity of processing shape resulting from the processing of the low-k dielectric layer 10 improves.

In contrast, according to the method disclosed in Tokukai 2004-71731, the uniformity of processing shape resulting from the processing of the first insulating layer degrades, as described above. Now, a specific example of this problem will be described. In general, etching proceeds according to competitive reaction between depositions accumulating on a wafer and ions plunging into the wafer. At this time, the speed at which the depositions accumulate and the uniformity of the depositions differ depending on the type thereof. In addition, there is a difference in etching characteristics between an SiO2 layer and a low-k dielectric layer. For example, the SiO2 layer has difficulties in facilitating etching in the absence of a physical sputtering element, while the low-k dielectric layer containing carbon and hydrogen is easy to be etched by not a physical etching but a chemical etching.

Accordingly, as shown in FIG. 15, excellent uniformity is maintained within the wafer in terms of the amount of depositions during the etching of the SiO2 layer 106, since a balance is reached between depositions P1 accumulating in a trench and ions P2 plunging into the trench. However, the balance of depositions accumulating on the low-k dielectric layer 1104 disrupts due to a difference in deposition constituents produced from the low-k dielectric layer 104, such as carbon and hydrogen, and due to a difference in the probability of adherence of the depositions to the low-k dielectric layer 104, as soon as the low-k dielectric layer 104 is exposed. FIGS. 16A and 16B respectively show conditions in the vicinity of the central and edge parts of the wafer at this point. In these figures, a via stop layer 102, the low-k dielectric layer 104, the cap layer 106 and resist 108 are stacked sequentially in this order on an interlayer insulating layer 100. In the interlayer insulating layer 100, there are formed elements, such as transistors, and wires (both are not shown in the figure).

Consequently, as shown in FIGS. 17A and 17B, a deposition layer 110a near the central part of the wafer is thicker than a deposition layer 110b near the edge part of the wafer. As a result, as shown in FIGS. 18A and 18B, an etch depth “d1” near the central part of the wafer is smaller than an etch depth d2 near the edge part of the wafer when etching the low-k dielectric layer 104. In this way, the uniformity of etch depth and the like within the wafer becomes impaired due to a difference in the thickness of deposition layers. In contrast, according to the present embodiment, a high degree of uniformity of etch depth can be obtained within wafer.

In addition, if a deposition layer accumulates on the low-k dielectric layer 10, the throughput decreases and the manufacture efficiency is lowered since an extra amount of time is consumed in order to remove the deposition layer. According to the present embodiment, it is possible to also avoid these problems.

Incidentally, when forming the cap layer 20 on the low-k dielectric layer 10, there may be a case that a transmuted layer is produced between these layers. This transmuted layer is, for example, a layer composed of an SiON-like material. A possible cause for the transmuted layer being formed is that a raw material gas for the cap layer 20 triggers unwanted reactions when the cap layer 20 is formed using a CVD method. Unfortunately, the presence of this transmuted layer can also be a cause for the impairment of etch uniformity within wafer, like the deposition layers. This is because the transmuted layer is thicker near the central part of the wafer than near the edge part thereof. In contrast, according to the present embodiment, it is possible to adequately suppress the effects of the transmuted layer even if such a transmuted layer exists, by setting the second etching conditions so that a selection ratio with respect to the transmuted layer also decreases. Accordingly, it is possible to alleviate etch non-uniformity attributable to the transmuted layer.

In the present embodiment, there is further provided the cap layer 20 on the low-k dielectric layer 10. Consequently, it is possible to prevent the low-k dielectric layer 10 from not only suffering damage but also absorbing moisture at the time of chemical mechanical polishing (CMP).

Furthermore, there is no etch stop layer interposed between the low-k dielectric layer 10 and the cap layer 20. Accordingly, it is possible to reduce the cost of manufacturing a semiconductor device. In contrast, if an etch stop layer is provided as in the case of the semiconductor device described in Tokukai 2003-332421, the frequency of film-forming increases by as much as the number of additional steps of forming the etch stop layer and then forming an interlayer insulating layer thereon, thus resulting in an increase in the manufacturing costs.

In cases where an etching time in the first etching step is no shorter than 60% but no longer than 90% of an end point time, it is possible to improve etch uniformity within wafer. In this regard, FIGS. 3 to 5 show the results of tests performed to examine a relationship between the etching time and the irregularity of etch depth. In the tests mentioned above, an SiO2 layer was used as the cap layer 20. In addition, the-first etching conditions, i.e., the etching conditions of the SiO2 layer were set so that the pressure was 40 mTorr, the top power was 300 W, the bias output was 1000 W, the flow rate of CHF3 was 0.0351/min (35 sccm), the flow rate of CF4 was 0.0551/min (55 sccm), and the flow rate of Ar was 0.91/min (900 sccm).

FIGS. 3A and 3B are graphs showing test results when the etching time was specified as 70% of the end point time. The horizontal axes of these graphs represent the dimensions of a pattern of lines and spaces, i.e., line width (nm)/space width (nm). In addition, the vertical axes represent etch depth (nm) in FIG. 3A and a difference in the etch depth (nm) in FIG. 3B. The etch depths were measured at points 7 mm away from the central part (cntr) and from the edge part of the wafer, respectively. The etch depth was defined as a value obtained by subtracting the former measured value from the latter measured value.

FIGS. 4A and 4B show test results when the etching time was specified as 85% of the end point time, whereas FIGS. 5A and 5B show test results when the etching time was specified as 95% of the end point time. The meanings of the graphs shown in FIGS. 4A and 5A are the same as those of the graph shown in FIG. 3A. Likewise, the meanings of the graphs shown in FIGS. 4B and 5B are the same as those of the graph shown in FIG. 3B.

Comparison between these graphs reveals that the irregularity of etch depth is smaller when the etching time is within the above-described range (see FIG. 3 or FIG. 4) than when the etching time is out of the above-described range (no shorter than 60% but no longer than 90% of the end point time) (see FIG. 5).

FIGS. 6A and 6B are graphs showing the results of measuring the etch rate profiles of an SiO2 layer within wafer in cases where the present embodiment was applied. In contrast, FIGS. 7A and 7B are graphs showing the results of measuring the etch rate profiles of the SiO2 layer within wafer in cases where the present embodiment was not applied. The horizontal axes of these graphs represent a position (mm) measured with the center of the wafer defined as the point of origin, whereas the vertical axes represent an etch rate (nm/min). In addition, the X-axis denotes a horizontal direction when the notch of the wafer is faced downwardly and the Y-axis denotes a direction perpendicular to that direction, i.e., a vertical direction. FIGS. 6A and 7A show the results of measurement after parts in the chamber of the etching apparatus wore out, whereas FIGS. 6B and 7B show the results of measurement when the parts were new.

Comparison between these graphs reveals that an etch rate profile varies according to the degree of wear of parts in cases where the present embodiment was not applied (see FIG. 7), whereas the etch rate profile does not depend on the degree of wear of parts in cases where the present embodiment was applied (see FIG. 6). As described above, the manufacturing method in accordance with the present embodiment is superior in long-term stability.

In cases where the mixing ratio of oxygen in the second etching conditions is no lower than 0.4%, it is possible to improve etch uniformity within wafer. Furthermore, in cases where the mixing ratio of oxygen is no higher than 2.6%, it is possible to secure a sufficiently high selection ratio with respect to the resist 30 and control the degree of roughness to a minimum.

In this regard, FIGS. 8 and 9 show the results of tests performed to examine a relationship between the mixed amount of oxygen and the irregularity of etch depth in the second etching step. In the tests mentioned above, BD was used as the low-k dielectric layer 10. In addition, the second etching conditions were set so that the pressure was 40 mTorr, the top power was 1900 W, the bias output was 600 W., the flow rate of CHF3 was 0.0231/min (23 sccm), the flow rate of CF4 was 0.0231/min (23 sccm), and the flow rate of Ar is 0.41/min (400 sccm). In this case, the condition of the mixing ratio of oxygen being no lower than 0.4% but no higher than 2.6% corresponds to the condition of the flow rate of O2 being no lower than 0.0021/min (2 sccm) but no higher than 0.0121/min (12 sccm). In FIGS. 8 and 9, the flow rates of O2 were respectively set to 0.0031/min (3 sccm) and 0.0061/min (6 sccm). Other conditions are as described with regard to FIGS. 3 to 5. The meanings of the graphs shown in FIGS. 8A and 9A are the same as those of the graph shown in FIG. 3A. Likewise, the meanings of the graphs shown in FIGS. 8B and 9B are the same as those of the graph shown in FIG. 3B.

Comparison between these graphs reveals that the etch rate increases mainly in the vicinity of the central part of the wafer as the mixed amount of O2 increases, thus resulting in a decrease in the irregularity of etch depth. A possible cause for this is that O2 has the capability to decrease the amount of the depositions described earlier.

In cases where the top power in the second etching conditions is no lower than 1300 W but no higher than 2200 W, it is possible to improve etch uniformity within wafer. In this regard, FIGS. 10 to 12 show the results of tests performed to examine a relationship between the top power and the irregularity of etch depth. FIGS. 10, 11 and 12 show test results when the top power was set to 1000 W, 1400 W and 1600 W, respectively. The meanings of the graphs shown in FIGS. 10A, 11A and 12A are the same as those of the graph shown in FIG. 3A. Likewise, the meanings of the graphs shown in FIGS. 10B, 11B and 12B are the same as those of the graph shown in FIG. 3B.

Comparison between these graphs reveals that the etch rate increases mainly in the vicinity of the central part of the wafer as the top power increases, thus resulting in a decrease in the irregularity of etch depth. An increase in the top power facilitates decomposing of gases, thereby producing a fluorine-rich plasma. In addition, electron density increases easily in the central part of the wafer. Accordingly, a possible cause for the decrease in the irregularity of etch depth is that a fluorine-rich state was created in the central part of the wafer in particular and the etch rate increased in that part, thus reducing a difference in the etch depth.

Incidentally, an etching apparatus has a variety of consumable parts around a stage for fixing wafers. For example, a focus ring made of Si is located around a wafer. The wear of this focus ring made of Si affects the flow of gas passing above the wafer, thereby exercising an influence mainly on the depth and the film quality of depositions accumulating on the wafer. In addition, the resistance value of the focus ring varies according to the degree of wear thereof since the focus ring is located in the periphery of the stage, thereby affecting the state of convergence of a plasma. This also affects the film quality and thickness of depositions accumulating on the top surface of the wafer, as well as the orientation and the quantity of ions plunging into the wafer. Because of this phenomenon, the condition of a chamber varies on a day-to-day basis depending on the degree of wear of parts and there occurs a process shift, such as a variation in the etch depth between the central and edge parts of the wafer, in an etching apparatus used for production. It is therefore extremely important to set etching conditions in which a characteristic change in consumable parts are less influential to process characteristics.

In this regard, FIGS. 13A and 13B show the results of measuring etch depth profiles within wafer in cases where the present embodiment was applied. In contrast, FIGS. 14A and 14B show the results of measuring etch depth profiles within wafer in cases where the present embodiment was not applied. These figures are the results of optical critical dimension (OCD) measurement performed on patterns the line and space widths of which are equally 140 nm. The term “Uniformity” as used in the tables of each figure refers to a value calculated according to the formula “(max.−min.)/(2×Average)×100”. FIGS. 13A and 14A show the results of measurement after parts in the chamber of the etching apparatus wore out, whereas FIGS. 13B and 14B show the results of measurement when the parts were new.

Comparison between these measurement results shows that the irregularity of etch depth changes depending on the degree of wear of parts in cases where the present embodiment was not applied (see FIG. 14). On the other hand, the irregularity of etch depth hardly depends on the degree of wear of parts in cases where the present embodiment was applied (see FIG. 14).

The method of manufacturing a semiconductor device in accordance with the present invention is not limited to the above-described embodiments but may be modified in various other ways. In addition to the combinations exemplified in the above-described embodiments, a variety of other combinations are conceivable with regard to combinations of the first and second insulating layers. For example, both the first and second insulating layers may be low-k dielectric layers. A combination of low-k dielectric layers composed of the same material (for example, SiOC) is also acceptable as long as one of them is a porous layer. In that case, it is preferable that the first insulating layer be the porous layer.

While in the above-described embodiments, an example has been shown wherein no etch stop layer is interposed between the first and second insulating layers, an etch stop layer may be interposed therebetween. In that case, it is possible to further improve etch uniformity.

Furthermore, while in the above-described embodiments an example has been shown wherein a high-frequency output is applied to both the upper and lower electrodes, an etching apparatus wherein the high-frequency output is applied only to one of the upper and lower electrodes may be used.

Claims

1. A method of manufacturing a semiconductor device having a first insulating layer and a second insulating layer provided thereon, comprising:

etching said second insulating layer without exposing said first insulating layer under first etching condition; and
etching remnant of said second insulating layer left over said first insulating layer and said first insulating layer under second etching condition different from the first etching condition.

2. The method of manufacturing a semiconductor device as claimed in claim 1, wherein said second etching condition has not etching selectivity to said first and second insulating layer.

3. The method of manufacturing a semiconductor device as claimed in claim 1, wherein an etching time in said first etching step is no shorter than 60% but no longer than 90% of an etching time required to etch said second insulating layer to the last.

4. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the thickness of said remnant of said second insulating layer is no less than 10% but no greater than 40% of the total thickness of said second insulating layer.

5. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the flow rate of oxygen is larger under said second etching conditions than under said first etching conditions.

6. The method of manufacturing a semiconductor device as claimed in claim 5, wherein the mixing ratio of oxygen in said second etching conditions is no lower than 0.4% but no higher than 2.6%.

7. The method of manufacturing a semiconductor device as claimed in claim 1, wherein top power is higher under said second etching conditions than under said first etching conditions.

8. The method of manufacturing a semiconductor device as claimed in claim 7, wherein said top power under said second etching conditions is no lower than 1300 W but no higher than 2200 W.

9. The method of manufacturing a semiconductor device as claimed in claim 1, wherein said second insulating layer has permittivity higher than that of said first insulating layer.

10. The method of manufacturing a semiconductor device as claimed in claim 1, wherein said first insulating layer is a low-k dielectric layer.

11. The method of manufacturing a semiconductor device as claimed in claim 10, wherein said first insulating layer is made of SiOC.

12. The method of manufacturing a semiconductor device as claimed in claim 1, wherein said second insulating layer is made of SiO2, SiC, SiCN, SiN or BCB.

13. The method of manufacturing a semiconductor device as claimed in claim 1, wherein no etch stop layer is interposed between said first and second insulating layers.

14. The method of manufacturing a semiconductor device as claimed in claim 1, wherein said first and second etching steps are carried out as part of a dual damascene process.

15. The method of manufacturing a semiconductor device as claimed in claim 1, wherein

a gas consisting primarily of CH4-nFn (“n” is a natural number equal to or smaller than 4) is used with a pressure being no lower than 30 mTorr but no higher than 60 mTorr,
top power being no lower than 200 W but no higher than 600 W,
bias output thereof being no lower than 700 W but no higher than 1300 W, and
flow rate of Ar being no lower than 0.91/min (900 sccm) but no higher than 1.81/min (1800 sccm) under said first condition.

16. The method of manufacturing a semiconductor device as claimed in claim 1, wherein

a gas consisting primarily of CH4-nFn (“n” is a natural number equal to or smaller than 4) is used with a pressure being no lower than 30 mTorr but no higher than 60 mTorr,
top power being no lower than 1300 W but no higher than 2200 W,
bias output thereof being no lower than 600 W but no higher than 1200 W, and
flow rate of Ar being no lower than 0.21/min (200 sccm) but no higher than 0.61/min (600 sccm) under said second condition.

17. A method of a semiconductor devices comprising:

forming a first insulating layer and a second insulating layer on the first insulating layer;
performing an etching process in a first condition to make a hole in the second insulating layer, the hole having a depth that is smaller than a thickness of the second insulating layer so that a portion of the second insulating layer intervening between the first hole and the first insulating layer; and
performing an etching process in a second condition to remove the portion of the second insulating layer and make a second hole in the first insulating layer, the second condition being different from the first condition.

18. The method as claimed in claim 17, wherein the first and second holes are substantial equal in size to each other.

19. The method as claimed in claim 17, wherein the first and second insulating layer s are different in a material from each other.

Patent History
Publication number: 20080119054
Type: Application
Filed: Nov 8, 2007
Publication Date: May 22, 2008
Applicant: NEC ELECTRONICS CORPORATION (Kawasaki)
Inventor: Hidetaka Nambu (Kanagawa)
Application Number: 11/979,798
Classifications
Current U.S. Class: Formation Of Groove Or Trench (438/700); Etching Insulating Layer By Chemical Or Physical Means (epo) (257/E21.249)
International Classification: H01L 21/311 (20060101);