Formation Of Groove Or Trench Patents (Class 438/700)
  • Patent number: 11024534
    Abstract: A semiconductor device and a method for manufacturing the same. When a pattern for etching is formed through photolithography after forming a photoresist layer on an adhesion layer, a sub-resolution auxiliary pattern of the mask is above the non-lead-out region, and an exposable pattern of the mask is above a lead-out region. In the photolithography, a first partial exposure region exposed partially in depth is formed in the photoresist layer corresponding to the sub-resolution auxiliary pattern, and an exposed pattern that is exposed completely is formed in the photoresist layer corresponding to the exposable pattern. After anisotropic etching on the adhesion layer through the photoresist layer, both an opening running through a partial thickness of the adhesion layer and a via hole running through the adhesion layer are formed. The opening balances a load in planarization during a process of filling the via hole.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: June 1, 2021
    Assignee: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
    Inventors: Beibei Sheng, Sheng Hu
  • Patent number: 11004751
    Abstract: A semiconductor device includes a substrate with a first semiconductor fin and a second semiconductor fin formed thereon. A pair of opposing dielectric trench spacers are between the first and second semiconductor fins. The opposing dielectric trench spacers define an isolation region therebetween. The semiconductor device further includes a shallow trench isolation (STI) element formed in the isolation region. The STI element includes a lower portion on the substrate and an upper portion located opposite the lower portion. The upper portion extends above an upper end of the dielectric trench spacers.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: May 11, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Dexin Kong, Zhenxing Bi
  • Patent number: 10964587
    Abstract: An atomic layer deposition (ALD) technique is used to deposit one or more layers on hard mask layers and the sidewalls of low-K dielectric trench as part of the trench etch process. The ALD layer(s) can prevent the hard mask from being eroded during various hard mask open processes. Further, the ALD layer(s) may be utilized to prevent the low-K dielectric sidewall from being laterally etched during the low-K dielectric trench etch. Hence, better control of the trench profile and better critical dimension control may be provided.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: March 30, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Yen-Tien Lu, David O'Meara, Angelique Raley, Xinghua Sun
  • Patent number: 10950501
    Abstract: Fabrication schemes based on triblock copolymers for forming self-aligning vias or contacts for back end of line interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for a semiconductor die includes forming a lower metallization layer including alternating metal lines and dielectric lines above a substrate. The method also includes forming a triblock copolymer layer above the lower metallization layer. The method also includes segregating the triblock copolymer layer to form a first segregated block component over the dielectric lines of the lower metallization layer, and to form alternating second and third segregated block components disposed over the metal lines of the lower metallization layer, where the third segregated block component is photosensitive.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Todd R. Younkin, Eungnak Han, Shane M. Harlson, James M. Blackwell
  • Patent number: 10896941
    Abstract: The invention relates to: a light-emitting device which includes a first flexible substrate having a first electrode, a light-emitting layer over the first electrode, and a second electrode with a projecting portion over the light-emitting layer and a second flexible substrate having a semiconductor circuit and a third electrode electrically connected to the semiconductor circuit, in which the projecting portion of the second electrode and the third electrode are electrically connected to each other; a method for manufacturing the light-emitting device; and a cellular phone which includes a housing incorporating the light-emitting device and having a longitudinal direction and a lateral direction, in which the light-emitting device is disposed on a front side and in an upper portion in the longitudinal direction of the housing.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: January 19, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kaoru Hatano, Satoshi Seo, Shunpei Yamazaki
  • Patent number: 10886384
    Abstract: A method of forming a vertical fin field effect transistor with a self-aligned gate structure, comprising forming a plurality of vertical fins on a substrate, forming gate dielectric layers on opposite sidewalls of each vertical fin, forming a gate fill layer between the vertical fins, forming a fin-cut mask layer on the gate fill layer, forming one or more fin-cut mask trench(es) in the fin-cut mask layer, and removing portions of the gate fill layer and vertical fins not covered by the fin-cut mask layer to form one or more fin trench(es), and two or more vertical fin segments from each of the plurality of vertical fins, having a separation distance, D1, between two vertical fin segments.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10847460
    Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Shun Li Chen, Shih-Wei Peng, Tien-Lu Lin
  • Patent number: 10847517
    Abstract: A semiconductor device includes a semiconductor substrate having a gate trench including of an upper trench and a lower trench. The upper trench is wider than the lower trench. A gate is embedded in the gate trench. The gate includes an upper portion and a lower portion. A first gate dielectric layer is between the upper portion and a sidewall of the upper trench. The first gate dielectric layer has a first thickness. A second gate dielectric layer is between the lower portion and a sidewall of the lower trench and between the lower portion and a bottom surface of the lower trench. The second gate dielectric layer has a second thickness that is smaller than the first thickness.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: November 24, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tsuo-Wen Lu, Ger-Pin Lin, Tien-Chen Chan, Shu-Yen Chan
  • Patent number: 10818556
    Abstract: A method for forming a semiconductor structure is provided. Multiple fins extending along a first direction are formed in a semiconductor substrate. The multiple fins includes a group of active fins, a pair of protection fins sandwiching about the group the active fins, and at least one dummy fin around the pair of protection fins. A fin cut process is performed to remove the at least one dummy fin around the pair of protection fins. After performing the fin cut process, trench isolation structures are formed within the trenches between the multiple fins. The trench isolation structures are subjected to an anneal process. After annealing the trench isolation structures, the pair of protection fins is removed.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: October 27, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hao-Yeh Liu, Jia-Feng Fang, Yu-Hsiang Lin, Ching-Hsiang Chiu, Chia-Wei Liu
  • Patent number: 10804395
    Abstract: The present disclosure provides a semiconductor device structure in accordance with some embodiments. In some embodiments, the semiconductor device structure includes a semiconductor substrate of a first semiconductor material and having first recesses. The semiconductor device structure further includes a first gate stack formed on the semiconductor substrate and being adjacent the first recesses. In some examples, a passivation material layer of a second semiconductor material is formed in the first recesses. In some embodiments, first source and drain (S/D) features of a third semiconductor material are formed in the first recesses and are separated from the semiconductor substrate by the passivation material layer. In some cases, the passivation material layer is free of chlorine.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hsiung Tsai, Yuan-Ko Hwang
  • Patent number: 10745270
    Abstract: Provided herein is a method including fusion bonding a handle wafer to a first side of a device wafer. A hardmask is deposited on a second side of the device wafer, wherein the second side is planar. The hardmask is etched to form a MEMS device pattern and a standoff pattern. Standoffs are formed on the device wafer, wherein the standoffs are defined by the standoff pattern. A eutectic bond metal is deposited on the standoffs, the device wafer, and the hardmask. A first photoresist is deposited and removed, such that the first photoresist covers the standoffs. The eutectic bond metal is etched using the first photoresist. The MEMS device pattern is etched into the device wafer. The first photoresist and the hardmask are removed.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: August 18, 2020
    Assignee: InvenSense, Inc.
    Inventors: Daesung Lee, Dongyang Kang, Chienlu Chang, Bongsang Kim, Alan Cuthbertson
  • Patent number: 10734284
    Abstract: A method of self-aligned double patterning is disclosed in the present invention, which includes the step of forming multiple mandrels on a hard mask layer and spacers at two sides of each mandrel, forming a protection layer filling between the spacers, removing the mandrels to expose the hard mask layer, and performing an anisotropic etch process using the spacers and the protection layer as an etch mask to remove a portion of hard mask layer, so that a thickness of hard mask layer exposed between the spacers equals to a thickness of hard mask layer under the protection layer.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: August 4, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Ying-Chih Lin, Gang-Yi Lin, Chieh-Te Chen, Yi-Ching Chang
  • Patent number: 10714340
    Abstract: According to an embodiment, a wafer W includes a layer EL to be etched, an organic film OL, an antireflection film AL, and a mask MK1, and a method MT according to an embodiment includes a step of performing an etching process on the antireflection film AL by using the mask MK1 with plasma generated in a processing container 12, in the processing container 12 of a plasma processing apparatus 10 in which the wafer W is accommodated, and the step includes steps ST3a to ST4 of conformally forming a protective film SX on the surface of the mask MK1, and steps ST6a to ST7 of etching the antireflection film AL by removing the antireflection film AL for each atomic layer by using the mask MK1 on which the protective film SX is formed.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: July 14, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yoshihide Kihara, Toru Hisamatsu, Tomoyuki Oishi
  • Patent number: 10714382
    Abstract: Methods for forming conductive regions of a metallization network with reduced leakage current and capacitance are described. Aspects of the invention include forming a trench in a dielectric material on the substrate, forming a first liner layer in a first portion of the trench, forming a second liner layer in a second portion of the trench, and forming a conductive material over the second liner layer in the trench.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: July 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Raghuveer Patlolla, Cornelius Brown Peethala, Chih-Chao Yang
  • Patent number: 10658458
    Abstract: A method of forming a semiconductor structure is disclosed. A fin structure is formed on a substrate and a trench is formed in the fin structure. The trench has a top corner, an upper portion having an upper sidewall and a lower portion having a lower sidewall. A first dielectric layer is then formed on the substrate and fills the lower portion of the trench. After that, a second dielectric layer is formed on the substrate and covers the top corner and the upper sidewall of the trench. The second dielectric layer also covers an upper surface of the first dielectric layer.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: May 19, 2020
    Assignee: UNITED MICROELECTRONCIS CORP.
    Inventors: I-Ming Tseng, Chun-Hsien Lin, Wen-An Liang
  • Patent number: 10658181
    Abstract: A method of spacer-defined direct patterning in semiconductor fabrication includes: providing a photoresist structure having a target width of lines; trimming the photoresist structures such that a width of each trimmed photoresist structure is smaller than the target width; depositing an oxide film on the template, thereby entirely covering with the oxide film an exposed top surface of the template and the trimmed photoresist structures; etching the oxide film-covered template to remove an unwanted portion of the oxide film without removing the trimmed photoresist structures so as to form vertical spacers isolated from each other, each spacer substantially maintaining the target width and being constituted by the trimmed photoresist structures and a vertical portion of the oxide film covering sidewalls of the trimmed photoresist structures; and etching the spacer-formed template to transfer a pattern constituted by the spacers to the template.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: May 19, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Toshihisa Nozawa, Dai Ishikawa, Tomohiro Kubota
  • Patent number: 10658189
    Abstract: A method of selectively etching a first region R1 made of silicon oxide with respect to a second region R2 made of silicon nitride by performing a plasma processing upon a processing target object is provided. The processing target object has the second region R2 forming a recess; the first region R1 configured to fill the recess; and a mask MK provided on the first region R1. The method includes a first process of generating plasma of a processing gas containing a fluorocarbon gas, and a second process of etching the first region with radicals of fluorocarbon contained in a deposit. In the second process, a high frequency power contributing to the generating of the plasma is applied in a pulse shape, and these processes are repeated.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: May 19, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yoshinari Hatazaki, Wakako Ishida, Kensuke Taniguchi
  • Patent number: 10618805
    Abstract: Methods are provided for manufacturing well-controlled, solid-state nanopores and arrays of well-controlled, solid-state nanopores by a cyclic process including atomic layer deposition (ALD), or chemical vapor deposition (CVD), and etching. One or more features are formed in a thin film deposited on a topside of a substrate. A dielectric material is deposited over the substrate having the one or more features in the thin film. An etching process is then used to etch a portion of the dielectric material deposited over the substrate having the one or more features in the thin film. The dielectric material deposition and etching processes are optionally repeated to reduce the size of the features until a well-controlled nanopore is formed through the thin film on the substrate.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: April 14, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Joseph R. Johnson, Kenichi Ohno
  • Patent number: 10607835
    Abstract: An etching method is provided for etching a silicon-containing layer into a pattern of a mask that is formed by etching—from a block copolymer layer that includes a first polymer and a second polymer, that is layered on the silicon-containing layer of a process-target object via an intermediate layer, and that is enabled to be self-assembled—a region including the second polymer and the intermediate layer right under the region. The method includes forming a protective film on the mask by arranging upper and lower electrodes facing each other, by applying a negative DC voltage to the upper electrode in a processing chamber of a plasma processing apparatus in which the process-target object is provided, by applying high-frequency power to the upper or lower electrode, and by supplying a process gas including a hydrogen gas and an inert gas into the processing chamber to generate plasma.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: March 31, 2020
    Assignee: Tokyo Electron Limited
    Inventor: Yuki Takanashi
  • Patent number: 10573715
    Abstract: Embodiments of the present disclosure describe techniques for backside isolation for devices of an integrated circuit (IC) and associated configurations. The IC may include a plurality of devices (e.g., transistors) formed on a semiconductor substrate. The semiconductor substrate may include substrate regions on which one or more devices are formed. Trenches may be disposed between the devices on the semiconductor substrate. Portions of the semiconductor substrate between the substrate regions may be removed to expose the corresponding trenches and form isolation regions. An insulating material may be formed in the isolation regions. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: February 25, 2020
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Rishabh Mehandru, Harold W. Kennel, Paul B. Fischer, Stephen M. Cea
  • Patent number: 10566184
    Abstract: A process of forming a silicon nitride film on a nitride semiconductor layer as a passivation film is disclosed. The process first sets a temperature lower than 500° C. to load into a growth reactor, a wafer that provides the nitride semiconductor layer thereon. Then, the process raises the temperature to a deposition temperature higher than 750° C. while replacing the atmosphere in the reactor with pure ammonia (NH3), or a mixed gas of NH3 and N2 with a NH3 partial pressure greater than 0.2, and sets the pressure higher than 3 kPa. Finally, with the pressure lower than 100 Pa and di-chloro-silane (SiH2Cl2) supplied, the SiN is deposited on the nitride semiconductor layer.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: February 18, 2020
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Kazuhide Sumiyoshi
  • Patent number: 10546772
    Abstract: A plurality of interconnect features are formed in an interconnect layer on a first insulating layer on a substrate. An opening in the first insulating layer is formed through at least one of the interconnect features. A gap fill layer is deposited in the opening.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: January 28, 2020
    Assignee: Intel Corporation
    Inventors: Manish Chandhok, Richard E. Schenker, Hui Jae Yoo, Kevin L. Lin, Jasmeet S. Chawla, Stephanie A. Bojarski, Satyarth Suri, Colin T. Carver, Sudipto Naskar
  • Patent number: 10535702
    Abstract: An image sensor includes a first photodiode formed in a first substrate. A first deep-trench isolation (DTI) structure is in the first substrate and surrounds the first photodiode. A first inter-dielectric layer having a first circuit structure is formed on the first substrate. A bonding layer is between the first inter-dielectric layer and a second inter-dielectric layer. The second-inter dielectric layer having a second circuit structure is on the bonding layer. A connection wall is disposed in the first inter-dielectric layer, the bonding layer, and the second inter-dielectric layer to physically connect the first circuit structure and the second circuit structure. A second substrate is disposed on the second inter-dielectric layer. A second photodiode is formed in the second substrate. A second DTI structure is in the second substrate and surrounds the second photodiode.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: January 14, 2020
    Assignee: United Microelectronics Corp.
    Inventor: Cheng-Yu Hsieh
  • Patent number: 10468271
    Abstract: A dry etching method, including: etching a silicon-containing thin film with a first gas by a first preset thickness; etching the silicon-containing thin film with a second gas by a second preset thickness, to remove etching residues generated after etching the silicon-containing thin film by the first preset thickness; after the etching residues are removed, etching the silicon-containing thin film with the first gas by a third preset thickness, which is less than the first preset thickness; wherein the first gas includes chlorine gas, and the second gas includes fluoride gas.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: November 5, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Qingzhao Liu, Jiushi Wang, Lei Zhao
  • Patent number: 10388728
    Abstract: Structures that include an airgap and methods for forming a structure that includes an airgap. A layer stack is epitaxially grown on a substrate and includes a first semiconductor layer and a second semiconductor layer on a substrate. A plurality of openings are formed that extend through a device region of the first semiconductor layer to the second semiconductor layer. The second semiconductor layer is etched through the openings and selective to the substrate and the first semiconductor layer so as to form an airgap that is arranged in a vertical direction between the substrate and the device region. A device structure is formed in the device region of the first semiconductor layer.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: August 20, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Michael Zierak, Anthony K. Stamper, John J. Pekarik, Vibhor Jain
  • Patent number: 10340177
    Abstract: Intermediate semiconductor devices and methods of reducing damage during back end of the line (BEOL) metallization and metal one (M1) layer integration scheme are provided. One method includes, for instance: obtaining a wafer having at least one contact region; depositing on the wafer a thin film stack having at least one layer of amorphous silicon (a-Si); performing lithography to pattern at least one opening; performing lithography to pattern at least one via opening and at least one trench opening; and removing the at least one a-Si layer. One intermediate semiconductor device includes, for instance: a wafer having at least one contact region; at least one first dielectric layer on the device; at least one second dielectric layer on the at least one first dielectric layer; and at least one a-Si layer on the at least one second dielectric layer.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: July 2, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ashwini Chandrashekar, Anbu Selvam Km Mahalingam, Craig Michael Child, Jr.
  • Patent number: 10273152
    Abstract: Methods for manufacturing MEMS structures are provided. The method includes forming a first trench and a second trench in a MEMS substrate by performing a main etching process and etching the MEMS substrate through the first trench and the second trench to form a first through hole and an extended second trench by performing a first step of an over-etching process. The method further includes etching the MEMS substrate through the extended second trench to form a second through hole by performing a second step of the over-etching process. In addition, a width of the first trench is greater than a width of the second trench, and a height of the first trench is greater than ¾ of a height of the MEMS substrate, and a height of the second trench is smaller than ? of the MEMS substrate.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Han Meng, Jr-Sheng Chen, Chih-Hsien Hsu, Yu-Pei Chiang, Lin-Ching Huang
  • Patent number: 10214833
    Abstract: The present invention relates to additive manufacturing methods, in which crystalline materials can be formed by using a liquid precursor. In particular embodiments, the crystalline material is a perovskite. The methods include the use of a thermal voxel, which can be translated to form any arbitrary pattern of initial crystalline seed structure(s). Then, the seed structure can be incubated to promote crystal growth and/or crystal dissolution, thereby providing a patterned crystalline material.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: February 26, 2019
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Bryan James Kaehr, Stanley Shihyao Chou
  • Patent number: 10153165
    Abstract: The present invention pertains to a patterning method. By taking advantage of the etching loading effect due to different pattern densities in the memory cell region and the peripheral region, the first hard mask is not masked when anisotropically etching the first hard mask within the memory cell region.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: December 11, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Ming-Feng Kuo, Chien-Cheng Tsai
  • Patent number: 10109582
    Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Shun Li Chen, Shih-Wei Peng, Tien-Lu Lin
  • Patent number: 10094797
    Abstract: A semiconductor-based multi-sensor module integrates miniature temperature, pressure, and humidity sensors onto a single substrate. Pressure and humidity sensors can be implemented as capacitive thin film sensors, while the temperature sensor is implemented as a precision miniature Wheatstone bridge. Such multi-sensor modules can be used as building blocks in application-specific integrated circuits (ASICs). Furthermore, the multi-sensor module can be built on top of existing circuitry that can be used to process signals from the sensors. An integrated multi-sensor module that uses differential sensors can measure a variety of localized ambient environmental conditions substantially simultaneously, and with a high level of precision. The multi-sensor module also features an integrated heater that can be used to calibrate or to adjust the sensors, either automatically or as needed.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: October 9, 2018
    Assignee: STMICROELECTRONICS PTE LTD.
    Inventors: Olivier Le Neel, Ravi Shankar, Suman Cherian, Calvin Leung, Tien-Choy Loh, Shian-Yeu Kam
  • Patent number: 10090378
    Abstract: Capacitors and methods of forming the same include forming a self-assembled pattern of periodic first and second domains using first and second block copolymer materials over a substrate. The second block copolymer material is etched away. Material from the substrate is etched based on a pattern defined by the first block copolymer material to form cavities in the substrate. A capacitor stack is conformally deposited over the substrate, such that the capacitor stack is formed on horizontal surfaces of the substrate and vertical surfaces of the cavities.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: October 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kisup Chung, Isabel C. Estrada-Raygoza, Hemanth Jagannathan, Chi-Chun Liu, Yann A. M. Mignot, Hao Tang
  • Patent number: 10068805
    Abstract: Semiconductor devices include one or more semiconductor fins. A gate is formed over the one or more semiconductor fins. A vertical sidewall is formed at a perimeter of the gate, the vertical sidewall having a uniform thickness along its height. A power rail is formed in contact with the vertical sidewall.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: September 4, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Dechao Guo, Zuoguang Liu
  • Patent number: 10043868
    Abstract: A semiconductor structure and method of forming the same. The semiconductor structure includes a fin structure formed on a substrate and an isolation structure formed therein. The isolation structure includes a trench with a concave upper sidewall, a straight lower sidewall and a rounded top corner. A first dielectric layer fills a lower portion of the trench. A second dielectric layer covers a top surface of the first dielectric layer, the concave upper sidewall and the rounded top corner of the trench.
    Type: Grant
    Filed: August 28, 2016
    Date of Patent: August 7, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: I-Ming Tseng, Chun-Hsien Lin, Wen-An Liang
  • Patent number: 10020183
    Abstract: A method for processing a stack with an etch layer below a mask is provided. The mask is treated by flowing a treatment gas, wherein the treatment gas comprises a sputtering gas and a trimming gas, providing pulsed TCP power to create a plasma from the treatment gas, and providing a pulsed bias, wherein the pulsed bias has a same period as the pulsed TCP power, wherein the pulsed TCP power and pulsed bias provide a first state with a first bias above a sputter threshold and a first TCP power, which causes species from the sputtering gas to sputter and redeposit material from the mask, and provide a second state with a second bias below the sputter threshold and a second TCP power, wherein the second TCP power is greater than the first TCP power, which causes species from the trimming gas to chemically trim the mask.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: July 10, 2018
    Assignee: Lam Research Corporation
    Inventors: Yansha Jin, Zhongkui Tan, Lin Cui, Qian Fu, Martin Shim
  • Patent number: 9995708
    Abstract: In one implementation, a chemical sensor is described. The chemical sensor includes chemically-sensitive field effect transistor including a floating gate conductor having an upper surface. A dielectric material defines an opening extending to the upper surface of the floating gate conductor. A conductive sidewall spacer is on a sidewall of the opening and contacts the upper surface of the floating gate conductor.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: June 12, 2018
    Assignee: Life Technologies Corporation
    Inventors: Keith G. Fife, James Bustillo, Jordan Owens
  • Patent number: 9991133
    Abstract: Techniques herein provide an etch-based planarization technique. An initial film is deposited on a substrate. Deposition of this initial film results in a non-planar film because of differences in area density of underlying structures (for example, open areas compared to closely spaced trenches). Etch processes are executed that use a reverse lag RIE process to planarize the initial film, and then another coat of the film material can be deposited, resulting in a planar surface. Such techniques can planarized substrates without using chemical mechanical polishing (CMP).
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: June 5, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Cheryl Pereira, Nihar Mohanty, Lior Huli
  • Patent number: 9935012
    Abstract: Disclosed are methods of forming different shapes in different regions of a specific layer. In the methods, a first mask layer and an etch process are used to form first shapes in a first region. Subsequently, a second mask layer and additional etch process(es) are used to form second shapes in a second region. However, before the second shapes are formed, a sacrificial layer of a degradable material is deposited onto the first mask layer and within openings in the specific layer surrounding the first shapes, thereby protecting the first shapes during formation of the second shapes. After the second shapes are formed, the material of the sacrificial layer is degraded (e.g., oxidized, volatilized, burned-off, etc.) so as to selectively remove that material from surfaces of the first mask layer and the specific layer without impacting the profiles of either the first shapes or the second shapes.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: April 3, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jinsheng Gao, Haigou Huang
  • Patent number: 9835585
    Abstract: In one implementation, a chemical sensor is described. The chemical sensor includes a chemically-sensitive field effect transistor including a floating gate conductor having an upper surface. A conductive element protrudes from the upper surface of the floating gate conductor into an opening. A dielectric material defines a reaction region. The reaction region overlies and extends below an upper surface of the conductive element.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: December 5, 2017
    Assignee: LIFE TECHNOLOGIES CORPORATION
    Inventors: Keith G. Fife, Jordan Owens, Shifeng Li, James Bustillo
  • Patent number: 9761557
    Abstract: Methods for bonding two wafers are disclosed. In one aspect, a first wafer includes an integrated circuit and the second wafer including a MEMS device. The method comprises depositing a bond pad on a metal on the first wafer and sequentially bonding the first wafer to the second wafer utilizing first and second temperatures. The second wafer is bonded to the bond pad at the first temperature and the bond pad and the metal are bonded at the second temperature. In another aspect, a first wafer including an integrated circuit, the second wafer includes a MEMS device. The method comprises depositing a bond pad on a metal on one of the first wafer and the second wafer and bonding the first wafer to the second wafer at a first temperature via a direct bond interface. The method includes bonding the bond pad to the metal at a second temperature.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: September 12, 2017
    Assignee: INVENSENSE, INC.
    Inventors: Jong Il Shin, Peter Smeys, Jongwoo Shin
  • Patent number: 9640427
    Abstract: A method for forming a semiconductor structure is provided. The method includes providing a substrate; and forming an ultra-low-dielectric-constant (ULK) dielectric layer on a surface of the substrate. The method also includes etching the ultra-low-dielectric-constant dielectric layer to form a trench in the ultra-low-dielectric-constant dielectric layer; and performing an inert plasma treatment process on a side surface of the trench. Further, the method includes performing a carbonization process on the side surface of the trench; and performing a nitridation process on the side surface of the trench to form a SiCNH layer on the side surface of the trench.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: May 2, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Hao Deng
  • Patent number: 9607997
    Abstract: A wide trench having a width W1 and narrow trenches having a width W2 that is less than W1 are formed in a dielectric layer, the wide trench extending deeper in outer regions than in a central region. A trench modification step changes the width of the wide trench and reduces a depth difference between the outer regions and the central region of the wide trench.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: March 28, 2017
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Katsuo Yamada, Yuji Takahashi, Noritaka Fukuo, Masami Uozaki, Kiyokazu Shishido, Takuya Futase, Shunsuke Watanabe
  • Patent number: 9607883
    Abstract: A method embodiment includes forming a hard mask over a dielectric layer, patterning the hard mask to form an opening, forming a passivation layer on sidewalls of the opening, and forming a trench in the dielectric layer by extending the opening into the dielectric layer using an etching process. The sidewalls of the opening are etched to form a rounded profile in the hard mask and a substantially perpendicular profile in the dielectric layer.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: March 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chien-Chih Chiu
  • Patent number: 9583361
    Abstract: A method of processing a target object includes (a) exposing a resist mask to active species of hydrogen generated by exciting plasma of a hydrogen-containing gas within a processing vessel while the target object is mounted on a mounting table provided in the processing vessel; and (b) etching a hard mask layer by exciting plasma of an etchant gas within the processing vessel after the exposing of the resist mask to the active species of hydrogen. The plasma is excited by applying of a high frequency power for plasma excitation to an upper electrode. In the method, a distance between the upper electrode and the mounting table in the etching of the hard mask layer ((b) process) is set to be larger than a distance between the upper electrode and the mounting table in the exposing of the resist mask to the active species of hydrogen ((a) process).
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: February 28, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yoshihide Kihara, Hiromi Mochizuki, Masanobu Honda, Masaya Kawamata, Ken Kobayashi, Ryoichi Yoshida
  • Patent number: 9536778
    Abstract: Self-aligned double patterning processes to produce metal route between and connecting conductive lines are disclosed. Embodiments include forming a hard mask over a dielectric layer; forming a patterning template including plural parallel linear elements on the hard mask, wherein said hard mask is exposed between adjacent parallel linear elements; forming a block mask covering a portion of said adjacent parallel linear elements and spaces therebetween; etching exposed portions of said hard mask through said block mask and said patterning template defining plural parallel lines; removing said block mask and said patterning template; forming a cut mask above said hard mask to define an opening perpendicular to and connecting two adjacent parallel lines; etching said hard mask through said cut mask and removing the cut mask; etching recesses in the dielectric layer through said hard mask; removing the hard mask; and filling said recesses with a conductive material.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: January 3, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Lei Yuan, Jongwook Kye, Harry J Levinson
  • Patent number: 9469524
    Abstract: A method of forming a semiconductor device includes bonding a capping wafer and a base wafer to form a wafer package. The base wafer includes a first chip package portion, a second chip package portion, and a third chip package portion. The capping wafer includes a plurality of isolation trenches. Each isolation trench of the plurality of isolation trenches is substantially aligned with a corresponding trench region of one of the first chip package portion, the second chip package portion or the third chip package portion. The method also includes removing a portion of the capping wafer to expose a first chip package portion contact, a second chip package portion contact, and a third chip package portion contact. The method further includes separating the wafer package into a first chip package configured to perform a first operation, a second chip package configured to perform a second operation, and a third chip package configured to perform a third operation.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: October 18, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-wen Cheng, Jung-Huei Peng, Shang-Ying Tsai, Hung-Chia Tsai, Yi-Chuan Teng
  • Patent number: 9427953
    Abstract: A method of manufacturing a liquid ejection head includes forming, on the substrate, a metal layer formed of a first metal, forming a liquid flow path pattern formed of a second metal that is a metal of a different kind from that of the first metal and that is dissolvable in a solution that does not dissolve the first metal, the liquid flow path pattern being formed on at least a part of a surface of the metal layer, covering the metal layer and the pattern with an inorganic material layer to be formed as the nozzle layer, forming the ejection orifices in the inorganic material layer, and removing the pattern by the solution. A standard electrode potential E1 of the first metal and a standard electrode potential E2 of the second metal have a relationship of E1>E2.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: August 30, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Kazuaki Shibata, Makoto Sakurai, Yuzuru Ishida, Sadayoshi Sakuma
  • Patent number: 9391081
    Abstract: A first depression and a second depression are formed in an upper surface of a first metal layer. A dielectric layer is formed over the first metal layer. Subsequently, a wide trench is formed in the dielectric layer, the wide trench extending deeper in a first outer region and in a second outer region than in a central region located between the first outer region and the second outer region, the first outer region overlying the first depression and the second outer region overlying the second depression.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: July 12, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Kiyokazu Shishido, Takuya Futase, Noritaka Fukuo, Yuji Takahashi, Shunsuke Watanabe, Katsuo Yamada, Masami Uozaki
  • Patent number: 9385122
    Abstract: A method for manufacturing a semiconductor device comprises growing a source/drain epitaxy region over a plurality of gates on a substrate, wherein a top surface of the source/drain epitaxy region is at a height above a top surface of each of the plurality of gates, forming at least one opening in the source/drain epitaxy region over a top surface of at least one gate, forming a silicide layer on the source/drain epitaxy region, wherein the silicide layer lines lateral sides of the at least one opening, depositing a dielectric layer on the silicide layer, wherein the dielectric layer is deposited in the at least one opening between the silicide layer on lateral sides of the at least one opening, etching the dielectric layer to form a contact area, and depositing a conductor in the contact area.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: July 5, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Szu-Lin Cheng, Jack Oon Chu, Isaac Lauer, Jeng-Bang Yau
  • Patent number: 9384998
    Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reactants and/or reaction mechanisms that result in substantially complete sidewall coating at relatively low temperatures without the use of plasma. In some cases the protective coating is deposited using molecular layer deposition techniques.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: July 5, 2016
    Assignee: Lam Research Corporation
    Inventors: Eric A. Hudson, Dennis M. Hausmann, Joseph Scott Briggs