Abstract: Provided is a method of manufacturing a memory device and a patterning method. The patterning method includes following steps. A control structure including stop layers and oxide layers stacked alternately, a hard mask layer, and a mask pattern are sequentially formed on a target layer. A photoresist layer is formed in the mask pattern on the hard mask layer. A portion of the hard mask layer and a portion of the control structure are removed to form first openings by using the photoresist layer and the mask pattern as a mask. The photoresist layer and the hard mask layer are removed to form a second opening having a bottom surface higher than that of the first openings. At least one etching process is performed so that the first and second openings extend into and divide the control structure and the target layer into stack structures.

Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes forming a first patterned layer over a substrate; forming a second patterned layer over the substrate and alternately arranged with the first patterned layer; performing an etching, thereby forming an arched surface of the first patterned layer and an arched surface of the second patterned layer; forming a sacrificial layer over the first patterned layer and the second patterned layer, wherein a plurality of air gaps are defined by the substrate, the first patterned layer, the second patterned layer and the sacrificial layer; removing the sacrificial layer above the plurality of air gaps, thereby forming a planar top surface of the first patterned layer and a planar top surface of the second patterned layer; and patterning the substrate using the first patterned layer and the second patterned layer as a mask.

Abstract: Permanent magnets and method of making the same are provided. The magnets include a magnetic layer having an insulation layer disposed thereon. The insulation layer is formed via additive manufacturing techniques such as laser melting such that that it has discrete phases including a magnetic phase and an insulating phase.

Abstract: Semiconductor structures and fabrication methods thereof are provided. The method may include providing a to-be-etched layer; forming a plurality of core layers on the to-be-etched layer, wherein a first opening and a second opening are formed between different adjacent core layers and a width of the first opening is smaller than a width of the second opening; forming a first sacrificial material layer on the to-be-etched layer and the plurality of core layers; forming a second sacrificial layer on a portion of the first sacrificial material layer in the first opening to form a sacrificial structure in the first opening; removing the plurality of core layers after forming the sacrificial structure; forming sidewall spacers on sidewall surfaces of the sacrificial structure after removing the plurality of core layers; and removing the sacrificial structure after forming the sidewall spacers.

Abstract: Embodiments of the present disclosure provide a method for forming a hole structure in a semiconductor device. The method for forming a hole structure having a first hole portion and a second hole portion connected to and over the first portion in a stack structure of a semiconductor device includes determining a hard mask layer. An etching resistivity of the hard mask layer may be inversely proportional to a difference between a first lateral dimension of the first hole portion and a second lateral dimension of the second hole portion, and the first lateral dimension may be less than the second lateral dimension. The method may also include forming the hard mask layer over the stack structure, and patterning the hard mask layer to form a first patterned hard mask layer that has a first mask opening. The first mask opening may have the first lateral dimension.

Abstract: A method for patterning a substrate in which a patterned photoresist structure can be formed on the substrate, the patterned photoresist structure having a sidewall. A conformal layer of spacer material can be deposited on the sidewall. The patterned photoresist structure can then be removed from the substrate, leaving behind the spacer material. Then, the substrate can be directionally etched using the sidewall spacer as an etch mask to form the substrate having a target critical dimension.

Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.

Abstract: A semiconductor device includes a die, a plurality of dielectric layers over the die, a via and at least one ring. The dielectric layers include a plurality of first surfaces facing the die. The via penetrates through the plurality of dielectric layers and includes at least one second surface facing the die. The ring surrounds the via and is disposed in at least one of the plurality of dielectric layers. The ring includes a third surface facing the die, wherein the third surface of the at least one ring is inserted between the at least one second surface of the via and the first surface of the at least one of the plurality of dielectric layers.

Abstract: There is a provided a technique that includes forming a film containing Si, C and N on a substrate by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: (a) supplying a first precursor containing a Si—C bond and not containing halogen to the substrate; and (b) supplying a second precursor containing a Si—N bond and not containing an alkyl group to the substrate, wherein (a) and (b) are performed under a condition that at least a part of the Si—C bond in the first precursor and at least a part of the Si—N bond in the second gas are held without being cut.

Abstract: A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.

Abstract: Split ash processes are disclosed to suppress damage to low-dielectric-constant (low-K) layers during via formation. For one embodiment, ash processes used to remove an organic layer, such as an organic planarization layer (OPL), associated with via formation are split into multiple ash process steps that are separated by intervening process steps. A first ash process is performed to remove a portion of an organic layer after vias have been partially opened to a low-K layer. Subsequently, after the vias are fully opened through the low-K layer, an additional ash process is performed to remove the remaining organic material. Although some damage may still occur on via sidewalls due to this split ash processing, the damage is significantly reduced as compared to prior solutions, and device performance is improved. Target critical dimension (CD) for vias and effective dielectric constants for the low-K layer are achieved.

Abstract: A dual-shell architecture and methods of fabrication of fused quartz resonators is disclosed. The architecture may include two encapsulated and concentric cavities using plasma-activated wafer bonding followed by the high-temperature glassblowing. The dual-shell architecture can provide a protective shield as well as a “fixed-fixed” anchor for the sensing element of the resonators. Structures can be instrumented to operate as a resonator, a gyroscope, or other vibratory sensor and for precision operation in a harsh environment. Methods for fabricating a dual-shell resonator structure can include pre-etching cavities on a cap wafer, pre-etching cavities on a device wafer, bonding the device wafer to a substrate wafer to form a substrate pair and aligning and bonding the cap wafer to the substrate pair to form a wafer stack with aligned cavities including a cap cavity and a device cavity. The wafer stack may be glassblown to form a dual-shell structure.

Abstract: A method of forming a semiconductor device includes forming first sacrificial patterns on a lower structure, forming first remaining mask layers having a “U” shape between the first sacrificial patterns to be in contact with the first sacrificial patterns, forming first remaining mask patterns by pattering the first remaining mask layers, each of the first remaining mask patterns including a horizontal portion, parallel to an upper surface of the lower structure, and a vertical portion, perpendicular to the upper surface of the lower structure, forming second mask patterns spaced apart from the vertical portions of the first remaining mask patterns, removing the first sacrificial patterns remaining after forming the second mask patterns, and forming first mask patterns by etching the horizontal portions of the first remaining mask patterns.

Abstract: The present disclosure provides a method of fabricating a semiconductor structure with a reduced pitch (half-pitch feature) and a method of fabricating the same. The method includes providing a substrate; forming a dielectric layer disposed on the substrate; forming at least one main feature disposed in the dielectric layer and contacting the substrate; forming at least one first conductive feature disposed in the dielectric layer and on the main feature; forming at least one first spacer interposed between the dielectric layer and a portion of the first conductive feature; forming a plurality of second conductive features disposed in the dielectric layer and on either side of the first conductive feature; and forming a plurality of second spacers interposed between the dielectric layer and portions of the second conductive features.

Abstract: A composition for forming an organic film contains a polymer having a partial structure shown by the following general formula (1) as a repeating unit, and an organic solvent. Each of AR1 and AR2 represents a benzene ring or naphthalene ring which optionally have a substituent; W1 represents a particular partial structure having a triple bond, and the polymer optionally contains two or more kinds of W1; and W2 represents a divalent organic group having 6 to 80 carbon atoms and at least one aromatic ring. This invention provides: a polymer curable even under film formation conditions in an inert gas and capable of forming an organic film which has not only excellent heat resistance and properties of filling and planarizing a pattern formed in a substrate, but also favorable film formability onto a substrate with less sublimation product; and a composition for forming an organic film, containing the polymer.

Abstract: In an antenna in package structure, a plurality of supporting blocks spaced apart from each other are disposed between a first substrate and a second substrate, and an antenna cavity is formed between every two adjacent supporting blocks. Therefore, a height of the supporting block determines a height of the antenna cavity. The supporting blocks spaced apart from each other are located between the first substrate and the second substrate, and at least one of the first substrate or the second substrate adheres to the supporting blocks spaced apart from each other using an adhesive layer.

Abstract: An object of the present invention is to provide: a compound containing an imide group which is not only cured under film formation conditions of inert gas as well as air and has excellent heat resistance and properties of filling and planarizing a pattern formed on a substrate, but can also form an organic underlayer film with favorable adhesion to a substrate, and a material for forming an organic film containing the compound.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first conductive structure over the semiconductor substrate. The semiconductor device structure also includes a first dielectric layer surrounding the first conductive structure and a second dielectric layer over the first dielectric layer. The semiconductor device structure further includes a second conductive structure partially surrounded by the second dielectric layer and partially surrounded by the first conductive structure. In addition, the semiconductor device structure includes an interfacial layer separating the first conductive structure from the second conductive structure.

Abstract: A semiconductor device and method of manufacturing thereof are provided. The semiconductor device includes a substrate, a first dielectric layer, an isolation layer, a conductor and a liner layer. The substrate has a top surface and a bottom surface opposite the top surface. The first dielectric layer is on the bottom surface of the substrate, in which the first dielectric layer comprises an interconnect structure disposed therein. The isolation layer is on the top surface of the substrate. The conductor is disposed in the substrate and covers a portion of the isolation layer, in which the conductor includes a first portion connected to the interconnect structure and a second portion on the first portion, in which the first portion has a width greater than a width of the second portion. The liner layer is disposed between the substrate and the conductor.

Abstract: A method for manufacturing a semiconductor device includes: forming a first film on a substrate; forming a second film containing at least carbon on the first film; forming a hole in the second film; and forming a recess, which communicates with the hole, in the first film by etching using the second film as a mask. In this method, the second film includes a first layer formed on the first film, and a second layer formed on the first layer. The first layer having a higher oxygen concentration than the second layer.

Abstract: In some methods, a first recess is etched in a selected region of a substrate. A first polymer liner is formed on sidewalls and a bottom surface of the first recess. A portion of the first polymer liner is removed from the bottom surface, and a remaining portion of the first polymer liner is left along the sidewalls. The first recess is deepened to establish a second recess while the remaining portion of the first polymer liner is left along the sidewalls. A first oxide liner is formed along the sidewalls and along sidewalls and a bottom surface of the second recess. A portion of the first oxide liner is removed from a bottom surface of the second recess, while a remaining portion of the first oxide liner is left on the sidewalls of the first recess and the sidewalls of the second recess.

Abstract: High etch contrast materials provide the basis for using pre-patterned template structure with a template hardmask having periodic holes and filler within the holes that provides the basis for rapidly obtaining high resolution patterns guided by the template and high etch contrast resist. Methods are described for performing the radiation lithography, e.g., EUV radiation lithography, using the pre-patterned templates. Also, methods are described for forming the templates. The materials for forming the templates are described.

Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.

Abstract: A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

Abstract: The invention relates to: a light-emitting device which includes a first flexible substrate having a first electrode, a light-emitting layer over the first electrode, and a second electrode with a projecting portion over the light-emitting layer and a second flexible substrate having a semiconductor circuit and a third electrode electrically connected to the semiconductor circuit, in which the projecting portion of the second electrode and the third electrode are electrically connected to each other; a method for manufacturing the light-emitting device; and a cellular phone which includes a housing incorporating the light-emitting device and having a longitudinal direction and a lateral direction, in which the light-emitting device is disposed on a front side and in an upper portion in the longitudinal direction of the housing.

Abstract: An etching method includes: providing a substrate having a film and a patterned mask on the film; forming a silicon-containing layer including silicon, carbon, and nitrogen on the substrate using a precursor gas containing silicon; and performing a plasma etching on the film. The substrate is placed under a depressurized environment for a time period from a start time point of the step of forming the silicon-containing layer on the substrate to an end time point of the step of performing the plasma etching on the film.

Abstract: The present disclosure describes an exemplary method to form p-type fully strained channel (PFSC) or an n-type fully strained channel (NFSC) that can mitigate epitaxial growth defects or structural deformations in the channel region due to processing. The exemplary method can include (i) two or more surface pre-clean treatment cycles with nitrogen trifluoride (NF3) and ammonia (NH3) plasma, followed by a thermal treatment; (ii) a prebake (anneal); and (iii) a silicon germanium epitaxial growth with a silicon seed layer, a silicon germanium seed layer, or a combination thereof.

Abstract: The present application relates to an OLED panel for a lighting device and a method of manufacturing the same. An OLED panel for a lighting device includes: a substrate; a auxiliary wiring pattern having a plurality of wiring lines disposed on the substrate; a first electrode disposed on the substrate where the auxiliary wiring pattern is disposed, and having a planarized upper surface; a passivation layer disposed on the first electrode and disposed at least in an area above the auxiliary wiring pattern; an OLED emission structure disposed on the first electrode; and a second electrode disposed on the OLED emission structure. In the OLED panel for a lighting device, luminance uniformity may be improved through a dual auxiliary wiring pattern, and the upper surface of the first electrode is planarized. Accordingly, the area of the passivation layer is reduced, and thus a light-emitting area may be increased.

Abstract: A semiconductor device includes a semiconductive substrate, a first semiconductive fin and a second semiconductive fin extending upwards from the semiconductive substrate, an isolation structure at least partially between the first semiconductive fin and the second semiconductive fin, a first semiconductive raised portion and a second semiconductive raised portion. The first semiconductive raised portion extends upwards from the semiconductive substrate, is buried under the isolation structure, and is between the first semiconductive fin and the second semiconductive fin. A top surface of the first semiconductive fin is higher than a top surface of the first semiconductive raised portion. The second semiconductive raised portion extends upwards from the semiconductive substrate, is buried under the isolation structure, and is between the first semiconductive raised portion and the second semiconductive fin.

Abstract: A method includes forming a recess in a first substrate, bonding a micro-electro-mechanical systems (MEMS) substrate to the first substrate after forming the recess in the first substrate, forming an anti-stiction layer over the micro-electro-mechanical systems (MEMS) substrate, pattering the anti-stiction layer, etching the MEMS substrate to form a MEMS device, and bonding the MEMS device and the first substrate to a second substrate. The patterned anti-stiction layer is between the MEMS device and the second substrate.

Abstract: Embodiments of the invention address several issues and problems associated with etching of dielectric materials for BEOL applications. According to one embodiment, the method includes providing a patterned substrate containing a dielectric material, exposing the substrate to a gas phase plasma to functionalize a surface of the dielectric material, exposing the substrate to a silanizing reagent that reacts with the functionalized surface of the dielectric material to form a dielectric film, and sequentially repeating the exposing steps at least once to increase a thickness of the dielectric film. According to one embodiment, the dielectric material may be a porous low-k material, and the dielectric film seals the pores on a surface of the porous low-k material.

Abstract: A semiconductor device and a method for manufacturing the same. When a pattern for etching is formed through photolithography after forming a photoresist layer on an adhesion layer, a sub-resolution auxiliary pattern of the mask is above the non-lead-out region, and an exposable pattern of the mask is above a lead-out region. In the photolithography, a first partial exposure region exposed partially in depth is formed in the photoresist layer corresponding to the sub-resolution auxiliary pattern, and an exposed pattern that is exposed completely is formed in the photoresist layer corresponding to the exposable pattern. After anisotropic etching on the adhesion layer through the photoresist layer, both an opening running through a partial thickness of the adhesion layer and a via hole running through the adhesion layer are formed. The opening balances a load in planarization during a process of filling the via hole.

Abstract: A semiconductor device includes a substrate with a first semiconductor fin and a second semiconductor fin formed thereon. A pair of opposing dielectric trench spacers are between the first and second semiconductor fins. The opposing dielectric trench spacers define an isolation region therebetween. The semiconductor device further includes a shallow trench isolation (STI) element formed in the isolation region. The STI element includes a lower portion on the substrate and an upper portion located opposite the lower portion. The upper portion extends above an upper end of the dielectric trench spacers.

Abstract: An atomic layer deposition (ALD) technique is used to deposit one or more layers on hard mask layers and the sidewalls of low-K dielectric trench as part of the trench etch process. The ALD layer(s) can prevent the hard mask from being eroded during various hard mask open processes. Further, the ALD layer(s) may be utilized to prevent the low-K dielectric sidewall from being laterally etched during the low-K dielectric trench etch. Hence, better control of the trench profile and better critical dimension control may be provided.

Abstract: Fabrication schemes based on triblock copolymers for forming self-aligning vias or contacts for back end of line interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for a semiconductor die includes forming a lower metallization layer including alternating metal lines and dielectric lines above a substrate. The method also includes forming a triblock copolymer layer above the lower metallization layer. The method also includes segregating the triblock copolymer layer to form a first segregated block component over the dielectric lines of the lower metallization layer, and to form alternating second and third segregated block components disposed over the metal lines of the lower metallization layer, where the third segregated block component is photosensitive.

Abstract: The invention relates to: a light-emitting device which includes a first flexible substrate having a first electrode, a light-emitting layer over the first electrode, and a second electrode with a projecting portion over the light-emitting layer and a second flexible substrate having a semiconductor circuit and a third electrode electrically connected to the semiconductor circuit, in which the projecting portion of the second electrode and the third electrode are electrically connected to each other; a method for manufacturing the light-emitting device; and a cellular phone which includes a housing incorporating the light-emitting device and having a longitudinal direction and a lateral direction, in which the light-emitting device is disposed on a front side and in an upper portion in the longitudinal direction of the housing.

Abstract: A method of forming a vertical fin field effect transistor with a self-aligned gate structure, comprising forming a plurality of vertical fins on a substrate, forming gate dielectric layers on opposite sidewalls of each vertical fin, forming a gate fill layer between the vertical fins, forming a fin-cut mask layer on the gate fill layer, forming one or more fin-cut mask trench(es) in the fin-cut mask layer, and removing portions of the gate fill layer and vertical fins not covered by the fin-cut mask layer to form one or more fin trench(es), and two or more vertical fin segments from each of the plurality of vertical fins, having a separation distance, D1, between two vertical fin segments.

Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.

Abstract: A semiconductor device includes a semiconductor substrate having a gate trench including of an upper trench and a lower trench. The upper trench is wider than the lower trench. A gate is embedded in the gate trench. The gate includes an upper portion and a lower portion. A first gate dielectric layer is between the upper portion and a sidewall of the upper trench. The first gate dielectric layer has a first thickness. A second gate dielectric layer is between the lower portion and a sidewall of the lower trench and between the lower portion and a bottom surface of the lower trench. The second gate dielectric layer has a second thickness that is smaller than the first thickness.

Abstract: A method for forming a semiconductor structure is provided. Multiple fins extending along a first direction are formed in a semiconductor substrate. The multiple fins includes a group of active fins, a pair of protection fins sandwiching about the group the active fins, and at least one dummy fin around the pair of protection fins. A fin cut process is performed to remove the at least one dummy fin around the pair of protection fins. After performing the fin cut process, trench isolation structures are formed within the trenches between the multiple fins. The trench isolation structures are subjected to an anneal process. After annealing the trench isolation structures, the pair of protection fins is removed.

Abstract: The present disclosure provides a semiconductor device structure in accordance with some embodiments. In some embodiments, the semiconductor device structure includes a semiconductor substrate of a first semiconductor material and having first recesses. The semiconductor device structure further includes a first gate stack formed on the semiconductor substrate and being adjacent the first recesses. In some examples, a passivation material layer of a second semiconductor material is formed in the first recesses. In some embodiments, first source and drain (S/D) features of a third semiconductor material are formed in the first recesses and are separated from the semiconductor substrate by the passivation material layer. In some cases, the passivation material layer is free of chlorine.

Abstract: Provided herein is a method including fusion bonding a handle wafer to a first side of a device wafer. A hardmask is deposited on a second side of the device wafer, wherein the second side is planar. The hardmask is etched to form a MEMS device pattern and a standoff pattern. Standoffs are formed on the device wafer, wherein the standoffs are defined by the standoff pattern. A eutectic bond metal is deposited on the standoffs, the device wafer, and the hardmask. A first photoresist is deposited and removed, such that the first photoresist covers the standoffs. The eutectic bond metal is etched using the first photoresist. The MEMS device pattern is etched into the device wafer. The first photoresist and the hardmask are removed.

Abstract: A method of self-aligned double patterning is disclosed in the present invention, which includes the step of forming multiple mandrels on a hard mask layer and spacers at two sides of each mandrel, forming a protection layer filling between the spacers, removing the mandrels to expose the hard mask layer, and performing an anisotropic etch process using the spacers and the protection layer as an etch mask to remove a portion of hard mask layer, so that a thickness of hard mask layer exposed between the spacers equals to a thickness of hard mask layer under the protection layer.

Abstract: Methods for forming conductive regions of a metallization network with reduced leakage current and capacitance are described. Aspects of the invention include forming a trench in a dielectric material on the substrate, forming a first liner layer in a first portion of the trench, forming a second liner layer in a second portion of the trench, and forming a conductive material over the second liner layer in the trench.

Abstract: According to an embodiment, a wafer W includes a layer EL to be etched, an organic film OL, an antireflection film AL, and a mask MK1, and a method MT according to an embodiment includes a step of performing an etching process on the antireflection film AL by using the mask MK1 with plasma generated in a processing container 12, in the processing container 12 of a plasma processing apparatus 10 in which the wafer W is accommodated, and the step includes steps ST3a to ST4 of conformally forming a protective film SX on the surface of the mask MK1, and steps ST6a to ST7 of etching the antireflection film AL by removing the antireflection film AL for each atomic layer by using the mask MK1 on which the protective film SX is formed.

Abstract: A method of spacer-defined direct patterning in semiconductor fabrication includes: providing a photoresist structure having a target width of lines; trimming the photoresist structures such that a width of each trimmed photoresist structure is smaller than the target width; depositing an oxide film on the template, thereby entirely covering with the oxide film an exposed top surface of the template and the trimmed photoresist structures; etching the oxide film-covered template to remove an unwanted portion of the oxide film without removing the trimmed photoresist structures so as to form vertical spacers isolated from each other, each spacer substantially maintaining the target width and being constituted by the trimmed photoresist structures and a vertical portion of the oxide film covering sidewalls of the trimmed photoresist structures; and etching the spacer-formed template to transfer a pattern constituted by the spacers to the template.

Abstract: A method of selectively etching a first region R1 made of silicon oxide with respect to a second region R2 made of silicon nitride by performing a plasma processing upon a processing target object is provided. The processing target object has the second region R2 forming a recess; the first region R1 configured to fill the recess; and a mask MK provided on the first region R1. The method includes a first process of generating plasma of a processing gas containing a fluorocarbon gas, and a second process of etching the first region with radicals of fluorocarbon contained in a deposit. In the second process, a high frequency power contributing to the generating of the plasma is applied in a pulse shape, and these processes are repeated.

Abstract: A method of forming a semiconductor structure is disclosed. A fin structure is formed on a substrate and a trench is formed in the fin structure. The trench has a top corner, an upper portion having an upper sidewall and a lower portion having a lower sidewall. A first dielectric layer is then formed on the substrate and fills the lower portion of the trench. After that, a second dielectric layer is formed on the substrate and covers the top corner and the upper sidewall of the trench. The second dielectric layer also covers an upper surface of the first dielectric layer.

Abstract: Methods are provided for manufacturing well-controlled, solid-state nanopores and arrays of well-controlled, solid-state nanopores by a cyclic process including atomic layer deposition (ALD), or chemical vapor deposition (CVD), and etching. One or more features are formed in a thin film deposited on a topside of a substrate. A dielectric material is deposited over the substrate having the one or more features in the thin film. An etching process is then used to etch a portion of the dielectric material deposited over the substrate having the one or more features in the thin film. The dielectric material deposition and etching processes are optionally repeated to reduce the size of the features until a well-controlled nanopore is formed through the thin film on the substrate.