Abstract: An inductor element is formed in a multiple layer lead structure including a lead, an insulative layer that insulates leads above and below, and a via provided in the insulative layer and connecting leads above and below wherein lead layers are multiply laminated layers, characterized in that: at least a portion of at least a pair of vertically adjacent leads are coiled leads; the coiled leads are connected in series, wherein current directions of vertically adjacent coiled leads are the same by a via provided on an end portion thereof, and form a serial inductance; and an inter-lead capacitance of the vertically adjacent coiled leads is larger than an inter-lead capacitance between other coiled leads formed in the same lead layer.
Abstract: A differential amplifier has first and second input terminals (T1, T2), an output terminal, a differential stage connected to the first and second input terminals, and an amplification stage having an input terminal thereof connected to an output terminal of the differential stage and an output terminal thereof connected to the output terminal. The differential stage includes a first differential pair with one of an input pair thereof connected to the first input terminal (T1) and the other connected to the output terminal, a second differential pair with one of an input pair thereof connected to the first input terminal (T1) and the other connected to the second input terminal (T2), a first current source for supplying current to the first differential pair, a second current source for supplying current to the second differential pair, and a load circuit connected to the output pairs of the first and second differential pairs.
October 27, 2004
Date of Patent:
August 20, 2013
NEC Corporation, NEC Electronics Corporation
Abstract: A semiconductor memory device includes a memory cell array divided into a plurality of subarrays arranged in matrix form, the plurality of subarrays making up a plurality of subarray columns, an address pad column formed outside the memory cell array, the address pad column comprising a plurality of address pads that are arranged to be substantially parallel to the subarray columns, a data I/O pad column formed in a middle section of the memory cell array, the data I/O pad column comprising data I/O pads that are arranged to be substantially parallel to the subarray columns, an address input circuit arranged in the middle section of the memory cell array, and a pad input address line formed in a direction substantially perpendicular to the subarray columns on the memory cell array, the pad input address line directly connecting the address pad and the address input circuit.
October 23, 2012
February 21, 2013
RENESAS ELECTRONICS CORPORATION, NEC ELECTRONICS CORPORATION
NEC ELECTRONICS CORPORATION, RENESAS ELECTRONICS CORPORATION
Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.
Abstract: A semiconductor integrated circuit design apparatus (100) includes a delay analysis unit (102) which analyzes a static delay in respective paths of a semiconductor integrated circuit, a noise generation unit (104) which generates noise information based on a predetermined noise definition, a voltage fluctuation level analysis unit (106) which analyzes a voltage fluctuation level of the semiconductor integrated circuit when the noise is applied based on the noise information, and a timing verification unit (108) which makes the delay analysis unit (102) analyze the static delay based on the analyzed voltage fluctuation level, to verify timing for operation of the semiconductor integrated circuit based on a result of the static delay analysis, wherein the noise generation unit (104) generates noise information on noise applied at predetermined application timing, and the timing verification unit (108) verifies the timing for each noise applied with the predetermined application timing.
April 21, 2010
April 19, 2012
NEC ELECTRONICS CORPORATION, NEC CORPORATION
Abstract: A heat sink 109 is configured by a plate component having a combined structure composed of a recess and a projection formed thereon, wherein the recess is formed by allowing a part of the plate component to be set back from the surface level of the residual region, and the projection is formed on one surface of the plate component with the progress of formation of the recess, so as to be built up above the level of the residual region of the one surface.
Abstract: A semiconductor device 1 includes a semiconductor chip 10 (first semiconductor chip), a semiconductor chip 20 (second semiconductor chip) and a seal ring 30. The semiconductor chip 20 is provided on a surface S1 of the semiconductor chip 10 so as to be spaced apart from the semiconductor chip 10 with a predetermined spacing therebetween. A seal ring 30 is interposed between the semiconductor chip 10 and the semiconductor chip 20. An internal region, which is an inner region of the seal ring 30, and an external region, which is an outer region of the seal ring 30, are provided between the semiconductor chip 10 and the semiconductor chip 20.
Abstract: A multiprocessor system includes a memory that stores a program; an address notification register; a first processor; and a second processor, in which the first processor stores address information indicating an address from which the program is executed in the address notification register, when the first processor notifies an interrupt request to the second processor and causes the second processor to execute the program, and the second processor obtains the interrupt request notified from the first processor and the address information stored in the address notification register, and starts to execute the program from the address indicated by the obtained address information.
Abstract: A main object of the invention is to provide a reflective mask for EUV lithography, which may detect an alignment mark by transmission. The invention achieves the object by providing a reflective mask comprising a substrate, a multilayer formed on one side of the substrate, an intermediate layer formed on the multilayer, an absorber formed in pattern on the substrate on which the multilayer and the intermediate layer are formed, and a conductive layer formed on the other side of the substrate, wherein the pattern of the absorber constitutes a circuit pattern and an alignment mark, and in an alignment region where the alignment mark is provided, the other side of the substrate is exposed.
March 2, 2009
Date of Patent:
May 24, 2011
Dai Nippon Printing Co., Ltd., NEC Electronics Corporation
Abstract: Two interconnect layers are electrically connected while reducing the number of manufacturing steps. A contact plug 9c which is formed into a beaded shape in a layer underlying two interconnects 11C and 11D and which also electrically connects the two interconnects 11C and 11D is included. The two interconnects 11C and 11D are separated to each other and are formed in a same layer. The contact plug 9c is simultaneously formed with a contact plug 9b to be connected to an interconnect 4b and a contact plug 9a to be connected to a source/drain region 6.
Abstract: Method of cleaning a plasma etching apparatus capable of suppressing variation in line width among wafers in a single lot, and improving throughput in the cleaning process, includes steps of supplying a cleaning gas into a chamber of a plasma etching apparatus; igniting a plasma of the cleaning gas in the chamber; and allowing plasma cleaning to proceed in the chamber, by bringing the cleaning gas in plasma form into contact with a deposit adhered on the inner wall of the chamber so as to etch off the deposit, wherein in the step of plasma cleaning in the chamber, intensity of plasma emission ascribable to the deposit adhered on the inner wall of the chamber is detected in a time-dependent manner, and the plasma cleaning in the chamber is terminated based on changes in the intensity of the plasma emission.
Abstract: A semiconductor device includes a semiconductor chip, an electrode pad provided in the semiconductor chip, in which the electrode pad includes Al as a major constituent and further includes Cu, a coupling member coupled to the electrode pad, in which the coupling member primarily includes Cu, a plurality of layers of Cu and Al alloys formed between the electrode pad and the coupling member, and an encapsulating resin that includes a halogen of less than or equal to 1000 ppm, in which the encapsulating resin encapsulates the semiconductor chip, the electrode pad, and the coupling member. The plurality of layers of Cu and Al alloys includes a CuAl2 layer formed on the electrode pad, a CuAl layer formed on the CuAl2 layer, and a layer including one of Cu9Al4 and Cu3Al2 formed on the CuAl layer.
Abstract: A semiconductor memory device to an exemplary aspect of the present invention includes a plurality of memory cells, a plurality of word lines, a plurality of bit line pairs, a plurality of column selectors, a common signal line pair including one common line commonly connected to one of each of the plurality of bit line pairs, and the other common line commonly connected to the other of each of the plurality of bit line pairs, a sense amplifier amplifying the potential difference of the common signal line pair, and a plurality of capacitance adding circuits that balance with parasitic capacitances of the column selectors which are not selected, the capacitance adding circuits being provided respectively between the one of each of the bit line pairs and the other common line and between the other of each of the bit line pairs and the one common line.
Abstract: A level shift circuit includes a first circuit connected between a first power supply terminal (PST) and an output terminal (OT) of the level shift circuit to set OT to a first voltage (V1) when conducting, a second circuit connected between a second PST and OT to set OT to the second voltage (V2) when conducting, and a third circuit that receives an input signal and a feedback signal from OT so that, when OT=V2 and input=a third voltage (V3), the first circuit conducts, and when OT=V1, the first circuit is made nonconductive irrespective of the value of the input signal. The second circuit is made conductive and nonconductive, when the input=a fourth voltage (V4) and V3, respectively. A high/low relationship of V1, V2=that of V3, V4. The input between V3, V4 has a lower amplitude than the output signal between V1, V2.
Abstract: A reference current or voltage generation circuit which forms a self feedback circuit with a plurality of transistors and generates a reference current or a reference voltage, the reference current or voltage generation circuit including a normally-on type transistor that has a gate connected to a first power supply and is connected between a node and a second power supply. Moreover, a voltage of the node is substantially equal to a voltage of the first power supply when the reference current or voltage generation circuit does not operate, and the voltage of the node fluctuates from the voltage of the first power supply toward a voltage of the second power supply by a predetermined value or more when the reference current or voltage generation circuit operates.
Abstract: A semiconductor device including a plurality of memory cells arranged in a matrix pattern, a write amplifier which writes write data to the memory cell in synchronization with a clock, a sense amplifier which reads out the write data written in the memory cell in synchronization with the clock, a plurality of column select switches which connect the plurality of the memory cells with the sense amplifier and the write amplifier, a column address decoder which makes the column select switch corresponding to one column among the plurality of the memory cells a conductive state based on a column address, a row address decoder which activates the memory cell of one row based on a row address, and a test write circuit which writes data corresponding to a logical level of a test signal to the memory cell based on a test mode signal.
Abstract: A semiconductor device capable of dissipating heat, which has been produced in an ESD protection element, to the exterior of the device rapidly and efficiently includes an ESD protection element having a drain region, a source region and a gate electrode, and a thermal diffusion portion. The thermal diffusion portion, which has been formed on the drain region, has a metal layer electrically connected to a pad, and contacts connecting the drain region and metal layer. The metal layer has a first wiring trace extending along the gate electrode, and second wiring traces intersecting the first wiring trace perpendicularly. The contacts are connected to intersections between the first wiring trace and the second wiring traces. Heat that has been produced at a pn-junction of the ESD protection element and transferred through a contact is diffused simultaneously in three directions through the first wiring trace and second wiring trace in the metal layer and is released into the pad.
Abstract: An exemplary embodiment of the present invention is an autofocus method that includes moving a focus lens according to an image signal generated from an image of a subject formed by an imaging optical system with a focus lens, obtaining a focus contrast of each of multiple image signals generated in a case of moving a position of the focus lens; and determining a moving direction of the focus lens according to the multiple obtained focus contrasts in response to a focus instruction.
Abstract: A semiconductor storage device, in which successive reading and successive writing of data having a predetermined length from and to a memory cell specified by a certain address are performed, includes a plurality of memory cells, address input terminals through which the address is input, data output terminals through which read data having the predetermined length is output, and data input terminals through which write data having the predetermine length is input. Part of the address input terminals are also used as the data output terminals. In this way, the operation of successive reading and successive writing performed in succession at the same address can be made faster without increasing the number of terminals.
Abstract: A push-pull amplifier including first to third current paths. The first current path includes first transistor allowing first current to flow through the first current path according to input signal. The second current path includes second transistor allowing second current having opposite phase to the first current to flow through the second current path according to the first current; first resistor; and third transistor connected to one end of the first resistor and having control terminal connected to the other end of the first resistor. The third current path includes output terminal; fourth transistor allowing current having the same phase as the first current to flow through the third current path according to the input signal; and fifth transistor allowing current having the same phase as the second current to flow through the third current path according to voltage of first node between the first resistor and the third transistor.