Etching Insulating Layer By Chemical Or Physical Means (epo) Patents (Class 257/E21.249)
  • Patent number: 10121879
    Abstract: Techniques for forming an odd number of fins by SIT are provided. In one aspect, a method of forming an odd number of fins by SIT includes the steps of: forming a pad layer on a substrate; forming at least one mandrel on the pad layer; forming a first pair of spacers on opposite sides of the mandrel; forming a second pair of spacers on a side of the first pair of spacers opposite the mandrel; removing the first pair of spacers selective to the mandrel and the second pair of spacers; and patterning the odd number of fins in the substrate using a combination of the mandrel and the second pair of spacers as fin masks. A method of forming a finFET device and a fin device structure are also provided.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: November 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao
  • Patent number: 9679815
    Abstract: A semiconductor device fabrication method includes sequentially forming a hard mask layer and a sacrificial layer on a substrate, forming an upper mandrel which includes first to third upper sub-mandrels on the sacrificial layer, the first to third upper sub-mandrels extending in a first direction and being spaced apart from each other in a second direction, a width of the first upper sub-mandrel being smaller than widths of the second and third upper sub-mandrels, forming first spacers on sidewalls of each of the upper sub-mandrels, removing the upper mandrel, etching the sacrificial layer using the first spacers as etching masks to form a lower mandrel that includes a plurality of sub-mandrels, forming second spacers on sidewalls of the lower sub-mandrels, removing the lower mandrel, patterning the hard mask layer and the substrate using the second spacers as etching masks to form first to tenth fins which extend alongside each other in the first direction and are spaced apart from each other in the second
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: June 13, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Hun Lee, Sunhom Steve Paak
  • Patent number: 9673049
    Abstract: A manufacturing method of a patterned structure of a semiconductor device includes following steps. A plurality of support features are formed on a substrate. A first conformal spacer layer is formed on the support features and a surface of the substrate, a second conformal spacer layer is formed on the first conformal spacer layer, and a covering layer is formed on the second conformal spacer layer. A gap between the support features is filled with the first conformal spacer layer, the second conformal spacer layer, and the covering layer. A first process is performed to remove a part of the covering layer, the second conformal spacer layer, and the first conformal spacer layer. A second process is performed to remove the support features or the first conformal spacer layer between the support feature and the second conformal spacer layer to expose a part of the surface of the substrate.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: June 6, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 9627359
    Abstract: Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first conductive layer; a large-diameter concave portion having, on a main side of a substrate, an opening sized to overlap the first and second conductive layers, with the first conductive layer exposed in part of the bottom of the large-diameter concave portion; a small-diameter concave portion extended from the large-diameter concave portion and formed by digging into the bottom of the large-diameter concave portion, with the second conductive layer exposed at the bottom of the small-diameter concave portion; and a conductive member provided in a connection hole made up of the large- and small-diameter concave portions to connect the first and second conductive layers.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: April 18, 2017
    Assignee: Sony Corporation
    Inventor: Masanaga Fukasawa
  • Patent number: 9620452
    Abstract: An apparatus including a conductive stack structure includes an Mx layer interconnect on an Mx layer and extending in a first direction on a first track, an My layer interconnect on an My layer in which the My layer is a lower layer than the Mx layer, a first via stack coupled between the Mx layer interconnect and the My layer interconnect, a second via stack coupled between the Mx layer interconnect and the My layer interconnect, a second Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track, and a third Mx layer interconnect extending in the first direction on a track immediately adjacent to the first track. The Mx layer interconnect is between the second Mx layer interconnect and the third Mx layer interconnect. The second Mx layer interconnect and the third Mx layer interconnect are uncoupled to each other.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: April 11, 2017
    Assignee: QUALCOMM INCORPORATED
    Inventors: Xiongfei Meng, Joon Hyung Chung, Yuancheng Christopher Pan
  • Patent number: 9006100
    Abstract: An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: April 14, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, Yuansheng Ma, Irene Lin, Jason Stephens, Yunfei Deng, Yuan Lei, Jongwook Kye, Rod Augur, Shibly Ahmed, Subramani Kengeri, Suresh Venkatesan
  • Patent number: 8999859
    Abstract: Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by intermittent delivery of dopant species to the film between the cycles of adsorption and reaction.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: April 7, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Shankar Swaminathan, Jon Henri, Dennis M. Hausmann, Pramod Subramonium, Mandyam Sriram, Vishwanathan Rangarajan, Kirthi K. Kattige, Bart K. van Schravendijk, Andrew J. McKerrow
  • Patent number: 8980751
    Abstract: Polymerized material on a substrate may be removed by exposure to vacuum ultraviolet (VUV) radiation from an energy source within a gaseous atmosphere of a controlled composition. Following such removal, additional etching techniques are also described for nano-imprinting.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: March 17, 2015
    Assignees: Canon Nanotechnologies, Inc., Molecular Imprints, Inc.
    Inventors: Gerard M. Schmid, Michael N. Miller, Byung-Jin Choi, Douglas J. Resnick, Sidlgata V. Sreenivasan, Frank Y. Xu, Darren D. Donaldson
  • Patent number: 8980752
    Abstract: A method of forming a plurality of spaced features includes forming sacrificial hardmask material over underlying material. The sacrificial hardmask material has at least two layers of different composition. Portions of the sacrificial hardmask material are removed to form a mask over the underlying material. Individual features of the mask have at least two layers of different composition, with one of the layers of each of the individual features having a tensile intrinsic stress of at least 400.0 MPa. The individual features have a total tensile intrinsic stress greater than 0.0 MPa. The mask is used while etching into the underlying material to form a plurality of spaced features comprising the underlying material. Other implementations are disclosed.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: March 17, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Farrell Good, Baosuo Zhou, Xiaolong Fang, Fatma Arzum Simsek-Ege
  • Patent number: 8981501
    Abstract: A method of forming a semiconductor device is disclosed. Provided is a substrate having at least one MOS device, at least one metal interconnection and at least one MOS device formed on a first surface thereof. A first anisotropic etching process is performed to remove a portion of the substrate from a second surface of the substrate and thereby form a plurality of vias in the substrate, wherein the second surface is opposite to the first surface. A second anisotropic etching process is performed to remove another portion of the substrate from the second surface of the substrate and thereby form a cavity in the substrate, wherein the remaining vias are located below the cavity. An isotropic etching process is performed to the cavity and the remaining vias.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: March 17, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Meng-Jia Lin, Chang-Sheng Hsu, Kuo-Hsiung Huang, Wei-Hua Fang, Shou-Wei Hsieh, Te-Yuan Wu, Chia-Huei Lin
  • Patent number: 8969926
    Abstract: An embodiment of a vertical power device includes a III-nitride substrate, a drift region coupled to the III-nitride substrate and comprising a III-nitride material of a first conductivity type, and a channel region coupled to the drift region and comprising a III-nitride material of the first conductivity type. The vertical power device also includes a source region coupled to the channel region and comprising a III-nitride material of the first conductivity type, and a gate region coupled to the channel region. The gate region includes a III-nitride material of a second conductivity type. The vertical power device further includes a source-coupled region coupled to the drift region and electrically connected with the source region. The source-coupled region includes a III-nitride material of the second conductivity type.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: March 3, 2015
    Assignee: Avogy, Inc.
    Inventor: Donald R. Disney
  • Patent number: 8962452
    Abstract: In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: February 24, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Gordon M. Grivna
  • Patent number: 8952512
    Abstract: A wafer-level package structure of a light emitting diode and a manufacturing method thereof are provided in the present invention. The wafer-level package structure of a light emitting diode includes a die, a first insulating layer, at least two wires, bumps, an annular second insulating layer on the wires and the insulating layer, the annular second insulating layer surrounding an area between the bumps and there being spaces arranged between the second insulating layer and the bumps; a light reflecting cup on the second insulating layer; at least two discrete lead areas and leads in the lead areas. The technical solution of the invention reduces the area required for the substrate; and the electrodes can be extracted in the subsequent structure of the package without gold wiring to thereby further reduce the volume of the package.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: February 10, 2015
    Assignee: China Wafer Level CSP Ltd.
    Inventors: Junjie Li, Wenbin Wang, Qiuhong Zou, Guoqing Yu, Wei Wang
  • Patent number: 8951833
    Abstract: A method for forming large substantially defect-free void areas on a semiconductor integrated circuit chip includes processing the chip through the passivation level processing operations then forming one or more openings in a designated blank area of the integrated circuit chip in a separate dedicated etching operation. The one or more openings may constitute 5-10% or more of the total area of the semiconductor chip. The void areas are deep trench openings that extend through the passivation layer and through all of the other material layers in the blank area exposing the substrate surface in one embodiment and through all material layers except for a field oxide layer formed directly on the substrate in another embodiment.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: February 10, 2015
    Assignee: WaferTech, LLC
    Inventor: Kun-Yi Liu
  • Patent number: 8932960
    Abstract: Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: January 13, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Luan C. Tran
  • Patent number: 8916470
    Abstract: The present invention relates to a method of manufacturing sidewall spacers on a memory device. The method comprises forming sidewall spacers on a memory device having a memory array region and at least one peripheral circuit region by forming a first sidewall spacer adjacent to a word line in the memory array region and a second sidewall spacer adjacent to a transistor in the peripheral circuit region. The first sidewall spacer has a first thickness and the second sidewall spacer has a second thickness, wherein the second thickness is greater than the first thickness.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: December 23, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Durga Panda, Jaydip Guha, Robert Kerr
  • Patent number: 8895445
    Abstract: A method for forming vias and trenches for an interconnect structure on a substrate includes exposing via pitch reduction patterns in a photoresist layer, developing the patterns to remove the via pitch reduction patterns, etching the photoresist layer partially using a polymer gas to reshape the pattern into small via shapes, and etching the remaining photoresist layer to extend the reshaped pattern. The reshaped small via shape patterns have a smaller pitch than the via pitch reduction patterns in a long direction. For via pitch reduction patterns having two vias each, the pattern has a peanut-shape. During the reshaping etch operation, the polymer gas deposits more in a pinched-in middle section while allowing downward etch in unpinched sections.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: November 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Kuo Hsieh, Marowen Ng, Ming-Chung Liang, Hsin-Yi Tsai
  • Patent number: 8890214
    Abstract: The present invention relates to a method of manufacturing sidewall spacers on a memory device. The method comprises forming sidewall spacers on a memory device having a memory array region and at least one peripheral circuit region by forming a first sidewall spacer adjacent to a word line in the memory array region and a second sidewall spacer adjacent to a transistor in the peripheral circuit region. The first sidewall spacer has a first thickness and the second sidewall spacer has a second thickness, wherein the second thickness is greater than the first thickness.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: November 18, 2014
    Assignee: Nan Ya Technology Corporation
    Inventors: Panda Durga, Jaydip Guha, Robert Kerr
  • Patent number: 8883646
    Abstract: The present disclosure is directed to a process for the fabrication of a semiconductor device. In some embodiments the semiconductor device comprises a patterned surface. The pattern can be formed from a self-assembled monolayer. The disclosed process provides self-assembled monolayers which can be deposited quickly, thereby increasing production throughput and decreasing cost, as well as providing a pattern having substantially uniform shape.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee, Chien-Hua Huang
  • Patent number: 8883601
    Abstract: A semiconductor device has memory cell portions and compensation capacitance portions on a single substrate. The memory cell portion and the compensation capacitance portion have mutually different planar surface areas. The memory cell portion and the compensation capacitance portion include capacitance plate electrodes of the same structure. The capacitance plate electrode has a laminated structure including a boron-doped silicon germanium film and a metal film.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: November 11, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Nobuyuki Sako
  • Patent number: 8884377
    Abstract: In one embodiment, first and second pattern structures respectively include first and second conductive line patterns and first and second hard masks sequentially stacked, and at least portions thereof extends in a first direction. The insulation layer patterns contact end portions of the first and second pattern structures. The first pattern structure and a first insulation layer pattern of the insulation layer patterns form a first closed curve shape in plan view, and the second pattern structure and a second insulation layer pattern of the insulation layer patterns form a second closed curve shape in plan view. The insulating interlayer covers upper portions of the first and second pattern structures and the insulation layer patterns, a first air gap between the first and second pattern structures, and a second air gap between the insulation layer patterns.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sok-Won Lee, Joon-Hee Lee, Jung-Dal Choi, Seong-Min Jo
  • Patent number: 8877650
    Abstract: Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: November 4, 2014
    Assignees: International Business Machines Corporation, Infineon Technologies AG
    Inventors: O Seo Park, Wai-Kin Li
  • Patent number: 8853090
    Abstract: A method for fabricating a through-silicon via comprises the following steps. Provide a substrate. Form a through silicon hole in the substrate having a diameter of at least 1 ?m and a depth of at least 5 ?m. Perform a first chemical vapor deposition process with a first etching/deposition ratio to form a dielectric layer lining the bottom and sidewall of the through silicon hole and the top surface of the substrate. Perform a shape redressing treatment with a second etching/deposition ratio to change the profile of the dielectric layer. Repeat the first chemical vapor deposition process and the shape redressing treatment at least once until the thickness of the dielectric layer reaches to a predetermined value.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 7, 2014
    Assignee: IPEnval Consultant Inc.
    Inventors: Chao-Yuan Huang, Yueh-Feng Ho, Ming-Sheng Yang, Hwi-Huang Chen
  • Patent number: 8828879
    Abstract: There is provided a lithographic resist underlayer film-forming composition for forming a resist underlayer film which can be used as a hard mask. A lithographic resist underlayer film-forming composition including a silane compound having sulfonamide group, wherein the silane compound having sulfonamide group is a hydrolyzable organosilane having a sulfonamide group in the molecule, a hydrolyzate thereof, or a hydrolytic condensation product thereof. The composition including a silane compound having sulfonamide group and a silane compound lacking a sulfonamide group, wherein the silane compound having sulfonamide group is present within the silane compounds overall in a proportion of less than 1 mol %, for example 0.1 to 0.95 mol %.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: September 9, 2014
    Assignee: Nissan Chemical Industries, Ltd.
    Inventors: Yuta Kanno, Makoto Nakajima, Wataru Shibayama
  • Patent number: 8809132
    Abstract: A capping layer may be deposited over the active channel of a thin film transistor (TFT) in order to protect the active channel from contamination. The capping layer may affect the performance of the TFT. If the capping layer contains too much hydrogen, nitrogen, or oxygen, the threshold voltage, sub threshold slope, and mobility of the TFT may be negatively impacted. By controlling the ratio of the flow rates of the nitrogen, oxygen, and hydrogen containing gases, the performance of the TFT may be optimized. Additionally, the power density, capping layer deposition pressure, and the temperature may also be controlled to optimize the TFT performance.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: August 19, 2014
    Assignee: Applied Materials, Inc.
    Inventor: Yan Ye
  • Patent number: 8802551
    Abstract: A semiconductor device is fabricated by forming first holes arranged along a first direction on an etch-target layer, forming dielectric patterns in the first holes, conformally forming a barrier layer on the dielectric patterns, forming a sacrificial layer on the barrier layer to define a first void, partially removing the sacrificial layer to expose the first void, anisotropically etching the barrier layer to form second holes below the first void, and etching portions of the etch-target layer located below the first and second holes to form contact holes. The first void may be formed on a first gap region confined by at least three of the dielectric patterns disposed adjacent to each other, and the sacrificial layer may include a material having a low conformality.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: August 12, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: JungWoo Seo, JinSeo Choi, KyoungRyul Yoon
  • Patent number: 8786027
    Abstract: In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: July 22, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Uwe Griebenow, Jan Hoentschel, Thilo Scheiper, Sven Beyer
  • Patent number: 8778805
    Abstract: In a method for manufacturing a semiconductor device, an opening formed in a semiconductor substrate by using a mask and covering an inner side face of the opening with a sidewall protective film. The mask is removed, while a part of the sidewall protective film remains.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: July 15, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Seiya Fujii
  • Patent number: 8742544
    Abstract: A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof. Note that the oxide region of the source electrode and the drain electrode is preferably formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: June 3, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 8741396
    Abstract: An amorphous carbon film, which has excellent etching resistance and is capable of reducing reflectance when a resist film is exposed to light, is form. A method for manufacturing a semiconductor device includes forming an object film to be etched on a wafer, supplying a process gas containing a CO gas and an N2 gas into a processing container, forming an amorphous carbon nitride film from the supplied CO gas and N2 gas, forming a silicon oxide film on the amorphous carbon nitride film, forming an ArF resist film on the silicon oxide film, patterning the ArF resist film, etching the silicon oxide film by using the ArF resist film as a mask, etching the amorphous carbon nitride film by using the silicon oxide film as a mask, and etching the object film to be etched by using the amorphous carbon nitride film as a mask.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: June 3, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Hiraku Ishikawa, Eiichi Nishimura
  • Patent number: 8741763
    Abstract: An approach for providing layout designs with via routing structures is disclosed. Embodiments include: providing a gate structure and a diffusion contact on a substrate; providing a gate contact on the gate structure; providing a metal routing structure that does not overlie a portion of the gate contact, the diffusion contact, or a combination thereof; and providing a via routing structure over the portion and under a part of the metal routing structure to couple the gate contact, the diffusion contact, or a combination thereof to the metal routing structure.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: June 3, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yuansheng Ma, Jongwook Kye, Harry Levinson, Hidekazu Yoshida, Mahbub Rashed
  • Patent number: 8728945
    Abstract: A method of uniformly shrinking hole and space geometries by forming sidewalls of an ALD film deposited at low temperature on a photolithographic pattern.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: May 20, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Steven Alan Lytle
  • Patent number: 8723340
    Abstract: The present invention relates to a process for the production of solar cells comprising a selective emitter using an improved etching-paste composition which has significantly improved selectivity for silicon layers.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: May 13, 2014
    Assignee: Merck Patent GmbH
    Inventors: Werner Stockum, Oliver Doll, Ingo Koehler
  • Publication number: 20140127907
    Abstract: Methods of forming a semiconductor device structure and sulfur dioxide etch chemistries. The methods and chemistries, which may be plasma chemistries, include use of sulfur dioxide and a halogen-based compound to form a trimmed pattern of a patterning material, such as a resist material, at a critical dimension with low feature width roughness, with low space width roughness, without excessive height loss, and without substantial irregularities in the elevational profile, as compared to trimmed features formed using conventional chemistries and trimming methods.
    Type: Application
    Filed: November 8, 2012
    Publication date: May 8, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Guangjun Yang
  • Publication number: 20140124840
    Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.
    Type: Application
    Filed: November 7, 2012
    Publication date: May 8, 2014
    Applicants: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Ali Khakifirooz, Thomas N. Adam, Kangguo Cheng, Shom Ponoth, Alexander Reznicek, Raghavasimhan Sreenivasan, Xiuyu Cai, Ruilong Xie
  • Patent number: 8716133
    Abstract: A three photomask image transfer method. The method includes using a first photomask, defining a set of mandrels on a hardmask layer on a substrate; forming sidewall spacers on sidewalls of the mandrels, the sidewall spacers spaced apart; removing the set of mandrels; using a second photomask, removing regions of the sidewall spacers forming trimmed sidewall spacers and defining a pattern of first features; forming a pattern transfer layer on the trimmed sidewall spacers and the hardmask layer not covered by the trimmed sidewall spacers; using a third photomask, defining a pattern of second features in the transfer layer, at least one of the second features abutting at least one feature of the pattern of first features; and simultaneously transferring the pattern of first features and the pattern of second features into the hardmask layer thereby forming a patterned hardmask layer.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shyng-Tsong Chen, Ryan O. Jung, Neal V. Lafferty, Yunpeng Yin
  • Publication number: 20140099792
    Abstract: Fin-defining spacers are formed on an array of mandrel structure. Mask material portions can be directionally deposited on fin-defining spacers located on one side of each mandrel structure, while not deposited on the other side. A photoresist layer is subsequently applied and patterned to form an opening, of which the overlay tolerance increases by a pitch of fin-defining spacers due to the mask material portions. Alternately, a conformal silicon oxide layer can be deposited on fin-defining spacers and structure-damaging ion implantation is performed only on fin-defining spacers located on one side of each mandrel structure. A photoresist layer is subsequently applied and patterned to form an opening, from which a damaged silicon oxide portion and an underlying fin-defining spacer are removed, while undamaged silicon oxide portions are not removed. An array of semiconductor fins including a vacancy can be formed by transferring the pattern into a semiconductor layer.
    Type: Application
    Filed: October 10, 2012
    Publication date: April 10, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
  • Publication number: 20140070292
    Abstract: A method of forming a deep trench capacitor in a semiconductor-on-insulator substrate is provided. The method may include providing a pad layer positioned above a bulk substrate, etching a deep trench into the pad layer and the bulk substrate extending from a top surface of the pad layer down to a location within the bulk substrate, and doping a portion of the bulk substrate to form a buried plate. The method further including depositing a node dielectric, an inner electrode, and a dielectric cap substantially filling the deep trench, the node dielectric being located between the buried plate and the inner electrode, the dielectric cap being located at a top of the deep trench, removing the pad layer, growing an insulator layer on top of the bulk substrate, and growing a semiconductor-on-insulator layer on top of the insulator layer.
    Type: Application
    Filed: September 7, 2012
    Publication date: March 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang
  • Publication number: 20140070373
    Abstract: A first dielectric layer is formed over a substrate. A second dielectric layer is formed over the first dielectric layer. A first opening is formed in the second dielectric layer. A second opening is formed in the first dielectric layer.
    Type: Application
    Filed: September 10, 2012
    Publication date: March 13, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Nien-Yu Tsai, Wei Ming Chen
  • Publication number: 20140051248
    Abstract: The methods involve selectively depositing a resist containing a solid hydrogenated rosin resin and a liquid hydrogenated rosin resin ester as a mixture on a semiconductor followed by etching uncoated portions of the semiconductor and simultaneously inhibiting undercutting of the resist. The etched portions may then be metallized to form current tracks.
    Type: Application
    Filed: August 16, 2012
    Publication date: February 20, 2014
    Applicant: Rohm and Haas Electronic Materials LLC
    Inventors: Hua DONG, Robert K. Barr
  • Patent number: 8647981
    Abstract: Some embodiments include methods of forming a pattern. First lines are formed over a first material, and second lines are formed over the first lines. The first and second lines form a crosshatch pattern. The first openings are extended through the first material. Portions of the first lines that are not covered by the second lines are removed to pattern the first lines into segments. The second lines are removed to uncover the segments. Masking material is formed between the segments. The segments are removed to form second openings that extend through the masking material to the first material. The second openings are extended through the first material. The masking material is removed to leave a patterned mask comprising the first material having the first and second openings therein. In some embodiments, spacers may be formed along the first and second lines to narrow the openings in the crosshatch pattern.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: February 11, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Vishal Sipani
  • Publication number: 20140038402
    Abstract: A method for fabricating a dual-workfunction FinFET structure includes depositing a first workfunction material in a layer in a plurality of trenches of the FinFET structure, depositing a low-resistance material layer over the first workfunction material layer, and etching the low-resistance material layer and the first workfunction material layer from a portion of the FinFET structure. The method further includes depositing a second workfunction material in a layer in a plurality of trenches of the portion and depositing a stress material layer over the second workfunction material layer.
    Type: Application
    Filed: July 31, 2012
    Publication date: February 6, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Andy C. Wei, Bin Yang, Francis M. Tambwe
  • Publication number: 20140017894
    Abstract: Methods of manufacturing semiconductor devices are disclosed. In one embodiment, a material layer is formed over a workpiece. The workpiece includes a first portion, a second portion, and a hard mask disposed between the first portion and the second portion. The material layer is patterned, and first spacers are formed on sidewalls of the patterned material layer. The patterned material layer is removed, and the second portion of the workpiece is patterned using the first spacers as an etch mask. The first spacers are removed, and second spacers are formed on sidewalls of the patterned second portion of the workpiece. The patterned second portion of the workpiece is removed, and the hard mask of the workpiece is patterned using the second spacers as an etch mask. The first portion of the workpiece is patterned using the hard mask as an etch mask.
    Type: Application
    Filed: July 11, 2012
    Publication date: January 16, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hsiung Tsai, Chung-Ju Lee, Hsin-Chieh Yao, Tien-I Bao
  • Patent number: 8629052
    Abstract: Semiconductor devices and methods of forming semiconductor devices are provided in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using double patterning.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: January 14, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-ju Park, Jae-ho Min, Myeong-cheol Kim, Dong-chan Kim, Jae-hwang Sim
  • Publication number: 20140011364
    Abstract: A method of forming a pattern on a substrate includes forming longitudinally elongated first lines and first sidewall spacers longitudinally along opposite sides of the first lines elevationally over an underlying substrate. Longitudinally elongated second lines and second sidewall spacers are formed longitudinally along opposite sides of the second lines. The second lines and the second sidewall spacers cross elevationally over the first lines and the first sidewall spacers. The second sidewall spacers are removed from crossing over the first lines. The first and second lines are removed in forming a pattern comprising portions of the first and second sidewall spacers over the underlying substrate. Other methods are disclosed.
    Type: Application
    Filed: July 6, 2012
    Publication date: January 9, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Vishal Sipani, Anton J. deVilliers
  • Patent number: 8609544
    Abstract: A method for fabricating a semiconductor device, comprising forming a first photoresist pattern having a hole on a first layer, forming a surface curing layer in the hole and curing the first photoresist pattern on an inner sidewall of the hole to form a first curing pattern, removing the surface curing layer, forming a second photoresist pattern in the hole and curing the second photoresist pattern that contacts with the first curing pattern to form a second curing pattern, removing the first and second photoresist patterns, and etching the first layer using the first and second curing patterns as an etch barrier.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: December 17, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung Koo Lee
  • Patent number: 8609480
    Abstract: One illustrative method disclosed herein includes performing at least one etching process on a semiconducting substrate to form a plurality of trenches and a plurality of fins for the FinFET device in the substrate, forming a first layer of insulating material in the trenches, wherein an upper surface of the first layer of insulating material is below an upper surface of the substrate, forming an isolation layer within the trenches above the first layer of insulating material, wherein the isolation layer has an upper surface that is below the upper surface of the substrate, forming a second layer of insulating material above the isolation layer, wherein the second layer of insulating material has an upper surface that is below the upper surface of the substrate, and forming a gate electrode structure above the second layer of insulating material.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: December 17, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Ruilong Xie
  • Publication number: 20130323931
    Abstract: A method of manufacturing is disclosed. An exemplary method includes providing a substrate and forming one or more layers over the substrate. The method further includes forming a surface layer over the one or more layers. The method further includes performing a patterning process on the surface layer thereby forming a pattern on the surface layer. The method further includes performing a cleaning process using a cleaning solution to clean a top surface of the substrate. The cleaning solution includes tetra methyl ammonium hydroxide (TMAH), hydrogen peroxide (H2O2) and water (H2O).
    Type: Application
    Filed: June 1, 2012
    Publication date: December 5, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Lun Lu, Kuan-Wen Lin, Ching-Wei Shen, Ting-Hao Hsu, Sheng-Chi Chin
  • Patent number: 8598038
    Abstract: A process for producing two interleaved patterns on a substrate uses photolithography and etching to produce, on the substrate, a first pattern of first material protruding regions separated by recessed regions. A non-conformal deposition of a second material on the first pattern forms cavities in the recessed regions of the first pattern. These cavities are opened and filled with a third material. The second material is then removed, and the remaining third material forms a second pattern of third material protruding regions, wherein the second pattern is interleaved with the first pattern.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: December 3, 2013
    Inventors: Yves Morand, Thierry Poiroux
  • Patent number: 8598643
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises a first conductive layer, a second conductive layer, a first inter-electrode insulating film, and a third conductive layer stacked above the first conductive layer, a memory film, a semiconductor layer, an insulating member, and a silicide layer. The memory film and the semiconductor layer is formed on the inner surface of through hole provided in the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The insulating member is buried in a slit dividing the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The silicide layer is formed on surfaces of the second conductive layer and the third conductive layer in the slit. The distance between the second conductive layer and the third conductive layer along the inner surface of the slit is longer than that of along the stacking direction.
    Type: Grant
    Filed: September 18, 2011
    Date of Patent: December 3, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kaori Kawasaki, Yoshiaki Fukuzumi, Masaru Kito, Tomoko Fujiwara, Takeshi Imamura, Ryouhei Kirisawa, Hideaki Aochi