Method of making high speed interposer
A method of making a high speed interposer which includes a substrate having alternatingly oriented dielectric and conductive layers which form a substrate, openings which extend from one opposing surface of the substrate to a second opposing surface, conductive members positioned within the openings and also extending from surface to surface (and beyond, in some embodiments), and a plurality of shielding members positioned substantially around the conductive members to provide shielding therefore during the passage of high frequency signals through the conductive members.
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In Ser. No. 11/086,324, filed Mar. 23, 2005, there is defined a circuitized substrate in which at least one signal line used therein is shielded by a pair of opposingly positioned ground lines which in turn are electrically coupled to a ground plane located beneath the signal and ground lines and separated there-from by a common interim dielectric layer. An electrical assembly including the circuitized substrate as part thereof and a method of making the circuitized substrate are also included. The substrate may form part of a larger structure such as a PCB, chip carrier or the like.
In Ser. No. 11/401,401, filed Apr. 11, 2006, there is defined a circuitized substrate in which selected ones of the signal conductors are substantially surrounded by shielding members which shield the conductors during passage of high frequency signals, e.g., to reduce noise. The shielding members may form solid members which lie parallel and/or perpendicular to the signal conductors, and may also be substantially cylindrical in shape to surround a conductive thru-hole which also forms part of the substrate. An electrical assembly and an information handling system are also defined.
In Ser. No. 11/454,896, filed Jun. 19, 2006, there is defined a high speed interposer which includes a substrate having alternatingly oriented dielectric and conductive layers which form a substrate, openings which extend from one opposing surface of the substrate to a second opposing surface, conductive members positioned within the openings and also extending from surface to surface (and beyond, in some embodiments), and a plurality of shielding members positioned substantially around the conductive members to provide shielding therefore during the passage of high frequency signals through the conductive members.
The present application is a divisional of Ser. No. 11/454,896. The above applications are assigned to the same Assignee as the present invention, Endicott Interconnect Technologies, Inc.TECHNICAL FIELD
The present invention relates to methods of making electrical connectors and, more particularly, to electrical connectors for interconnecting circuitized substrates such as printed circuit boards (hereinafter also referred to as PCB's), chip carriers, or the like, especially those which may be used in information handling systems (e.g., computers, computer servers, mainframes, etc.).BACKGROUND OF THE INVENTION
Electrical connectors used in many of today's products such as those described above must provide high electrical performance, high density and highly reliable connections between various circuit devices, which form important parts of these products.
Improvement of signal integrity (performance) for such connectors may be accomplished by providing the interconnections with shielding, thus helping these to more closely match the desired product's impedance. To enable effective repair, upgrade, and/or replacement of various components of the product (e.g., connectors, cards, chips, boards, modules, etc.), it is also highly desirable that such connections be separable and re-connectable in the field. Such a capability is also desirable during the manufacturing process for such products in order to facilitate testing, for example. Both of these features (shielding and separability) must be provided in such a manner so as to assure a final product which is highly reliable and cost effective. In this regard, it is understood that one or more misconnections within critical parts of the overall product may result in product failure and the need for costly replacement.
A land grid array (hereinafter also referred to as an LGA) interposer connector (hereinafter also simply referred to as an interposer) is an example of such a connector in which each of two primarily parallel circuit elements to be connected has a plurality of contact points, arranged in a linear or two-dimensional array. An array of interconnection elements (the LGA interposer) is placed between the two arrays to be connected, and provides the electrical connection between the contact points or pads. An LGA interposer typically includes at least one conductive plane sandwiched between two dielectric planes. The conductive plane typically includes a pattern of circuitry. A plurality of plated through holes (hereinafter also referred to as PTH's) are formed through the planes of the interposer so that the pattern of plated through holes formed on one surface of the interposer matches the pattern of ground, power and signal sites on the chip carrier or other electrical component; and the pattern of plated through holes on the opposite side of the interposer matches the pattern of ground, power, and signal sites on the PCB or other circuitized substrate. Examples of LGA and similar interposers are known in the art, with examples provided below. It is to be understood that the invention is not limited to LGA connectors but is applicable to many other kinds of connectors and modules.
In U.S. Pat. No. 7,176,383, there is defined a printed circuit board and method of making same in which the board includes a common power plane having dielectric layers on opposing sides thereof and a signal layer on each of said dielectric layers, each signal layer comprising a plurality of substantially parallel signal lines running in substantially similar directions across the signal layers. Predetermined portions of the signal lines in one signal layer are aligned relative to and also parallel to corresponding signal lines in the other signal layer, with the power plane being located between these portions. Through hole connections are provided between selected signal lines in the two layers, these occurring through clearance holes in the power plane so as to be isolated there-from. U.S. Pat. No. 7,176,383 is assigned to the same assignee as the present invention.
In U.S. Pat. No. 6,954,984, there is described an Land Grid Array structure which includes a flexible film interposer that provides electrical connection between a multi-chip module and the next level of integration such as a system board while allowing for engineering change capabilities as well as a means for decoupling power to ground structure to minimize switching activity effects on the overall system using this structure.
In U.S. Pat. No. 6,638,077, there is described a shielded carrier with electrical components, resulting in an LGA interposer connector with apparent improved electrical performance and enhanced functionality. The carrier includes components such as resistors and capacitors on and/or in the carrier. The components are preferably of the surface mount variety or are imbedded within the carrier, due to the inherent lower profile of these form factors. Decoupling capacitors and terminating resistors are two examples of components that may improve performance.
In U.S. Pat. No. 6,528,892, there is described a flexible chip carrier with contact pads on its upper surface matching those of the chip with the pads conductively connected to LGA pads on its lower surface matching those of a PCB. The chip carrier is provided with a stiffening layer at the LGA interface which is mechanically attached to the lower surface of the chip carrier. Holes are formed in the stiffening layer to expose the LGA pads. The holes are then filled with a conductive adhesive material. Compliant LGA bumps are applied to the uncured conductive adhesive material and the material is then cured.
In U.S. Pat. No. 6,471,525, there is described a carrier with electrical shielding of individual contact elements, resulting in an LGA interposer connector with alleged improved electrical performance. The carrier includes a plurality of openings, each of which may contain an individual contact element. The openings may be plated with conductive material, and may also be commoned to one or more reference voltages (e.g., ground) present on at least one conductive layer of the carrier. The carrier may be a single unified structure with a conductive layer on one outer surface, or much more complex, having many layers of dielectric and conductive material.
In U.S. Pat. No. 6,312,266, there is described a carrier that provides improved retention to the individual contact elements resulting in an LGA interposer connector with apparent improved mechanical and electrical performance. In one embodiment, the carrier, which includes upper and lower sections of dielectric material with an adhesive layer in between, includes a plurality of openings, each of which may contain an individual contact element. During assembly of the connector, once the contact elements are inserted, the adhesive layer is reflowed, thereby allowing the carrier to capture the location of the contact elements both with respect to each other as well as to the carrier. Alternately, the carrier may be implemented in a manner which, while not including an adhesive layer to be reflowed, still provides improved retention of the individual contact elements.
In U.S. Pat. No. 6,137,161, there is described a semiconductor package which includes an interposer with upper surface contacts aligned with circuit chip contacts and lower surface contacts aligned with the corresponding contacts on a supporting substrate. The interposer includes a series of ground plane layers which are capacitively coupled to the conductors that connect the upper surface contacts to the lower surface contacts. The ground plane layers closest to the circuit chip have plates there-between and electrically separated there-from which are connected to the power input supply lines to form decoupling capacitances. The ground plane layers more remote from the circuit chip have, there-between and electrically separated there-from, conductive flange portions attached to individual signal lines to form a low pass feed-through filter for each signal line. The capacitance of the flange portions is designed to establish the correct roll off to pass the desired signals and shunt to ground the unwanted harmonics while the decoupling capacitance is sized to afford the required, stabilized power supply. The semiconductor package also may include a conductive shield member that surrounds the top and four sides of the package and is connected to the grounded elements of the interposer to provide mechanical connection and apply ground potential to the shield.
In U.S. Pat. No. 6,097,611, there is described an LGA carrier which includes an interposer having a first surface and a second surface opposite the first surface, with a plurality of locations on the first surface adapted to receive a plurality of semiconductor dice and passive components. The second surface has a plurality of conductive pads coupled thereto.
In U.S. Pat. No. 6,097,609, there is described an electronic packaging assembly in which an electronic component is disposed on a socketing substrate utilizing a ball grid array or LGA. The socketing substrate contains a series of pins that are embedded within the thickness of the socketing substrate, these pins corresponding to the ball grid array or land grid array contacts of the electronic component. The socketing substrate is mounted onto a motherboard using an array of solder balls that correspond to and are disposed on, the end of the pins facing the motherboard. If desired, the electronic component may be protected by a metal lid.
In U.S. Pat. No. 5,599,193, there is described an electrical interconnector for connecting an integrated circuit or other electrical or electronic component to a circuit board or for interconnecting two or more circuit boards. The interconnector comprises a substrate having one or more resilient elements of a non-conductive material and having opposite contact surfaces. A flexible conductive coating is provided on the contact surfaces of the resilient elements and extends between the contact surfaces to provide electrical connection there-between. In one embodiment, each element is integrally formed with a resilient substrate and has electrically conductive contact surfaces which are outward of the respective substrate surfaces and are electrically connected through a conductive surface which extends through vias (openings) formed in the substrate. In another embodiment, each element is individually formed and is disposed within a corresponding cavity of a separate substrate. In a further embodiment, each element is individually formed having different sections of different durometers so as to provide intended spring or resilience characteristics. A particulate layer can be provided on the conductive contact surfaces to provide a roughened surface by which an oxide layer on a mating electrical contact is penetrated to minimize contact resistance.
In U.S. Pat. No. 5,530,288, there is described an interposer including a first face and second face opposite the first face and at least one electrically conductive plane. The conductive plane functions as a power, ground, or signal plane. At least one electrically insulating plane is positioned on opposite sides of the conductive plane. A plurality of PTH's are formed through the conductive plane and the two insulating planes. The PTH's are selectively electrically joined to the conductive plane. At least one passive electronic structure is positioned within the interposer structure.
As understood from the following description, the present invention provides an interposer with improved shielding of various conductors therein in a new and unique manner and which can be produced using conventional PCB manufacturing processes which require little or no modification thereto. It is believed that such an invention will constitute a significant advancement in the art.OBJECTS AND SUMMARY OF THE INVENTION
It is a primary object of the invention to enhance the electrical connector art and particularly that aspect of the art which involves electrical interposers such as those used to interconnect electrical components such as semiconductor devices, chip carriers and the like with circuitized substrates such as PCB's.
It is another object of the invention to provide such an interposer with enhanced electrical functioning capabilities, especially improved shielding.
It is yet another object of the invention to provide such an interposer which can be produced using conventional PCB manufacturing processes which require little or no modification thereto, thereby providing an end product which is cost effective. According to one aspect of the invention, there is provided.
According to one aspect of the invention, there is provided a method of making an interposer which comprises providing a substrate including first and second opposing surfaces and including a plurality of dielectric layers and a plurality of conductive layers oriented within said substrate in an alternating manner with respect to the dielectric layers, forming a plurality of openings within the substrate which extend substantially through the substrate from the first opposing surface to the second opposing surface, providing a conductive member within each of the openings which extends substantially from the first opposing surface to the second opposing surface, and forming a plurality of shielding members within the substrate which each also extend substantially from the first opposing surface to the second opposing surface and which is positioned substantially around a respective conductive member at a spaced distance there-from, each shielding member being adapted for providing shielding the respective conductive member during the passage of high frequency signals through the conductive member.
For a better understanding of the present invention, together with other and further objects, advantages and capabilities thereof, reference is made to the following disclosure and appended claims in connection with the above-described drawings. Like figure numbers will be used from FIG. to FIG. to identify like elements in these drawings.
By the term “substrate” as used herein is meant to include structures having plurality of dielectric layers and a plurality of electrically conductive layers, at least some of both being arranged in an alternating manner, e.g., dielectric layer—conductive layer—dielectric layer—conductive layer, etc. Examples of dielectric materials usable for such substrates include fiberglass-reinforced epoxy resins (some referred to as “FR4” dielectric materials in the art, for the flame retardant rating of same), polytetrafluoroethylene (e.g., Teflon), polyimides, polyamides, cyanate resins, photo-imagable materials, and other like materials. Examples of conductor materials usable in such substrates include copper or copper alloys, but may include or comprise additional metals (e.g., nickel, aluminum, etc.) or alloys thereof. Such conductor materials are used to form layers which may serve as power, signal and/or ground layers. If as a signal layer, several conductor lines and/or pads may constitute the layer, while if used as power or ground, such layers will typically be of substantially solid construction. Combinations of signal, power and/or ground are possible in one substrate, and combinations of signal, power and/or ground are possible in one conductive layer. Examples of substrates include the aforementioned printed circuit boards (or cards) and chip carriers, when the conductive layers are “circuitized”, meaning these are capable of carrying signals (if a signal layer), power (if a power layer) or serving as ground (if a ground layer).
Conductive thru-holes are known in the substrate art, and are often referred to as “vias” if internally located (entirely within the substrate's outer confines), “blind vias” if extending a predetermined depth within the substrate from an external surface, or “plated thru-holes” (PTHs) if extending substantially through the substrate's full thickness. By the term “thru-hole” as used herein, therefore, is meant to include all three types of such substrate openings.
As understood, the term “high frequency” as used herein is meant signals of high speed. Examples of such signal frequencies attainable for the substrates produced in accordance with the teachings herein include those within the range of as high as from about 3.0 to about 10.0 gigabits per second (GPS). These examples are not meant to limit this invention, however, because frequencies outside this range, including those higher, are attainable.
By the term “electrical assembly” as used herein is meant an assembly including at least one interposer as taught herein and at least one semiconductor chip which is electrically coupled to the interposer, e.g., through use of a laminated carrier.
Following opening formation (which may include cleaning of the interior walls of the substrate, again, using conventional PCB processing), opening 21 is rendered conductive by applying a metal layer 23 to the opening's interior surfaces and, as shown in
Thus there has been shown and described an interposer which is able to interconnect conductive members such that high speed signals may be passed through the interposer and protected (shielded) from unwanted interference. The interposer may be utilized in a fixed embodiment (e.g., soldered to the respective conductors) or as a separable member (e.g., using pins or LGA pads). Significantly, the interposer as defined herein is capable of being manufactured using many conventional PCB and/or chip carrier manufacturing steps, thereby saving considerable time and costs over many known interposers which claim to provide high speed interconnections.
While there have been shown and described what are at present the preferred embodiments of the invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the scope of the invention as defined by the appended claims.
1. A method of making an interposer, said method comprising:
- providing a substrate including first and second opposing surfaces and including a plurality of dielectric layers and a plurality of conductive layers oriented within said substrate in an alternating manner with respect to said plurality of said dielectric layers;
- forming a plurality of openings within said substrate which extend substantially through said substrate from said first opposing surface to said second opposing surface;
- providing a conductive member within each of said openings which extends substantially from said first opposing surface of said substrate to said second opposing surface of said substrate; and
- forming a plurality of shielding members within said substrate which each extend substantially from said first opposing surface of said substrate to said second opposing surface of said substrate and is positioned substantially around a respective one of said conductive members at a spaced distance there-from, each of said shielding members being adapted for providing shielding for a respective one of said conductive members during the passage of high frequency signals through said conductive member.
2. The method of claim 1 wherein said plurality of openings is formed within said substrate using a drilling operation.
3. The method of claim 2 wherein said drilling operation is accomplished using mechanical or laser drilling.
4. The method of claim 1 wherein said shielding members are formed using a plating operation, said plating operation comprising forming a conductive layer on each of said openings.
5. The method of claim 4 further including substantially filling each of said openings with a dielectric composition following said plating operation.
6. The method of claim 5 further including thereafter forming a second opening within each of said dielectric compositions within said substantially filled openings having said conductive layer thereon and thereafter positioning a pin within said second opening, said pins being said conductive members.
7. The method of claim 5 further including forming at least one cover on one end of each of said substantially filled openings.
8. The method of claim 5 further including thereafter forming a second opening within each of said dielectric compositions within said substantially filled openings having said conductive layer thereon and thereafter positioning a quantity of conductive material within said second opening.
9. The method of claim 8 further including forming a conducting layer on each of said second openings prior to said positioning of said quantity of said conductive material within said second opening.
10. The method of claim 9 wherein each of said conducting layers are formed using a plating operation.
International Classification: H05K 3/42 (20060101); H05K 3/10 (20060101);