Manufacturing Circuit On Or In Base Patents (Class 29/846)
  • Patent number: 11656195
    Abstract: Systems and methods are provided that address the need to frequently calibrate analyte sensors, according to implementation. In more detail, systems and methods provide a preconnected analyte sensor system that physically combines an analyte sensor to measurement electronics during the manufacturing phase of the sensor and in some cases in subsequent life phases of the sensor, so as to allow an improved recognition of sensor environment over time to improve subsequent calibration of the sensor.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: May 23, 2023
    Assignee: Dexcom, Inc.
    Inventors: Naresh C. Bhavaraju, Becky L. Clark, Vincent P. Crabtree, Chris W. Dring, Arturo Garcia, Jason Halac, Jonathan Hughes, Jeff Jackson, Lauren Hruby Jepson, David I-Chun Lee, Ted Tang Lee, Rui Ma, Zebediah L. McDaniel, Jason Mitchell, Andrew Attila Pal, Daiting Rong, Disha B. Sheth, Peter C. Simpson, Stephen J. Vanslyke, Matthew D. Wightlin, Anna Leigh Davis, Hari Hampapuram, Aditya Sagar Mandapaka, Alexander Leroy Teeter, Liang Wang
  • Patent number: 11653439
    Abstract: Provided is a ground member that can prevent damage to interlayer adhesion between a conductive layer and an adhesive layer of the ground member due to heating in producing a shielded printed wiring board or in mounting an electronic component on a shielded printed wiring board. The ground member of the present invention includes: a conductive layer; and an adhesive layer stacked on the conductive layer, the adhesive layer containing a binder component and hard particles, the adhesive layer having a thickness of 5 to 30 ?m.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: May 16, 2023
    Assignee: TATSUTA ELECTRIC WIRE & CABLE CO., LTD.
    Inventors: Yoshihiko Aoyagi, Kenji Kamino, Yuusuke Haruna
  • Patent number: 11643525
    Abstract: An electronic device with self-recovering properties including a substrate including a polymer composite, a conductive pattern disposed on the substrate, and an electrode disposed on the conductive pattern is provided, and the polymer composite includes a composite of different first and second polymers, the first polymer includes a first functional group capable of forming a hydrogen bond between polymer chains, and the second polymer includes a second functional group capable of forming a hydrogen bond between polymer chains.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: May 9, 2023
    Assignee: Korea University Research and Business Foundation
    Inventors: Jeongsook Ha, Jungwook Kim
  • Patent number: 11616165
    Abstract: The present disclosure provides a method for manufacturing an electronic device. First, a plurality of light-emitting elements is provided on a first substrate. Then, at least one of the plurality of light-emitting elements is transferred from the first substrate to a second substrate by a transferring head. The transferring head includes an electrode and a cantilever supporting the electrode, and the cantilever includes a U-shaped portion.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: March 28, 2023
    Assignee: InnoLux Corporation
    Inventors: Hui-Chieh Wang, Tsau-Hua Hsieh, Fang-Ying Lin
  • Patent number: 11610929
    Abstract: The present disclosure relates to a semiconductor element, a manufacturing method of a semiconductor element, and an electronic apparatus, which enable suppression of crack occurrences and leaks. The present technology has a laminated structure including an insulating film having a CTE value between those of metal and Si and disposed under a metal wiring, and P—SiO (1 ?m) having good coverage and disposed as a via inner insulating film in a TSV side wall portion. As the insulating film having a CTE that is in the middle between those of metal and Si, for example, SiOC is used with a thickness of 0.1 ?m and 2 ?m respectively in the via inner insulating film and a field top insulating film continuous to the via inner insulating film. The present disclosure can be applied to, for example, a solid-state imaging element used in an imaging device.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: March 21, 2023
    Assignee: SONY CORPORATION
    Inventor: Naoto Sasaki
  • Patent number: 11605487
    Abstract: A laminate includes multiple paper layers, with at least one induction coil comprising first and second sets of windings. Two or more paper layers include the sets of windings comprising an electrically-conductive material. The sets of windings may be distributed throughout the laminate layers and provide good wireless induction charging performance in a compact space.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: March 14, 2023
    Assignee: THE DILLER CORPORATION
    Inventors: Robert Jacob Kramer, Kevin Francis O'Brien
  • Patent number: 11532569
    Abstract: A semiconductor package structure includes a first redistribution layer, a second redistribution layer and an interconnecting structure. The first redistribution layer has a first surface and a second surface opposite to each other. The second redistribution layer is disposed over the first surface of the first redistribution layer, wherein the second redistribution layer has a third surface and a fourth surface opposite to each other, and the third surface facing the first surface. The interconnecting structure is disposed between and electrically connected to the first redistribution layer and the second redistribution layer, wherein the interconnecting structure comprises a conductive post and a conductive bump stacked to each other.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jui-Pin Hung, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, De-Dui Marvin Liao
  • Patent number: 11527485
    Abstract: The present disclosure relates to a semiconductor package that may include a substrate, an interposer coupled to the substrate, a shield frame including at least one frame recess and at least one opening positioned over the interposer, a conductive shield layer on the shield frame, and a plurality of components coupled to the interposer.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: December 13, 2022
    Assignee: Intel Corporation
    Inventors: Seok Ling Lim, Bok Eng Cheah, Jenny Shio Yin Ong, Jackson Chung Peng Kong, Kooi Chi Ooi
  • Patent number: 11527479
    Abstract: A chip package including a chip; a substrate; an interposer module including a first layer having a larger surface area than the surface area of a second layer, wherein a bottom of the second layer is attached to a top of the first layer area creating an exposed surface area of the first layer; via openings extending at least partially through the first layer; via openings extending at least partially through the first layer and the second layer; a plurality of conductive routing electrically coupled between the via openings, wherein the chip is electrically coupled to the via openings of a top of the second layer, wherein the substrate is electrically coupled to via openings of a bottom of the first layer; and an electronic component electrically coupled to the via openings of the exposed surface area of the first layer.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: December 13, 2022
    Assignee: Intel Corporation
    Inventors: Chin Lee Kuan, Bok Eng Cheah, Jackson Chung Peng Kong
  • Patent number: 11494039
    Abstract: A touch sensor having a visible area and a peripheral area at least on one side of the visible area includes a substrate, a touch electrode layer, and peripheral traces. The touch electrode layer is disposed on a surface of the substrate and includes touch electrodes corresponding to the visible area. The peripheral traces are disposed on the surface of the substrate and corresponding to the peripheral area. The peripheral traces are respectively electrically connected to the touch electrodes. Each of the peripheral traces includes a matrix and metal nanowires distributed in the matrix. A line width of each of the peripheral traces is more than or equal to 6 ?m and less than or equal to 12 ?m, and a line spacing of any adjacent peripheral traces of the peripheral traces is more than or equal to 6 ?m and less than or equal to 12 ?m.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: November 8, 2022
    Assignee: TPK Advanced Solutions Inc.
    Inventors: Shao Jie Liu, Qin Xue Fang, Xue Long Zhang, Mei Fang Lan, Wei-Chia Fang, En-Chia Chang, Xiao Ping Guo
  • Patent number: 11488906
    Abstract: A bridge embedded interposer and a package substrate and a semiconductor package including the same includes: a connection structure including one or more redistribution layers, a first bridge disposed on the connection structure and including one or more first circuit layers electrically connected to the one or more redistribution layers, a frame disposed around the first bridge on the connection structure and including one or more wiring layers electrically connected to the one or more redistribution layers, and an encapsulant disposed on the connection structure and covering at least a portion of each of the first bridge and the frame.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: November 1, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jung Hyun Cho, Young Kwan Lee, Young Sik Hur, Yun Tae Lee, Ho Kwon Yoon
  • Patent number: 11476035
    Abstract: A coil component includes: a magnetic body part having a first compact containing a first magnetic material and a first resin, and a second compact placed on the outside of the first compact and containing a second magnetic material and a second resin; a coil formed by a conductive wire which comprises a metal conductor covered with an insulating film, and embedded in the magnetic body part; and lead parts of the coil placed on the outside of the first compact; wherein the filling rate of the first magnetic material constituting the first compact is higher than the filling rate of the second magnetic material constituting the second compact. The filling rate of magnetic grains can be improved while also ensuring the insulating property of the coil, etc.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: October 18, 2022
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Makoto Shimizu, Tomoo Kashiwa
  • Patent number: 11448965
    Abstract: Disclosed herein are methods for patterning two-dimensional atomic layer materials, the methods comprising: illuminating a first location of an optothermal substrate with electromagnetic radiation, wherein the optothermal substrate converts at least a portion of the electromagnetic radiation into thermal energy, and wherein the optothermal substrate is in thermal contact with a two-dimensional atomic layer material; thereby: generating an ablation region at a location of the two-dimensional atomic layer material proximate to the first location of the optothermal substrate, wherein at least a portion of the ablation region has a temperature sufficient to ablate at least a portion of the two-dimensional atomic layer material within the ablation region, thereby patterning the two-dimensional atomic layer material. Also disclosed herein are systems for performing the methods described herein, patterned two-dimensional atomic layer materials made by the methods described herein and methods of use thereof.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: September 20, 2022
    Assignee: Board of Regents, The University of Texas System
    Inventors: Yuebing Zheng, Linhan Lin, Jingang Li
  • Patent number: 11424743
    Abstract: An operator control device for a vehicle, and a method for operating such an operator control device is disclosed. The operator control device is for controlling safety-relevant functions. To this end, the operator control device has at least one user interface having at least one user input panel for user input and a sensor system for identifying a user input in the area of the user input panel, wherein the sensor system has at least one capacitive sensor device having a first, electrically conductive sensor structure and a second, capacitive sensor device having a second, electrically conductive sensor structure, the sensor structures being arranged beneath the user interface in the area of the user input panel. The first sensor structure and the second sensor structure are each configured in comb-like and/or meanderous fashion and arranged in intermeshing fashion at least in a subarea of the user input panel.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: August 23, 2022
    Assignee: Valeo Schalter und Sensoren GmbH
    Inventor: Sascha Staude
  • Patent number: 11417604
    Abstract: A method embodiment includes forming a patterned first photo resist over a seed layer. A first opening in the patterned first photo resist exposes the seed layer. The method further includes plating a first conductive material in the first opening on the seed layer, removing the patterned first photo resist, and after removing the patterned first photo resist, forming a patterned second photo resist over the first conductive material. A second opening in the patterned second photo resist exposes a portion of the first conductive material. The method further includes plating a second conductive material in the second opening on the first conductive material, removing the patterned second photo resist, and after removing the patterned second photo resist, depositing a dielectric layer around the first conductive material and the second conductive material.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Hung-Jui Kuo, Hui-Jung Tsai
  • Patent number: 11399432
    Abstract: A component carrier includes a stack with a plurality of electrically conductive layer structures and at least one electrically insulating layer structure. The electrically conductive layer structures include an electrically conductive vertical through-connection and a horizontally extending electrically conductive trace electrically coupled with an end portion of the vertical through-connection. A back-drill hole extends through at least part of the at least one electrically insulating layer structure towards the end portion of the vertical through-connection. An etching neck connects the back-drill hole with the end portion of the vertical through-connection.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: July 26, 2022
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Markus Kastelic, Lackner Sebastian
  • Patent number: 11380648
    Abstract: The invention concerns a support intended for the implementation of a method of self-assembly of at least one element on a surface of the support, including at least one assembly pad on said surface, a liquid drop having a static angle of contact on the assembly pad smaller than or equal to 15°, and nanometer- or micrometer-range pillars on said surface around the pad, the liquid drop having a static angle of contact on the pillars greater than or equal to 150°.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: July 5, 2022
    Assignee: Commissariat à l'Energie Atomique et aux Energies Alternatives
    Inventors: Léa Di Cioccio, Jean Berthier, Nicolas Posseme
  • Patent number: 11337309
    Abstract: Disclosed herein is a method of forming vias in electrical laminates comprising laminating a sheet having a layer comprising a crosslinkable polymer composition to a substrate wherein the crosslinkable polymer composition has a viscosity at lamination temperatures in the range of 200 Pa-s to 100,000 Pa-s, forming at least one via in the crosslinkable polymer layer by laser ablation; and after the forming of the at least one via, thermally curing the crosslinkable polymer layer. According to certain embodiments the cross linkable polymer composition has a viscosity at lamination temperature of at least 5000 Pa-s. This method yields good lamination results, good via profiles, and good desmear results when such compositions are used and the via is laser ablated before cure.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: May 17, 2022
    Assignee: ROHM AND HAAS ELECTRONIC MATERIALS LLC
    Inventors: Tina Aoude, David Fleming, Michelle Bowerman Riener, Colin O'Mara Hayes, Herong Lei, Robert K. Barr, David Louis Danza
  • Patent number: 11320417
    Abstract: In a non-limiting embodiment, a device may include a substrate having conducting lines thereon. One or more fin structures may be arranged over the substrate. Each fin structure may include a sensor arranged over the substrate and around the fin structure. The sensor may include a self-aligned first sensing electrode and a self-aligned second sensing electrode arranged around the fin structure. The first sensing electrode and the second sensing electrode each may include a first portion lining a sidewall of the fin structure and a second portion arranged laterally from the first portion. At least the first portion of the first sensing electrode and the first portion of the second sensing electrode may define a sensing cavity of the sensor. The second portion of the first sensing electrode and the second portion of the second sensing electrode may be electrically coupled to the conducting lines.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: May 3, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Xinshu Cai, Shyue Seng Tan, Eng Huat Toh, Kiok Boone Elgin Quek
  • Patent number: 11317522
    Abstract: Provided is a method of manufacturing a circuit board involves: preparing a composite laminate including a support, a release layer, and a multilayered circuit board; disposing the composite laminate on a stage such that one face of the composite laminate is put into tight contact with the stage; and releasing the support or the multilayered circuit board from the release layer such that the support or the multilayered circuit board forms a convex face with a curvature radius of 200 to 5000 mm while the face of the composite laminate is kept in tight contact with the stage. The method according to the present invention can prevent the occurrences of defects, for example, breaking in the support and cracking and wire disconnections in the multilayered circuit board in manufacturing of circuit boards, such as coreless circuit boards, and ensure stable release of the support or the multilayered circuit board.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: April 26, 2022
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Toshimi Nakamura, Yoshinori Matsuura
  • Patent number: 11293952
    Abstract: A passive current sensor includes a pair of electrically conductive busbars, a shunt resistor electrically connecting the busbars, and a support having a first pair of voltage drop measuring contacts. At least one of the voltage drop measuring contacts is attached to each of the busbars and forms a direct electrical contact between the at least one voltage drop measuring contact and the busbar.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: April 5, 2022
    Assignee: TE CONNECTIVITY GERMANY GMBH
    Inventors: Christoph Mueller, Sven Faas, Jens Gruendler, Walter Weinerth, Thimo Paulus, Claudio Negretti, Christoph Kraemer
  • Patent number: 11293495
    Abstract: A bush assembly configured to be disposed between a first component and a second component movably coupled to the first component, the bush assembly comprising a first bush portion comprising a self-lubricating material; and a second bush portion, the second bush portion having greater electrical conductivity than the first bush portion, wherein the second bush portion provides a conductive path between the first component and the second component.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: April 5, 2022
    Inventors: Daniel Haikney, Neil Price
  • Patent number: 11291110
    Abstract: A resin substrate includes a resin body, an interlayer connection conductor provided in the resin body, and a conductor pattern bonded to the interlayer connection conductor. The resin body includes a gap provided adjacent to or in a vicinity of a bonding portion of the interlayer connection conductor and the conductor pattern, and a contact portion that contacts the interlayer connection conductor.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: March 29, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yusuke Kamitsubo
  • Patent number: 11234329
    Abstract: A prepreg is used to fabricate a semiconductor package including a chip and a substrate to mount the chip thereon. The prepreg is in a semi-cured state. The substrate includes a cured product of the prepreg. The chip has: a first chip surface located opposite from the substrate; and a second chip surface located opposite from the first chip surface. The prepreg satisfies the relational expression: 0.9?X2/X1?1.0 (I), where X1 is a coefficient of thermal expansion of the first chip surface of the chip before the chip is mounted on the substrate, and X2 is a coefficient of thermal expansion of the first chip surface of the chip after the chip has been mounted on the substrate.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: January 25, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Rihoko Watanabe, Keiko Kashihara, Hiroharu Inoue
  • Patent number: 11229117
    Abstract: A printed circuit board includes: an insulating layer having one surface and the other surface; metal layers respectively disposed on the one surface and the other surface of the insulating layer; a through-hole penetrating through the insulating layer and the metal layers; a first plating layer disposed in a center portion of the through-hole in a thickness direction thereof; and a plug disposed in the through-hole.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: January 18, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jung Soo Kim, Jin Won Lee, Woo Seok Jeon
  • Patent number: 11217971
    Abstract: The present disclosure provides an AC power adapter comprising plural connectors, plural first power conveying wires, a junction box, a power conveying wire assembly and a plug. The first power conveying wire is connected with the connector and comprises an input neutral wire, an input live wire and an input ground wire. The first power conveying wire is inserted into the junction box. The power conveying wire assembly is inserted into the junction box and comprises plural output neutral wires, plural output live wires and an output ground wire. The output neutral wires are connected with the input neutral wires one-to-one, the output live wires are connected with the input live wires one-to-one, and the output ground wire is connected with the input ground wires. The plug comprises a housing and an electrical connector. The power conveying wire assembly is inserted into the housing and connected with the electrical connector.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: January 4, 2022
    Assignee: DELTA ELECTRONICS, INC.
    Inventor: Yu-Hung Huang
  • Patent number: 11217951
    Abstract: The present disclosure provides an AC power adapter comprising input connectors, first power conveying wires, a junction box, a power conveying wire assembly and a plug. The first power conveying wire is coupled to the input connector and includes an input neutral wire, an input live wire and an input ground wire. The power conveying wire assembly is electrically connected to the first power conveying wire through the junction box and includes plural output neutral wires, plural output live wires and an output ground wire. The output neutral wires are coupled to the input neutral wires respectively, the output live wires are coupled to the input live wires respectively, and the output ground wire is coupled to the input ground wires. The plug includes a housing and an electrical connector. The power conveying wire assembly is inserted into the housing and connected with the electrical connector.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: January 4, 2022
    Assignee: DELTA ELECTRONICS, INC.
    Inventor: Yu-Hung Huang
  • Patent number: 11158568
    Abstract: An apparatus is provided which comprises: a plurality of organic dielectric layers forming a substrate, a plurality of first conductive contacts on a top surface of the substrate, a plurality of second conductive contacts on a bottom surface of the substrate, a plurality of third conductive contacts on a side wall surface of the substrate, and one or more discrete capacitor(s) coupled with the third conductive contacts on the side wall surface. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: October 26, 2021
    Assignee: Intel Corporation
    Inventors: Jenny Shio Yin Ong, Seok Ling Lim
  • Patent number: 11152316
    Abstract: Methods of forming packages include forming an encapsulant laterally encapsulating a die over an active surface of the die. The active surface has an electrical pad. A first opening is formed through the encapsulant to the electrical pad. In some embodiments the first opening is formed using a photolithographic technique. In some embodiments the first opening is formed using a temporary pillar by forming the temporary pillar over the electrical pad, forming the encapsulant, and then exposing and removing the temporary pillar. A conductive pattern is formed over the encapsulant including a via formed in the first opening to the electrical pad of the die's active surface. In some embodiments, a dielectric layer is formed over the encapsulant, and the conductive pattern is over the dielectric layer. Embodiments may include forming additional dielectric layers and conductive patterns.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Cheng Hsu, Szu-Wei Lu, Jing-Cheng Lin
  • Patent number: 11121489
    Abstract: An electrical connector includes a flexible circuit with a flexible material and traces at least partially embedded in the flexible material. The electrical connector further includes a first set of conductive bumps, a second set of conductive bumps, and a stiffener. The first set of conductive bumps is coupled to respective first end portions of the traces and extends from a first side of the flexible circuit. The second set of conductive bumps is coupled to respective second end portions of the traces. The stiffener is coupled to the flexible circuit on a second side of the flexible circuit opposite the first side.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: September 14, 2021
    Assignee: Seagate Technology LLC
    Inventors: Peng Peng, William A. Casey, Dennis L. Buster, Kerry J. Johnson, Ruth LeMon, Ronald E. Anderson
  • Patent number: 11040873
    Abstract: In a method of manufacturing a highly stretchable three-dimensional (3D) percolated conductive nano-network structure, a 3D nano-structured porous elastomer including patterns distributed in a periodic network is formed. A surface of the 3D nano-structured porous elastomer is changed to a hydrophilic state. A polymeric material is conformally adhered on the surface of the 3D nano-structured porous elastomer. The surface of the 3D nano-structured porous elastomer is wet by infiltrating a conductive solution in which a conductive material is dispersed. A 3D percolated conductive nano-network coupled with the 3D nano-structured porous elastomer is formed by evaporating a solvent of the conductive solution and removing the polymeric material.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: June 22, 2021
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Seok-woo Jeon, Dong-hwi Cho
  • Patent number: 10947419
    Abstract: A composition of matter includes a first compatible material having particles containing chemical elements similar to a first substrate, and second compatible material having particles containing chemical elements similar to a second substrate, wherein the first substrate and the second substrate are chemically different. The particles are dispersed into a matrix that is in between the first and the second substrate. A deposition system has a multi-material printhead, a first reservoir of a first compatible material having particles containing chemical elements similar to a first substrate, a second reservoir of a second compatible material having particles containing chemical elements similar to a second substrate, a third reservoir of an polymer precursor material, and at least one mixer.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: March 16, 2021
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Gabriel Iftime, David Mathew Johnson, Jessica Louis Baker Rivest
  • Patent number: 10937722
    Abstract: A device substrate includes a first substrate, a second substrate, a plurality of first bonding pads, a plurality of second bonding pads, a plurality of first leads, and a plurality of second leads. The first and second bonding pads are separated from each other. The first bonding pads are arranged in a first column. The second bonding pads are arranged in a second column. The first and second leads respectively overlap the first and second bonding pads. The first lead includes a first extension portion and a first branch portion. The first extension portion extends from the first column to the second column. The first branch portion is connected to an end of the first extension portion close to the second column. An angle is present between the first extension portion and the first branch portion.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: March 2, 2021
    Assignee: Au Optronics Corporation
    Inventors: Ming-Wei Lin, Pin-Miao Liu, Yung-Hsiang Lan, Wen-Hui Lee, Kung-Cheng Lin
  • Patent number: 10937723
    Abstract: A package carrier structure includes an insulating substrate, a first wiring layer, a second wiring layer, at least one conductive via, a plurality of first and second conductive pads, a first insulating layer, a plurality of first and second conductive structures, and an encapsulated layer. The first and second wiring layers are disposed on the upper and lower surfaces of the insulating substrate respectively. The conductive via penetrates through the insulating substrate and electrically connected to the first and second wiring layers. The first and second conductive pads are disposed on the upper surface and electrically connected to the first wiring layer. The first insulating layer is disposed on the upper surface and exposing the first and second conductive pads. The first and second conductive structures are disposed on the first and second conductive pads respectively. The lower surface of the insulating substrate is covered by the encapsulation layer.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: March 2, 2021
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Yu-Chung Hsieh, Chun-Hsien Chien, Yu-Hua Chen
  • Patent number: 10892313
    Abstract: A display device includes: a substrate including a pad area; a plurality of first conductive pads disposed in a matrix form in the pad area in a first direction and in a second direction intersecting the first direction; protrusions disposed on the plurality of first conductive pads; and a plurality of second conductive pads disposed on the plurality of first conductive pads and the protrusions. The plurality of second conductive pads include: contact portions in contact with the first conductive pads; and raised portions configured to extend from the contact portions, to cover the protrusions, and to have heights greater than that of the contact portions. The plurality of second conductive pads include an ultrasonic bondable material.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: January 12, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Byoungyong Kim, Jonghyuk Lee, Jeongho Hwang
  • Patent number: 10881337
    Abstract: An oximetry sensor assembly connector, and a method for making the same, is provided that includes a flexible circuit and a stiffener panel. The flexible circuit has a plurality of layers including at least one electrical trace layer and at least one electromagnetic interference (EMI) shield layer. The stiffener panel has a first side surface and a second side surface, which second side surface is opposite the first side surface. The flexible circuit includes a first segment and a second segment, and one or more of the plurality of layers are disposed within the first segment and the second segment. The flexible circuit is folded such that the first segment is contiguous with the first side surface of the stiffener panel, and the second segment is contiguous with the second side surface of the stiffener panel.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: January 5, 2021
    Assignee: Edwards Lifesciences Corporation
    Inventor: Matthew Dalene
  • Patent number: 10821495
    Abstract: A component of a vehicle structure is obtained by a hot forming operation on a hybrid panel having a sheet element of light alloy and a sheet of plastic material. The hybrid panel is hot formed by pressing it against a forming surface of a mould element by a pressurized gas or by a second mould element. Following this operation, the hybrid panel assumes a configuration corresponding to the forming surface, whereas the light alloy sheet element and the plastic material sheet constituting the hybrid panel adhere to each other following softening by heat of the plastic material. Before the hot forming step, a surface of said light alloy sheet element which must contact the plastic material sheet is subjected to a roughening treatment, thereby defining surface asperities between which the plastic material of the plastic material sheet is inserted when it is softened by heat.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: November 3, 2020
    Assignee: C.R.F. Società Consortile per Azioni
    Inventors: Daniele Bassan, Marco Colosseo
  • Patent number: 10777223
    Abstract: The present invention provides a method of feeding an agent, capable of stabilizing a remaining agent of a feeding part in characteristic and amount just before definitively feeding an agent to each definitive portion. The method includes intermittently moving a feeding part to a plurality of definitive portions defined on a structural object to definitively feed a flowable agent with a predetermined amount to each one of the definitive portions. The structural object includes a semi-finished product part with the definitive portions and a frame to be separated from the semi-finished product part. The frame includes a waste portion for the flowable agent. The waste portion has a same form as the definitive portions. The feeding part wastefully feeds the flowable agent to the waste portion with a same amount as the predetermined amount and thereafter starts the intermittently moving for the definitively feeding of the flowable agent.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: September 15, 2020
    Assignee: NHK SPRING CO., LTD.
    Inventors: Yoshihiro Teramoto, Masaru Inoue, Takeshi Shimoda
  • Patent number: 10770869
    Abstract: The present disclosure provides an AC power adapter comprising plural connectors, plural first power conveying wires, a junction box, a power conveying wire assembly and a plug. The first power conveying wire is connected with the connector and comprises an input neutral wire, an input live wire and an input ground wire. The first power conveying wire is inserted into the junction box. The power conveying wire assembly is inserted into the junction box and comprises plural output neutral wires, plural output live wires and an output ground wire. The output neutral wires are connected with the input neutral wires one-to-one, the output live wires are connected with the input live wires one-to-one, and the output ground wire is connected with the input ground wires. The plug comprises a housing and an electrical connector. The power conveying wire assembly is inserted into the housing and connected with the electrical connector.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: September 8, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventor: Yu-Hung Huang
  • Patent number: 10765000
    Abstract: A method for manufacturing a multilayer printed circuit board includes: preparing a first wiring substrate having a first insulating resin film having a first circuit pattern formed on a first main surface, and a first protective film releasably bonded to a second main surface; partially removing the first protective film and the first insulating resin film to form a bottomed via hole having the first circuit pattern exposed on a bottom surface; filling the bottomed via hole with a conductive paste; disposing a second protective film on the first protective film to cover the bottomed via hole filled with the conductive paste; removing an unnecessary portion of the first wiring substrate after the second protective film is disposed on the first protective film; and peeling off the first protective film and the second protective film from the first wiring substrate after the unnecessary portion is removed.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: September 1, 2020
    Assignee: NIPPON MEKTRON, LTD.
    Inventors: Fumihiko Matsuda, Shoji Takano
  • Patent number: 10765013
    Abstract: A method for manufacturing rigid-flexible circuit board includes the step of providing an adhesive sheet defining at least one first opening, a copper foil, and a flexible board. The flexible board comprises a mounting region and a folding region. A removable sheet is pressed on a pressed surface of the adhesive sheet corresponding to each first opening. The copper foil, the adhesive sheet with the removable sheet, and the flexible board are pressed together in that sequence. The removable sheet corresponds to the folding region, and is embedded in the adhesive sheet. The copper foil contacts with the pressed surface and the removable sheet. An interspace is formed between the removable sheet and the flexible board. An outer conductive layer is formed on the copper foil. A removing region of the outer conductive layer corresponding to the folding region and the removable sheet is removed.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: September 1, 2020
    Assignees: Avary Holding (Shenzhen) Co., Limited., HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd.
    Inventors: Biao Li, Wei-Xiang Li, Peng He, Mei-Hua Huang, Xiao-Wei Kang, Meng-Lu Jia
  • Patent number: 10759658
    Abstract: In described examples, a first metal layer is arranged along a periphery of a cavity to be formed between a first substrate and a second substrate. A second metal layer is arranged adjacent to the first metal layer, where the second metal layer includes a cantilever. The cantilever is arranged to deform in response to forces applied from a contacting structure of the second substrate during bonding of the first substrate to the second substrate. The deformed cantilevered is arranged to impede contaminants against contacting an element within the cavity.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: September 1, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: John Charles Ehmke, Ivan Kmecko
  • Patent number: 10751976
    Abstract: A resin-clad metal foil which enables a reduction in fluidity of a resin during molding and a reduction in extrusion of the resin while maintaining good adhesiveness, bendability, thermal resistance, and circuit filling property. A first insulating layer includes a polyimide resin layer, a polyamideimide resin layer, a liquid crystal polymer resin layer, a fluororesin layer, or a polyphenylene ether resin layer and a second insulating layer includes a polyolefin resin layer in a semi-cured state are disposed in this order on a metal foil. The polyolefin resin layer contains a component representing a polyolefin-based elastomer and a component representing a thermosetting resin. The percentage by mass of the component in the polyolefin resin layer ranges from 50 wt. % to 95 wt. %.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: August 25, 2020
    Assignees: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD., TOMOEGAWA CO., LTD.
    Inventors: Yohsuke Ishikawa, Yoshiaki Esaki, Takayoshi Ozeki, Jun Tochihira, Ryu Harada
  • Patent number: 10741518
    Abstract: A semiconductor package includes: a redistribution substrate; a semiconductor chip on the redistribution substrate; and an external terminal on a bottom surface of the redistribution substrate, wherein the redistribution substrate comprises: a first insulating layer including a first opening; a second insulating layer on the first insulating layer and including a second opening, wherein the second opening is positioned in the first opening in a plan view; a first barrier metal layer disposed along a sidewall of the first opening and along a sidewall of the second opening; a first redistribution conductive pattern on the first barrier metal layer; a third insulating layer on a bottom surface of the first insulating layer; and a pad penetrating the third insulating layer and electrically connecting to the first redistribution conductive pattern, wherein the external terminal is provided on the pad, wherein the second insulating layer at least partially covers a chip pad of the semiconductor chip, and the second
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: August 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youn Ji Min, Seokhyun Lee, Jongyoun Kim, Kyoung Lim Suk, SeokWon Lee
  • Patent number: 10699990
    Abstract: An integrated circuit (IC) device includes an IC die and a plurality of leads. Each lead includes an unplated proximal end including a first material, and an unplated distal end including the first material. A plated bond wire portion extends between the proximal and distal ends and includes the first material and a plating of a second material thereon. A plurality of bond wires extend between the IC die and the plated bond wire portions of the leads. An encapsulation material surrounds the IC die and bond wires so that the unplated proximal end and plated bond wire portion of each lead are covered by the encapsulation material.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: June 30, 2020
    Assignee: STMicroelectronics SDN BHD
    Inventor: Cheeyang Ng
  • Patent number: 10674615
    Abstract: A method for manufacturing a wiring board includes preparing a core substrate having first and second surfaces, forming a first build-up structure including interlayer insulating layers and conductor layers on the first surface of the substrate, and forming a second build-up structure including interlayer insulating layers and one or more conductor layers on the second surface of the substrate. The forming of the first structure includes laminating the insulating layers and metal layers on first surface side of the substrate and forming the conductor layers from all of the metal layers on the first surface side, and the forming of the second structure includes laminating the insulating layers and metal layers on second surface side of the substrate, forming the one or more conductor layers from one or more of the metal layers on the second surface side, and entirely removing the other metal layers on the second surface side.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: June 2, 2020
    Assignee: IBIDEN CO., LTD.
    Inventor: Naoki Kurahashi
  • Patent number: 10651320
    Abstract: A method of manufacturing a circuit board includes: forming a plurality of metal electrodes so as to be separated from each other on a holding sheet by cutting a metal foil held on the holding sheet to remove a portion of the metal foil; forming adhesive layers on surfaces of the plurality of metal electrodes; adhering the adhesive layers to a base material by closely contacting the adhesive layers with the base material; and transcribing the adhesive layers and the plurality of metal electrodes onto the base material by detaching the holding sheet from the plurality of metal electrodes.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: May 12, 2020
    Assignee: DSM IP ASSETS B.V.
    Inventors: Koichi Kumai, Ryuji Ueda, Kentaro Kubota, Shigeki Kudo, Minoru Kawasaki
  • Patent number: 10651785
    Abstract: A photovoltaic assembly comprising; (a) at least two photovoltaic components that are adjacent to each other in a first direction, each photovoltaic component comprising (i) a partial recess in communication with the partial recess in an adjacent photovoltaic component and (ii) one or more connector receptors aligned in a second direction which is non-parallel to the first direction; (b) a connector located at feast partially in the partial recess of the photovoltaic component and at least partially in the partial recess of the adjacent photovoltaic component so that the connector connects the photovoltaic component to the adjacent photovoltaic component, the connector comprising: (i) a flexible housing having a first end and a second end; (ii) one or more connection ports at the first end; (iii) one or more connection ports at the second end; and (iv) one more flexible electrical conductors that extend from the one or more connection ports at the first end to the one or more connection ports at the second en
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: May 12, 2020
    Assignee: DOW GLOBAL TECHNOLOGIES LLC
    Inventors: James R. Keenihan, Leonardo C. Lopez, Joseph A. Langmaid, Shane Washburn, Darius Eghbal, Vijay Karthik Koneru, Kelvin L. Leung
  • Patent number: 10642399
    Abstract: A display device is disclosed. In one aspect, the display device includes a substrate including a display area and a non-display area adjacent to the display area and a display member formed over the substrate in the display area. The display device also includes an encapsulation layer formed over the display member and encapsulating the display member together with the substrate and a plurality of first touch lines formed over the encapsulation layer in the display area. The first touch lines extend in a first direction. The display device further includes a plurality of second touch lines formed on the same layer as the first touch lines in the display area. The second touch lines extend in the first direction and are spaced apart from the first touch lines.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: May 5, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yong-Hwan Park, Jong Seok Kim, Chi Wook An, Seong Jun Lee, Sang Hyun Jun
  • Patent number: 10597500
    Abstract: An object of the invention is achieved by a method for producing a composite material, including the steps of combining a resin precursor and a reinforcing fiber and carrying out a polymerization reaction of the resin precursor. That is, a thermoplastic resin composite material having high strength can be obtained by the production method.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: March 24, 2020
    Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Shigeru Horie, Nobuhiko Matsumoto, Kousuke Ikeuchi, Masao Someya