By Forming Conductive Walled Aperture In Base Patents (Class 29/852)
  • Patent number: 10383223
    Abstract: A circuit board film-plated against corrosion of conductive traces comprises a substrate, a conductive circuit layer attached to the substrate, a plating film attached to outer surface of the conductive circuit layer, and a covering film. Each plating film comprises a top outer surface and a side surface. The circuit board defines at least one through hole. Each through hole passes through substrate, conductive circuit layer, and the plating film. The covering film covers the conductive circuit layer, the side surfaces, and the through holes. The conductive circuit layer and the side surfaces of the plating films are sealed against the atmosphere and cannot be corroded. A method for making the circuit board is also provided.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: August 13, 2019
    Assignees: Avary Holding (Shenzhen) Co., Limited., HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd.
    Inventors: Ning Hou, Si-Hong He, Biao Li, Mei-Hua Huang
  • Patent number: 10356906
    Abstract: A method of manufacturing a printed circuit board includes providing a printed circuit board (PCB) substrate including at least one insulating layer and first and second conductive layers separated from one another by the at least one insulating layer, forming a first via hole in the PCB substrate extending from the first conductive layer to the second conductive layer, where the first via hole is defined by a first sidewall of the PCB substrate, forming a second via hole in the PCB substrate, where the second via hole is defined by a second sidewall of the PCB substrate, and selectively plating the first sidewall and the second sidewall to form a first via and a second via, respectively, where the first via and the second via have different via sidewall thicknesses.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: July 16, 2019
    Assignee: ABB SCHWEIZ AG
    Inventor: Robert Joseph Roessler
  • Patent number: 10299376
    Abstract: A method for producing an electrical wiring member includes press-molding a composition containing a resin material and metal particles with an insulating layer, each of which is constituted by a metal particle and a surface insulating layer covering the metal particle and containing a glass material as a main material, thereby obtaining a powder-compacted layer and irradiating the powder-compacted layer with an energy beam, thereby causing the irradiated regions to exhibit electrical conductivity.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: May 21, 2019
    Assignee: Seiko Epson Corporation
    Inventors: Hidefumi Nakamura, Taku Kawasaki
  • Patent number: 10191599
    Abstract: An in-cell touch screen and a display device are provided. In the in-cell touch screens, an insulation layer, in an area that each self-capacitance electrode overlap a wire, is provided with at least a first hole that runs through the insulation layer and each self-capacitance electrode is electrically connected with a corresponding wire via a corresponding first via hole; each self-capacitance electrode, within an area overlapping other wire than the corresponding wire and at a position corresponding to the first via hole, is disposed with a second via hole that runs through the self-capacitance electrode. An orthogonal projection of a second via hole on a lower substrate covers an orthogonal projection of a first via hole on the lower substrate. The in-cell touch screen can solve a problem of uneven image display due to nonuniform distribution of via holes in an insulation layer.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: January 29, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhiying Bao, Rui Xu, Weijie Zhao, Zhenhua Lv, Yanchen Li, Xi Chen, Haisheng Wang
  • Patent number: 10170441
    Abstract: A semiconductor structure comprises: a substrate, an alignment mark, pillars, and a seal wall. The alignment mark is adjacent to a surface of the substrate. The pillars protrudes from the substrate. The seal wall protrudes from the surface of the substrate and surrounding the alignment mark. The seal wall is between the pillars and the alignment mark. The pillars is configured into at least two different groups with different average heights. The seal wall around the alignment mark can prevent the alignment mark from the coverage of the flux. Further, the seal wall can be formed with pillars at the same time, and the increased cost is limited.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Wei Wu, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin
  • Patent number: 10159142
    Abstract: A printed wiring board includes a base member that includes a ground wiring pattern and a printed wiring board reinforcing member bonded to the ground wiring pattern in a conductive state. The printed wiring board reinforcing member includes a metal base material layer and a nickel layer bonded to at least a surface on a side opposite to a side bonded to the ground wiring pattern of the metal base material layer by diffusion bonding.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: December 18, 2018
    Assignee: TATSUTA ELECTRIC WIRE & CABLE CO., LTD.
    Inventors: Yuusuke Haruna, Hiroshi Tajima, Masahiro Watanabe, Yukari Kobayashi, Kiyoharu Sekiguchi, Yoshihiro Hosoya
  • Patent number: 9930789
    Abstract: The steps of forming a multi-layer flexible printed circuit cable (flex circuit) with an electrical interconnection between independent conductive layers. In accordance with various embodiments, a partial aperture is formed in the flex circuit that extends through a first conductive layer and an intervening insulative layer to an underlying surface of a second conductive layer that spans the partial aperture. A solder material is reflowed within the partial aperture to electrically interconnect the first and second conductive layers.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: March 27, 2018
    Assignee: Seagate Technology LLC
    Inventor: Chau-Chin Low
  • Patent number: 9832883
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first surface finish on one or more electrical routing features located on a first side of a package substrate and on one or more lands located on a second side of the package substrate, the second side being opposite the first side of the substrate. The method may further include removing the first surface finish on the first side of the package substrate; and depositing a second surface finish on the one or more electrical routing features of the first side. The depositing of the second surface finish may be accomplished by one of a Direct Immersion Gold (DIG) process or an Organic Solderability Preservative (OSP) process. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: November 28, 2017
    Assignee: Intel Corporation
    Inventor: Qinglei Zhang
  • Patent number: 9820374
    Abstract: A apparatus comprising a printed circuit board (“PCB”). The PCB comprises a first insulating layer and a second insulating layer. The first insulating layer is made of a first material and the second insulating layer is made of a second material. The first material has a lower dissipation factor than the second material. The first material and second material have substantially similar dielectric constants.
    Type: Grant
    Filed: August 30, 2008
    Date of Patent: November 14, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Karl J. Bois, Ramon R. Campa
  • Patent number: 9795033
    Abstract: A three-dimensional structure in which a wiring is provided on a surface is provided. At least a part of the surface of the three-dimensional structure includes an insulating layer containing filler. A recessed gutter for wiring is provided on the surface of the three-dimensional structure, and at least a part of a wiring conductor is embedded in the recessed gutter for wiring.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: October 17, 2017
    Assignee: PANASONIC CORPORATION
    Inventors: Shingo Yoshioka, Hiroaki Fujiwara
  • Patent number: 9704842
    Abstract: An interposer having a multilayered conductive pattern portion that is constructed by repeating the direct printing on a carrier of one or more conductive pattern layers and application of one or more insulating layers between the printed conductive pattern layers is described. Also, a method for manufacturing the interposer, a semiconductor package using the interposer, and a method for fabricating the semiconductor package are described.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: July 11, 2017
    Assignee: Amkor Technology, Inc.
    Inventors: DongHoon Lee, DoHyung Kim, JungSoo Park, SeungChul Han, JooHyun Kim, David Jon Hiner, Ronald Patrick Huemoeller, Michael G. Kelly
  • Patent number: 9668361
    Abstract: A printed wiring board includes an insulative resin substrate having a penetrating hole, a first conductive layer formed on first surface of the substrate, a second conductive layer formed on second surface of the substrate, and a through-hole conductor formed in the hole such that the conductor is connecting the first and second conductive layers. The conductor has a seed layer on inner wall of the hole, a laminated plated layer on the seed layer and a filled plated layer on the laminated layer, the laminated layer is formed such that the laminated layer is closing center portion of the hole and forming recess at end of the hole, the filled layer is formed such that the filled layer is filling the recess, and the laminated layer includes multiple electrolytic plated films laminated along the seed layer and each having thickness which is less at edge than at center.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: May 30, 2017
    Assignee: IBIDEN CO., LTD.
    Inventor: Kazuki Kajihara
  • Patent number: 9635761
    Abstract: A printed circuit board, and a method of fabricating the printed circuit board is disclosed. The printed circuit board includes at least one coaxial via. A hollow via is disposed in the printed circuit board. A metal sleeve is formed around the circumference of said hollow via. An inner conductive path is disposed in the hollow via. Additionally, an insulating material is disposed in the hollow via, between the conducting path and the metal sleeve. The conductive path is used to connect signal traces disposed on two different layers of the printed circuit board. In some embodiments, these signal traces carry signals having a frequency above 1 GHz, although the disclosure is not limited to this embodiment.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: April 25, 2017
    Assignee: Massachusetts Institute of Technology
    Inventors: Glenn A. Brigham, Richard J. Stanley, Bradley Thomas Perry, Patrick J. Bell
  • Patent number: 9615463
    Abstract: Conductive patterns and methods of using and printing such conductive patterns are disclosed. In certain examples, the conductive patterns may be produced by disposing a conductive material between supports on a substrate. The supports may be removed to provide conductive patterns having a desired length and/or geometry.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: April 4, 2017
    Inventors: Oscar Khaselev, Nitin Desai, Michael T. Marczi, Bawa Singh
  • Patent number: 9565749
    Abstract: An obfuscated radio frequency circuit may be manufactured to include a metallization layer, and a dielectric layer under the metallization layer. The dielectric layer may be made up of a plurality of dielectric substrates having different dielectric constants to obfuscate functions of the circuit.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: February 7, 2017
    Assignee: THE BOEING COMPANY
    Inventor: Robert Tilman Worl
  • Patent number: 9502363
    Abstract: Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: November 22, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael B. Vincent, Trung Q. Duong, Zhiwei Gong, Scott M. Hayes, Alan J. Magnus, Douglas G. Mitchell, Eduard J. Pabst, Jason R. Wright, Weng F. Yap
  • Patent number: 9485863
    Abstract: A fabrication method of a coreless packaging substrate is provided, including the steps of: forming an inner built-up circuit board on a carrier; removing the carrier; and symmetrically forming a first outer built-up structure and a second outer built-up structure on top and bottom surfaces of the inner built-up circuit board, respectively. The present invention effectively increases the product yield, saves the fabrication cost, and reduces wastes.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: November 1, 2016
    Assignee: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Chung W. Ho, Dyi-Chung Hu, Huan-Ling Lee, Sheng-Yuah He
  • Patent number: 9443834
    Abstract: Solid state lights (SSLs) including a back-to-back solid state emitters (SSEs) and associated methods are disclosed herein. In various embodiments, an SSL can include a carrier substrate having a first surface and a second surface different from the first surface. First and second through substrate interconnects (TSIs) can extend from the first surface of the carrier substrate to the second surface. The SSL can further include a first and a second SSE, each having a front side and a back side opposite the front side. The back side of the first SSE faces the first surface of the carrier substrate and the first SSE is electrically coupled to the first and second TSIs. The back side of the second SSE faces the second surface of the carrier substrate and the second SSE is electrically coupled to the first and second TSIs.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: September 13, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Casey Kurth, Kevin Tetz
  • Patent number: 9420706
    Abstract: In a method of manufacturing a multilayer board, including: a drilling step for forming a via hole through a pre-preg by laser beam machining, a step of filling the via hole with conductive paste containing a resin component and metal powder, and a step of arranging copper layers or copper layer portions of patterned boards on and under the filled conductive paste and pressing the same, a multilayer printed wiring board superior in conductivity and long-term stability is obtained by using alloying paste as the conductive paste in which at least part of the metal powder is melted and the metal powders adjacent to each other are alloyed, using a pre-preg having a ratio A/B of at least 10 before subjected to preheating, where A is a storage modulus at an inflection point where the storage modulus changes from increasing to decreasing and B is a storage modulus at an inflection point where the storage modulus changes from decreasing to increasing in a temperature profile rising from 60° C. to 200° C.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: August 16, 2016
    Assignee: Tatsuta Electric Wire & Cable Co., Ltd.
    Inventors: Norihiro Yamaguchi, Hiroaki Umeda, Ken Yukawa
  • Patent number: 9420683
    Abstract: A substrate embedding a passive element includes a first conductor pattern layer disposed on a lower surface thereof and a second conductor pattern layer disposed on an upper surface thereof; a first via electrically connecting between the passive element and the first conductor pattern layer; and a second via electrically connecting between the passive element and the second conductor pattern layer, in which a volume of the first via is larger than that of the second via.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: August 16, 2016
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Doo Hwan Lee, Yul Kyo Chung, Yee Na Shin, Seung Eun Lee
  • Patent number: 9406532
    Abstract: A method for making an interconnection component is disclosed, including forming a plurality of metal posts extending away from a reference surface. Each post is formed having a pair of opposed end surface and an edge surface extending therebetween. A dielectric layer is formed contacting the edge surfaces and filling spaces between adjacent ones of the posts. The dielectric layer has first and second opposed surfaces adjacent the first and second end surfaces. The dielectric layer has a coefficient of thermal expansion of less than 8 ppm/° C. The interconnection component is completed such that it has no interconnects between the first and second end surfaces of the posts that extend in a lateral direction. First and second pluralities of wettable contacts are adjacent the first and second opposed surfaces. The wettable contacts are usable to bond the interconnection component to a microelectronic element or a circuit panel.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: August 2, 2016
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Ilyas Mohammed
  • Patent number: 9351407
    Abstract: A method of forming a multilayer device includes providing a core substrate having opposing first and second core surfaces and forming top and bottom inner conductive patterns on each of the first and second core surfaces, respectively. A first dielectric layer is formed on the first core surface, and the top inner conductive pattern. A second dielectric layer is formed on the second core surface, and the bottom inner conductive pattern. The first and second dielectric layers are laminated with top and bottom outer conductive layers, respectively. A first via is provided through the core substrate extending from the top outer conductive layer to the bottom outer conductive layer. The first via is filled with solder. Magnetic particles are attracted by a magnetic force into the first via.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: May 24, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Boon Yew Low
  • Patent number: 9315014
    Abstract: In a screen printing apparatus, a squeegee is slid on a mask contacting a board to print paste onto the board via pattern holes formed in the mask. The screen printing apparatus includes: a box-like member including a top-plate portion in which first suction hole and a second section hole are formed and which is allowed to contact the board; a blower suction pipe communicating with an internal space of the box-like member and extending outside the box-like member; a blower suction source sucking air through the blower suction pipe to generate a blower suction force in the first suction hole; a vacuum suction pipe connected to the second suction hole and extending through the internal space to an outside of the box-like member; and a vacuum pressure supplying device supplying a vacuum pressure to the second suction hole through the vacuum suction pipe.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: April 19, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Isao Horie, Yusuke Sueyasu
  • Patent number: 9318466
    Abstract: A methodology for a thin, flexible substrate having integrated passive circuit elements, and the resulting device are disclosed. Embodiments may include integrating one or more passive circuit components on a first or second surface of a substrate, and interconnecting one or more integrated circuit (IC) dies on a second surface of the interposer to the one or more passive circuit components with one or more metal-filled vias between the first and second surfaces, the first and second surfaces being opposite surfaces of the substrate.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: April 19, 2016
    Assignee: GlobalFoundries Inc.
    Inventors: Saket Chadda, Ramakanth Alapati, Adam Beece
  • Patent number: 9320154
    Abstract: An electrode connected to a TH pad requiring electric conduction is formed on a bonded surface of a first multilayer substrate having piercing TH to form a solder bump on the electrode. An electrode connected to the TH pad is formed on a bonded surface of a second multilayer substrate to be bonded having a piercing TH at a position opposite the electrode formed on the first multilayer substrate to form a solder bump on the electrode. A three-layered sheet is formed by applying an adhesive as a resin material that is not completely cured to both surfaces of a core material as the cured resin, and has holes at positions corresponding to the TH and the solder bump, respectively. The first and the second multilayer substrates are then laminated having the bonded surfaces facing each other while having the three-layered sheet positioned and interposed therebetween, and batch thermocompression bonded.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: April 19, 2016
    Assignee: HITACHI, LTD.
    Inventors: Akira Soeda, Chiko Yorita, Shinichirou Tooya, Takayuki Ono, Mitsuru Takahira, Yuuichi Sekino, Akira Goto, Yoshimasa Tashiro, Hiroyuki Doi, Tsutomu Sakamoto
  • Patent number: 9314764
    Abstract: The invention features methods of making devices, or “platens”, having a high-density array of through-holes, as well as methods of cleaning and refurbishing the surfaces of the platens. The invention further features methods of making high-density arrays of chemical, biochemical, and biological compounds, having many advantages over conventional, lower-density arrays. The invention includes methods by which many physical, chemical or biological transformations can be implemented in serial or in parallel within each addressable through-hole of the devices. Additionally, the invention includes methods of analyzing the contents of the array, including assaying of physical properties of the samples.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: April 19, 2016
    Assignee: Life Technologies Corporation
    Inventors: Robert Hess, John Linton, Tanya S. Kanigan, Colin Brenan, Can Ozbal
  • Patent number: 9269602
    Abstract: A fabrication method of a wafer level semiconductor package includes: forming on a carrier a first dielectric layer having first openings exposing portions of the carrier; forming a circuit layer on the first dielectric layer, a portion of the circuit layer being formed in the first openings; forming on the first dielectric layer and the circuit layer a second dielectric layer having second openings exposing portions of the circuit layer; forming conductive bumps in the second openings; mounting a semiconductor component on the conductive bumps; forming an encapsulant for encapsulating the semiconductor component; and removing the carrier to expose the circuit layer. By detecting the yield rate of the circuit layer before mounting the semiconductor component, the invention avoids discarding good semiconductor components together with packages as occurs in the prior art, thereby saving the fabrication cost and improving the product yield.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: February 23, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventor: Lu-Yi Chen
  • Patent number: 9265146
    Abstract: A method for manufacturing a multi-layer circuit board includes steps of: providing three copper clad laminates; forming trace layers in each copper clad laminate by selectively removing portions of copper layer of each copper clad laminate to obtain three first circuit substrates; laminating a dielectric layer on two of the first circuit substrates to obtain two second circuit substrates; forming a metal bump on the trace layer he other one of the three first circuit substrate to obtain a third circuit substrate; stacking and laminating the third circuit substrate between the two second circuit substrate to obtain a multi-layer circuit board.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: February 16, 2016
    Assignee: Zhen Ding Technology Co., Ltd.
    Inventors: Che-Wei Hsu, Shih-Ping Hsu
  • Patent number: 9225103
    Abstract: A connector comprises a connector housing receiving therein a terminal fitting connected to an electrode of a connector-mounting portion and an electrical wire at an end of which the terminal fitting is provided; a cap for the connector housing; and a packing for the cap. The packing includes a mushroom-like locking projection with an enlarged end portion. The cap includes a locking hole into which the end portion of the locking projection is inserted so that the end portion is placed in locking engagement with the locking hole.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: December 29, 2015
    Assignee: Yazaki Corporation
    Inventor: Kenichi Okamoto
  • Patent number: 9210809
    Abstract: Embodiments are directed to semiconductor packaging having reduced sized plated through hole (PTH) pads by eliminating the margin of the pad-to-PTH alignment and enabling finer traces on the core of the substrate.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: December 8, 2015
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Mihir Roy
  • Patent number: 9184527
    Abstract: A socket housing and method of making the socket housing. A plurality of dielectric layers are printed with a plurality of recesses on a substrate. The dielectric layers include at least two different dielectric materials. A sacrificial material is printed in the recesses. The assembly is removed from the substrate and the sacrificial material is removed from the recesses. At least one contact member is located in a plurality of the recesses. Distal ends of the contact members are adapted to electrically couple with circuit members.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: November 10, 2015
    Assignee: HSIO TECHNOLOGIES, LLC
    Inventor: James Rathburn
  • Patent number: 9184123
    Abstract: Techniques and structures for achieving a more uniform current density in solder ball contact areas for a ball-grid-array semiconductor package are presented. Current density may be made more uniform by introducing electrically non-conductive regions into one or more areas that form a dedicated power rail within a package substrate that is configured to be connected with a die. Additionally or alternatively, the number of ?vias that connect each solder ball contact area with conductive areas within the package substrate may be individually tailored based on the desired current density at each solder ball contact area.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: November 10, 2015
    Assignee: Altera Corporation
    Inventor: Hui Liu
  • Patent number: 9179546
    Abstract: An information handling system circuit board interfaces storage device surface connectors and storage device controllers disposed on opposing sides by coupling a first circuit board portion having a controller press in connector to a second circuit board portion having plural surface connectors. The first and second circuit board portions couple to each other with an adhesive activated by curing. Resistant ink is printed over openings of the first circuit board portion where adhesive is applied in order to prevent the adhesive from flowing into the openings at or before the curing of the adhesive.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: November 3, 2015
    Assignee: Dell Products L.P.
    Inventors: Kevin W. Mundt, Jason D. Adrian
  • Patent number: 9179556
    Abstract: A conductive via and method of forming a conductive via in a multilayer printed circuit board are disclosed. A hole is drilled into a printed circuit board that is reinforced with glass fibers, wherein the hole extends between two conductive elements on different layers of the printed circuit board and cuts through a portion of the glass fibers. A tungsten nitride layer is then deposited on the walls of the hole, wherein the tungsten nitride layer has a thickness between 1.5 nanometers and 20 nanometers. A copper layer is deposited over the tungsten nitride layer, wherein the copper and tungsten nitride form a conductive via that provides an electrically conductive pathway between the two conductive elements, and wherein the tungsten nitride layer isolates the copper layer from the glass fibers.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: November 3, 2015
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Joseph Kuczynski, Melissa K. Miller, Heidi D. Williams, Jing Zhang
  • Patent number: 9156111
    Abstract: Provided are a lead-free solder, a solder paste, and a semiconductor device, and more particularly, a lead-free solder that includes Cu in a range from about 0.1 wt % to about 0.8 wt %, Pd in a range from about 0.001 wt % to about 0.1 wt %, Al in a range from about 0.001 wt % to about 0.1 wt %, Si in a range from about 0.001 wt % to about 0.1 wt %, and Sn and inevitable impurities as remainder, a solder paste and a semiconductor device including the lead-free solder. The lead-free solder and the solder paste are environment-friendly and have a high high-temperature stability and high reliability.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: October 13, 2015
    Assignees: MK ELECTRON CO., LTD., HOSEO UNIVERSITY ACADEMIC COOPERATION FOUNDATION, KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, KOREA INSTITUTE OF INDUSTRIAL TECHNOLOGY, KOREA ELECTRONICS TECHNOLOGY INSTITUTE
    Inventors: Sung Jae Hong, Keun Soo Kim, Chang Woo Lee, Jung Hwan Bang, Yong Ho Ko, Hyuck Mo Lee, Jae Won Chang, Ja Hyun Koo, Jeong Tak Moon, Young Woo Lee, Won Sik Hong, Hui Joong Kim, Jae Hong Lee
  • Patent number: 9148956
    Abstract: A base substrate includes an insulator board comprising through holes penetrating between two opposed principal surfaces, penetrating electrodes provided within the through holes, and intermediate layers sandwiched between inner surfaces of the through holes and the penetrating electrodes and having surfaces with smaller concavities and convexities than those of the inner surfaces at the penetrating electrode sides.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: September 29, 2015
    Assignee: Seiko Epson Corporation
    Inventor: Naohiro Nakagawa
  • Patent number: 9136169
    Abstract: A method is described for producing an electrical feedthrough in a substrate, and a substrate having an electrical feedthrough. The method has the following operations of forming the electrical feedthrough so that it extends through the substrate from the front side to the back side of the substrate, forming a first closing layer on a front side of the substrate, forming an annular isolation trench in the substrate which encloses the electrical feedthrough, using an etching process starting from the back side of the substrate, the etching process terminating at the first closing layer, and closing off the annular isolation trench in the substrate by forming a second closing layer on the back side of the substrate.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: September 15, 2015
    Assignee: ROBERT BOSCH GMBH
    Inventor: Jochen Reinmuth
  • Patent number: 9136214
    Abstract: A multilayer wiring board has a high degree of freedom of wiring design and can realize high-density wiring, and a method to simply manufacture the multilayer wiring board. A core substrate with two or more wiring layers provided thereon through an electrical insulating layer. The core substrate has a plurality of throughholes filled with an electroconductive material, and the front side and back side of the core substrate have been electrically conducted to each other by the electroconductive material. The throughholes have an opening diameter in the range of 10 to 100 ?m. An insulation layer and an electroconductive material diffusion barrier layer are also provided, and the electroconductive material is filled into the throughholes through the insulation layer. A first wiring layer provided through an electrical insulating layer on the core substrate is connected to the electroconductive material filled into the throughhole through via.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: September 15, 2015
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventors: Shigeki Chujo, Koichi Nakayama
  • Patent number: 9125314
    Abstract: A printed circuit board includes: an insulating substrate, and a patterned conductive layer having a signal line and fixed on the insulating substrate, where signal lines on different planes of the patterned conductive layer are electrically connected to a via hole through a pad. An inner wall of the via hole is formed of a conductive bar and an insulating bar that penetrate the via hole; the pad is at an edge of the via hole and is connected to the conductive bar; the pad has an unclosed structure. In the printed circuit board according to the present invention, the size of the pad is significantly reduced by arranging the pad at partial edge of the via hole, thereby effectively improving a layout density of the patterned conductive layer, hence reducing the size of the printed circuit board, and satisfying the market demand for smaller electronic products.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: September 1, 2015
    Assignee: CELESTICA TECHNOLOGY CONSULTANCY (SHANGHAI) CO. LTD.
    Inventor: Li Juan Qu
  • Patent number: 9107314
    Abstract: A method of manufacturing a wiring board includes: forming an outer through hole in a core substrate; filling the outer through hole with an insulation resin; forming a first conductive layer on a surface of the insulation resin at a portion where a core connecting via is formed; forming a land around the first conductive layer; laminating the wiring layer on the core substrate after the forming of the first conductive layer and the forming of the land; forming an inner through hole having a smaller diameter than that of the outer through hole and penetrating through the core substrate and the wiring layer so as to penetrate through the insulation resin; and coating a first conductive film on an inner wall surface of the inner through hole, in which the core substrate and the first conductive film are electrically connected through the first conductive layer and the land.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: August 11, 2015
    Assignee: FUJITSU LIMITED
    Inventor: Hideaki Yoshimura
  • Patent number: 9098646
    Abstract: A printed circuit board (PCB) design system and method allows for PCB layouts that can be manufactured using a PCB manufacturing technology selected from multiple PCB manufacturing technologies with minimal or no modification to the PCB layout. In accordance with the exemplary embodiment, the PCB layout is designed to meet all design rules of a High Density Interconnect (HDI) manufacturing technology while minimizing requirements for layout changes when the PCB is manufactured using an Interstitial Via Hole (IVH) manufacturing technology. An IVH PCB includes a plurality of vias positioned within reserved via areas that form connections between at least some conductive elements on the board layers. The conductive elements and the plurality of vias form a layout such that a majority of reserved via areas, of all of the reserved via areas on the printed circuit board, are adequate to accommodate mechanically drilled vias manufactured with the HDI manufacturing technology.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: August 4, 2015
    Assignee: KYOCERA Corporation
    Inventors: Mumtaz Y. Bora, Ronald T. Mora
  • Patent number: 9095083
    Abstract: A manufacturing method for a multi-layer circuit board includes the following steps. Firstly, a substrate having a first via penetrating the substrate is provided. Next, a patterned circuit layer is formed on a surface of the substrate by using the first via as an alignment target. The first patterned circuit layer includes a first concentric-circle pattern surrounding the first via. Next, a first stacking layer is formed on the surface. Then, a first through hole penetrating regions where a first concentric circle from the center of the concentric-circle pattern is orthogonally projected on the first stacking layer and the substrate is formed. Next, a second stacking layer is formed on the first stacking layer. Afterward, a second through hole penetrating regions where a second concentric circle from the center of the concentric-circle pattern is orthogonally projected on of the first, the second stacking layers and the substrate is formed.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: July 28, 2015
    Assignee: Unimicron Technology Corp.
    Inventors: Pei-Chang Huang, Cheng-Po Yu, Han-Pei Huang
  • Patent number: 9095068
    Abstract: Disclosed herein is a circuit board including: a base substrate including a via for power and a via pad for power connected to the via for power; and an insulating layer formed on the base substrate and including a dummy pattern formed in a region facing the via pad for power.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: July 28, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Seung Wook Park, Chang Bae Lee, Christian Romero, Mi Jin Park
  • Patent number: 9087777
    Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: July 21, 2015
    Assignee: UNITED TEST AND ASSEMBLY CENTER LTD.
    Inventors: Yongbo Yang, Antonio Jr. Bambalan Dimaano, Chun Hong Wo
  • Patent number: 9089041
    Abstract: A wiring board includes an electrode pad having a first surface and a second surface located on an opposite side from the first surface, a conductor pattern connected to the first surface of the electrode pad, and an insulator layer embedded with the electrode pad and the conductor pattern. The insulator layer covers an outer peripheral portion of the second surface of the electrode pad.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: July 21, 2015
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Kotaro Kodani, Kentaro Kaneko, Kazuhiro Kobayashi
  • Patent number: 9060430
    Abstract: A method includes forming a patterned sacrificial layer on a first carrier and a patterned trace layer on the patterned sacrificial layer. The patterned sacrificial layer and the patterned trace layer are laminated to a dielectric material. The first carrier and the patterned sacrificial layer are removed creating sacrificial layer gaps above the patterned trace layer. The sacrificial layer gaps are filled with a trace layer isolation dielectric material. Shield trenches are laser-ablated within the dielectric material and on opposite sides of a signal trace of the patterned trace layer. The shield trenches are filled with an electrically conductive material to form shield walls. The electrically conductive material is patterned to form a shield top. The shield top, the shield walls, and a second carrier form a bias shield around the signal trace.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: June 16, 2015
    Inventors: Ronald Patrick Huemoeller, Sukianto Rusli, Nozad Karim
  • Patent number: 9055702
    Abstract: One embodiment of the invention comprises an improved method for making a via structure for use in a printed circuit board (PCB). The via allows for the passage of a signal from one signal plane to another in the PCB, and in so doing transgresses the power and ground planes between the signal plane. To minimize EM disturbance between the power and ground planes, signal loss due to signal return current, and via-to-via coupling, the via is shielded within two concentric cylinders, each coupled to one of the power and ground planes.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: June 9, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Shiyou Zhao, Houfei Chen, Hao Wang
  • Patent number: 9038266
    Abstract: A multilayer printed wiring board including a first interlayer resin insulation layer, a first conductive circuit formed on the first interlayer resin insulation layer, a second interlayer resin insulation layer formed on the first interlayer resin insulation layer and the first conductive circuit and having an opening portion exposing a portion of the first conductive circuit, a second conductive circuit formed on the second interlayer resin insulation layer, a via conductor formed in the opening portion of the second interlayer resin insulation layer and connecting the first conductive circuit and the second conductive circuit, and a coating layer having a metal layer and a coating film and formed between the first conductive circuit and the second interlayer resin insulation layer. The metal layer is formed on the surface of the first conductive circuit and the coating film is formed on the metal layer.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: May 26, 2015
    Assignee: IBIDEN CO., LTD.
    Inventors: Sho Akai, Tatsuya Imai, Iku Tokihisa
  • Publication number: 20150135527
    Abstract: A packaging substrate having an embedded through-via interposer is provided, including an encapsulant layer, a through-via interposer embedded in the encapsulant layer and having a plurality of conductive through-vias therein, a redistribution layer embedded in the encapsulant layer and formed on the through-via interposer so as to electrically connect with first end surfaces of the conductive through-vias, and a built-up structure formed on the encapsulant layer and the through-via interposer for electrically connecting second end surfaces of the conductive through-vias.
    Type: Application
    Filed: January 22, 2015
    Publication date: May 21, 2015
    Inventors: Dyi-Chung Hu, Tzyy-Jang Tseng
  • Publication number: 20150136457
    Abstract: An interposer includes an insulating substrate, a photosensitive dielectric film, a conductive layer, and a conductive via. The insulating substrate includes a bottom surface and a top surface, and defines a receiving through hole extending through the bottom surface and the top surface. The photosensitive dielectric film is mounted on the bottom surface. The photosensitive dielectric film defines a through hole spatially corresponding to and communicating with the receiving through hole. The conductive layer is mounted on an end of the photosensitive dielectric film away from the insulating substrate. The conductive layer covers an end of the through hole. The conductive via is received in the receiving through hole and the through hole. The conductive via contacts and electrically connects to the conductive layer.
    Type: Application
    Filed: January 8, 2014
    Publication date: May 21, 2015
    Applicant: ZHEN DING TECHNOLOGY CO., LTD.
    Inventor: TAEKOO LEE