By Forming Conductive Walled Aperture In Base Patents (Class 29/852)
  • Patent number: 11155007
    Abstract: Solution casting a nanostructure. Preparing a template by ablating nanoholes in a substrate using single-femtosecond laser machining. Replicating the nanoholes by applying a solution of a polymer and a solvent into the template. After the solvent has substantially dissipated, removing the replica from the substrate.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: October 26, 2021
    Assignee: ULTRA SMALL FIBERS, LLC
    Inventors: William Hudson Hofmeister, Alexander Yuryevich Terekhov, Jose Lino Vasconcelos da Costa, Kathleen Stacia Lansford, Deepak Rajput, Lloyd M. Davis
  • Patent number: 11129275
    Abstract: A power supply comprises a main circuit board and a multilayer power transmission board electrically coupled to the main circuit board. The multilayer board includes a conductive neutral layer having an inner side, a conductive line layer having an inner side facing the inner side of the conductive neutral layer, and a dielectric medium positioned between the conductive neutral layer and the conductive line layer. The power supply also comprises a first conductive outer layer positioned adjacently to an outer side of the conductive neutral layer, a second conductive outer layer positioned adjacently to an outer side of the conductive line layer, and a conductive plating material positioned within a slot formed in the multilayer power transmission board and covering an interior portion of the multilayer power transmission board facing the slot. The conductive plating material electrically couples the first and second conductive outer layers.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: September 21, 2021
    Assignee: Astec International Limited
    Inventors: Prabou Ranganathan, Norman Oliva
  • Patent number: 11101235
    Abstract: A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: August 24, 2021
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventor: Lu-Yi Chen
  • Patent number: 11096290
    Abstract: The present invention is notably directed to a printed circuit board, or PCB. This PCB has two main surfaces, each delimited by lateral edges, as well as lateral surfaces, each meeting each of the two main surfaces at one lateral edge. The present PCB further comprises a row of solder pads, which extends along a lateral edge of the PCB. Each solder pad is formed directly at the lateral edge and/or directly on a lateral surface (meeting one of the two main surfaces at said lateral edge). I.e., each pad interrupts a lateral edge and/or an adjoining lateral surface. One or more chips, e.g., memory chips, can be mounted on such a PCB to form an IC package. The above solder pad arrangement allows particularly dense arrangements of IC packages to be obtained. The present invention is further directed to related devices and methods of fabrication thereof.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: August 17, 2021
    Assignee: International Business Machines Corporation
    Inventors: Thomas Brunschwiler, Andreas Doering, Ronald P. Luijten, Stefano S. Oggioni, Joerg-Eric Sagmeister, Patricia M. Sagmeister, Martin Schmatz
  • Patent number: 11081448
    Abstract: Microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that, provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Rahul N. Manepalli, Praneeth Akkinepally, Jesse C. Jones, Yosuke Kanaoka, Dilan Seneviratne
  • Patent number: 11056825
    Abstract: An insulator for a bus connector arrangement including a first layer defining at least one first aperture, a first annular protrusion emanating from the first layer at one first aperture, a second layer defining at least one second aperture configured to align with each of the at least one first apertures, and at least one second annular protrusion emanating from the second layer at each of the at least one second apertures.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: July 6, 2021
    Assignee: Hamilton Sundstrand Corporation
    Inventor: Robert H. Dold
  • Patent number: 11037803
    Abstract: A method for making a redistribution circuit structure provides a substrate and forms a peelable layer on the substrate. A metal layer is formed on a surface of the peelable layer, the metal layer including a controlling circuit including at least two spaced units. A first photoresist layer is formed on a portion of the surface of the peelable layer and an insulating layer is applied to completely cover the first photoresist layer and the controlling circuit. Through holes are defined in the insulating layer to partially expose the controlling circuit and a seed layer applied on the insulating layer. A block layer is laid to divide the seed layer into multiple sections and electroplating in each section on a portion of the seed layer is applied to form a plating layer with better uniformity of thickness across all sections.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: June 15, 2021
    Assignee: Century Technology (Shenzhen) Corporation Limited
    Inventors: Yung-Fu Lin, Po-Liang Chen
  • Patent number: 11026335
    Abstract: A wiring board manufacturing method includes: forming a first groove structure in a first principal surface of a base by scanning with laser light in a first irradiation pattern such that the first groove structure has a first width; irradiating an inside of the first groove structure with laser light in a second irradiation pattern that is different from the first irradiation pattern to form recessed portions inside the first groove structure; and forming a first wiring pattern by filling the first groove structure with a first electrically-conductive material to form a first wiring pattern whose shape matches with a shape of the first groove structure in a top view.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: June 1, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Rie Maeda, Masaaki Katsumata
  • Patent number: 10935574
    Abstract: A probe card assembly is provided as follows. A tile fixing substrate is disposed on a printed circuit board. A plurality of ceramic tiles is detachably attached to the tile fixing substrate. Each of the plurality of ceramic tiles comprises a plurality of probes. A plurality of alignment marks is fixed to the tile fixing substrate.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: March 2, 2021
    Inventors: Gyu Yeol Kim, Yu Kyum Kim, Jae Won Kim
  • Patent number: 10888000
    Abstract: A manufacturing method of a circuit board includes the following steps. A conductive plate is provided. The conductive plate is patterned to form ducts. The patterned conductive plate is laminated with a core dielectric layer. The lamination leaves exposed a bottom surface of the patterned conductive plate. Through holes are opened in portions of the core dielectric layer within the ducts. A conductive material is formed in the through holes and over the core dielectric layer to produce a metallization layer electrically insulated from the patterned conductive plate. Dielectric layers and conductive layers are alternately stacked on an upper surface of the core dielectric layer. The conductive layers are electrically connected to the metallization layer.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: January 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Yi Wu, Chien-Hsun Lee, Chen-Hua Yu, Chung-Shi Liu
  • Patent number: 10886230
    Abstract: A fan-out semiconductor package is provided. A semiconductor chip is disposed in a through hole of a first connection member. At least a portion of the semiconductor chip is encapsulated by an encapsulant. A second connection member including a redistribution layer is formed on an active surface of the semiconductor chip. An external connection terminal having excellent reliability is formed on the encapsulant.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: January 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyoung Joon Kim, Doo Hwan Lee
  • Patent number: 10834830
    Abstract: Creating in-via routing with a light pipe is disclosed. A resist layer is applied over a layer of conductive material provided in a via. A light pipe is inserted into the via. The surface of the light pipe includes at least one masked portion and at least one unmasked portion. A portion of the resist layer is exposed with light emitted from the unmasked portions of the light pipe. Portions of the conductive layer corresponding to the exposed portion of the resist layer are then removed to create the in-via routing.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Mark J. Jeanson, Darryl Becker, Gerald Bartley, Matthew S. Doyle
  • Patent number: 10820423
    Abstract: A fabrication method of a circuit includes drilling holes in a substrate, so as to form a plurality of first opening holes and second opening holes in the substrate. A cover film is attached onto the substrate, so as to cover the first opening holes and the second opening holes. A portion of the cover film covering the first opening holes is removed, so as to expose the first opening holes. The first opening holes are filled.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: October 27, 2020
    Assignee: Gold Circuit Electronics Ltd.
    Inventors: Chih-Hai Yu, Kuo-Wei Lo, Cheng-Hsiao Lin
  • Patent number: 10813214
    Abstract: A method for making an interconnection component includes forming a mask layer that covers a first opening in a sheet-like element that includes a first opening extending between the first and second surfaces of the element. The element consists essentially of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. The first opening includes a central opening and a plurality of peripheral openings open to the central opening that extends in an axial direction of the central opening. A conductive seed layer can cover an interior surface of the first opening. The method further includes forming a first mask opening in at least a portion of the mask layer overlying the first opening to expose portions of the conductive seed layer within the peripheral openings; and forming electrical conductors on exposed portions of the conductive seed layer.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: October 20, 2020
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Craig Mitchell, Belgacem Haba, Ilyas Mohammed
  • Patent number: 10757818
    Abstract: A wiring board manufacturing method includes: forming a first groove structure in a first principal surface of a base by scanning with laser light in a first irradiation pattern such that the first groove structure has a first width; irradiating an inside of the first groove structure with laser light in a second irradiation pattern that is different from the first irradiation pattern to form recessed portions inside the first groove structure; and forming a first wiring pattern by filling the first groove structure with a first electrically-conductive material to form a first wiring pattern whose shape matches with a shape of the first groove structure in a top view.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: August 25, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Rie Maeda, Masaaki Katsumata
  • Patent number: 10700564
    Abstract: A method includes forming one or more cores, wherein each of the one or more cores has a cross section corresponding to a conductor to be subsequently formed, forming an insulator around the one or more cores, removing the one or more cores to expose one or more recesses within the insulator, and forming one or more conductors in at least one of the one or more recesses of the insulator such that the cross sections of the one or more conductors conform to an interior surface of the one or more recesses in the insulator.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: June 30, 2020
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Christopher Michael Calebrese, Jeffrey S. Sullivan, Qin Chen, Benjamin Hale Winkler, Kevin Warner Flanagan, Anil Raj Duggal
  • Patent number: 10622273
    Abstract: A semiconductor package includes a support member having first and second surfaces, having a cavity, and including a wiring structure, a semiconductor chip having connection pads, a connection member including a first insulating layer, a first redistribution layer on the first insulating layer, and a plurality of first vias connecting the wiring structure and the connection pads to the first redistribution layer and an encapsulant encapsulating the semiconductor chip, The wiring structure includes wiring patterns disposed on the second surface of the support member, and the first insulating layer includes a first insulating coating covering the wiring patterns and a second insulating coating disposed on the first insulating coating and having a higher level of flatness than that of the first insulating coating.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: April 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joo Young Choi, Joon Sung Kim, Young Min Kim, Da Hee Kim, Tae Wook Kim, Byung Ho Kim
  • Patent number: 10588217
    Abstract: A manufacturing method of a flexible transparent circuit includes preparing a circuit template. The method further includes using a flexible transparent polymer material to prepare a cured transparent carrier on the circuit template, wherein the cured transparent carrier has a groove circuit structure. The method includes coating a solution containing a conductive material in a groove of the cured transparent carrier. The method further includes forming a circuit with the high transparency and conductivity after the solvent is volatilized. The circuit are designed and manufactured according to the requirements, and the precision thereof is able to achieve the micron or nanometer level. The formed circuit is light. The circuit can be stretched, bended or twisted many times. The circuit has a good biological compatibility. The circuit manufactured by such method is expected to be applied in various fields such as smart contact lens, flexible transparent electron devices, electronic skins.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: March 10, 2020
    Assignee: DALIAN UNIVERSITY
    Inventors: Jing Sun, Mingfei Lang
  • Patent number: 10496915
    Abstract: A radio frequency identification (RFID) tag that includes an antenna having a spiral form disposed on a major surface of a flexible substrate is described. The RFID tag includes a first terminal disposed at a first end of the antenna and a second terminal disposed at the second end of the antenna. The RFID tag may include a pad portion along the length of the antenna between the first and second ends for mounting an integrated circuit. Except for the pad portion, a radius of curvature of the antenna along at least 90 percent of a length of the antenna between the first and second ends is greater than about 0.1 mm and less than about 10 mm.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: December 3, 2019
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: John D. Geissinger, Donald G. Peterson, Robin E. Gorrell, Howard M. Kaplan
  • Patent number: 10485110
    Abstract: An electrical connection method of a printed circuit includes overlapping a base material and a thin member in which a thin conductor is mounted, forming a through hole which passes through the base material overlapped with the thin member in the overlapping and reaches the thin conductor of the thin member, and forming a printed circuit on the base material by a screen printing method using conductive paste. The through hole formed in the forming of the through hole is filled with the conductive paste in the forming of the printed circuit.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: November 19, 2019
    Assignee: Yazaki Corporation
    Inventors: Mizuki Shirai, Hiroki Kondo
  • Patent number: 10383223
    Abstract: A circuit board film-plated against corrosion of conductive traces comprises a substrate, a conductive circuit layer attached to the substrate, a plating film attached to outer surface of the conductive circuit layer, and a covering film. Each plating film comprises a top outer surface and a side surface. The circuit board defines at least one through hole. Each through hole passes through substrate, conductive circuit layer, and the plating film. The covering film covers the conductive circuit layer, the side surfaces, and the through holes. The conductive circuit layer and the side surfaces of the plating films are sealed against the atmosphere and cannot be corroded. A method for making the circuit board is also provided.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: August 13, 2019
    Assignees: Avary Holding (Shenzhen) Co., Limited., HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd.
    Inventors: Ning Hou, Si-Hong He, Biao Li, Mei-Hua Huang
  • Patent number: 10356906
    Abstract: A method of manufacturing a printed circuit board includes providing a printed circuit board (PCB) substrate including at least one insulating layer and first and second conductive layers separated from one another by the at least one insulating layer, forming a first via hole in the PCB substrate extending from the first conductive layer to the second conductive layer, where the first via hole is defined by a first sidewall of the PCB substrate, forming a second via hole in the PCB substrate, where the second via hole is defined by a second sidewall of the PCB substrate, and selectively plating the first sidewall and the second sidewall to form a first via and a second via, respectively, where the first via and the second via have different via sidewall thicknesses.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: July 16, 2019
    Assignee: ABB SCHWEIZ AG
    Inventor: Robert Joseph Roessler
  • Patent number: 10299376
    Abstract: A method for producing an electrical wiring member includes press-molding a composition containing a resin material and metal particles with an insulating layer, each of which is constituted by a metal particle and a surface insulating layer covering the metal particle and containing a glass material as a main material, thereby obtaining a powder-compacted layer and irradiating the powder-compacted layer with an energy beam, thereby causing the irradiated regions to exhibit electrical conductivity.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: May 21, 2019
    Assignee: Seiko Epson Corporation
    Inventors: Hidefumi Nakamura, Taku Kawasaki
  • Patent number: 10191599
    Abstract: An in-cell touch screen and a display device are provided. In the in-cell touch screens, an insulation layer, in an area that each self-capacitance electrode overlap a wire, is provided with at least a first hole that runs through the insulation layer and each self-capacitance electrode is electrically connected with a corresponding wire via a corresponding first via hole; each self-capacitance electrode, within an area overlapping other wire than the corresponding wire and at a position corresponding to the first via hole, is disposed with a second via hole that runs through the self-capacitance electrode. An orthogonal projection of a second via hole on a lower substrate covers an orthogonal projection of a first via hole on the lower substrate. The in-cell touch screen can solve a problem of uneven image display due to nonuniform distribution of via holes in an insulation layer.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: January 29, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhiying Bao, Rui Xu, Weijie Zhao, Zhenhua Lv, Yanchen Li, Xi Chen, Haisheng Wang
  • Patent number: 10170441
    Abstract: A semiconductor structure comprises: a substrate, an alignment mark, pillars, and a seal wall. The alignment mark is adjacent to a surface of the substrate. The pillars protrudes from the substrate. The seal wall protrudes from the surface of the substrate and surrounding the alignment mark. The seal wall is between the pillars and the alignment mark. The pillars is configured into at least two different groups with different average heights. The seal wall around the alignment mark can prevent the alignment mark from the coverage of the flux. Further, the seal wall can be formed with pillars at the same time, and the increased cost is limited.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Wei Wu, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin
  • Patent number: 10159142
    Abstract: A printed wiring board includes a base member that includes a ground wiring pattern and a printed wiring board reinforcing member bonded to the ground wiring pattern in a conductive state. The printed wiring board reinforcing member includes a metal base material layer and a nickel layer bonded to at least a surface on a side opposite to a side bonded to the ground wiring pattern of the metal base material layer by diffusion bonding.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: December 18, 2018
    Assignee: TATSUTA ELECTRIC WIRE & CABLE CO., LTD.
    Inventors: Yuusuke Haruna, Hiroshi Tajima, Masahiro Watanabe, Yukari Kobayashi, Kiyoharu Sekiguchi, Yoshihiro Hosoya
  • Patent number: 9930789
    Abstract: The steps of forming a multi-layer flexible printed circuit cable (flex circuit) with an electrical interconnection between independent conductive layers. In accordance with various embodiments, a partial aperture is formed in the flex circuit that extends through a first conductive layer and an intervening insulative layer to an underlying surface of a second conductive layer that spans the partial aperture. A solder material is reflowed within the partial aperture to electrically interconnect the first and second conductive layers.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: March 27, 2018
    Assignee: Seagate Technology LLC
    Inventor: Chau-Chin Low
  • Patent number: 9832883
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first surface finish on one or more electrical routing features located on a first side of a package substrate and on one or more lands located on a second side of the package substrate, the second side being opposite the first side of the substrate. The method may further include removing the first surface finish on the first side of the package substrate; and depositing a second surface finish on the one or more electrical routing features of the first side. The depositing of the second surface finish may be accomplished by one of a Direct Immersion Gold (DIG) process or an Organic Solderability Preservative (OSP) process. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: November 28, 2017
    Assignee: Intel Corporation
    Inventor: Qinglei Zhang
  • Patent number: 9820374
    Abstract: A apparatus comprising a printed circuit board (“PCB”). The PCB comprises a first insulating layer and a second insulating layer. The first insulating layer is made of a first material and the second insulating layer is made of a second material. The first material has a lower dissipation factor than the second material. The first material and second material have substantially similar dielectric constants.
    Type: Grant
    Filed: August 30, 2008
    Date of Patent: November 14, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Karl J. Bois, Ramon R. Campa
  • Patent number: 9795033
    Abstract: A three-dimensional structure in which a wiring is provided on a surface is provided. At least a part of the surface of the three-dimensional structure includes an insulating layer containing filler. A recessed gutter for wiring is provided on the surface of the three-dimensional structure, and at least a part of a wiring conductor is embedded in the recessed gutter for wiring.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: October 17, 2017
    Assignee: PANASONIC CORPORATION
    Inventors: Shingo Yoshioka, Hiroaki Fujiwara
  • Patent number: 9704842
    Abstract: An interposer having a multilayered conductive pattern portion that is constructed by repeating the direct printing on a carrier of one or more conductive pattern layers and application of one or more insulating layers between the printed conductive pattern layers is described. Also, a method for manufacturing the interposer, a semiconductor package using the interposer, and a method for fabricating the semiconductor package are described.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: July 11, 2017
    Assignee: Amkor Technology, Inc.
    Inventors: DongHoon Lee, DoHyung Kim, JungSoo Park, SeungChul Han, JooHyun Kim, David Jon Hiner, Ronald Patrick Huemoeller, Michael G. Kelly
  • Patent number: 9668361
    Abstract: A printed wiring board includes an insulative resin substrate having a penetrating hole, a first conductive layer formed on first surface of the substrate, a second conductive layer formed on second surface of the substrate, and a through-hole conductor formed in the hole such that the conductor is connecting the first and second conductive layers. The conductor has a seed layer on inner wall of the hole, a laminated plated layer on the seed layer and a filled plated layer on the laminated layer, the laminated layer is formed such that the laminated layer is closing center portion of the hole and forming recess at end of the hole, the filled layer is formed such that the filled layer is filling the recess, and the laminated layer includes multiple electrolytic plated films laminated along the seed layer and each having thickness which is less at edge than at center.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: May 30, 2017
    Assignee: IBIDEN CO., LTD.
    Inventor: Kazuki Kajihara
  • Patent number: 9635761
    Abstract: A printed circuit board, and a method of fabricating the printed circuit board is disclosed. The printed circuit board includes at least one coaxial via. A hollow via is disposed in the printed circuit board. A metal sleeve is formed around the circumference of said hollow via. An inner conductive path is disposed in the hollow via. Additionally, an insulating material is disposed in the hollow via, between the conducting path and the metal sleeve. The conductive path is used to connect signal traces disposed on two different layers of the printed circuit board. In some embodiments, these signal traces carry signals having a frequency above 1 GHz, although the disclosure is not limited to this embodiment.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: April 25, 2017
    Assignee: Massachusetts Institute of Technology
    Inventors: Glenn A. Brigham, Richard J. Stanley, Bradley Thomas Perry, Patrick J. Bell
  • Patent number: 9615463
    Abstract: Conductive patterns and methods of using and printing such conductive patterns are disclosed. In certain examples, the conductive patterns may be produced by disposing a conductive material between supports on a substrate. The supports may be removed to provide conductive patterns having a desired length and/or geometry.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: April 4, 2017
    Inventors: Oscar Khaselev, Nitin Desai, Michael T. Marczi, Bawa Singh
  • Patent number: 9565749
    Abstract: An obfuscated radio frequency circuit may be manufactured to include a metallization layer, and a dielectric layer under the metallization layer. The dielectric layer may be made up of a plurality of dielectric substrates having different dielectric constants to obfuscate functions of the circuit.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: February 7, 2017
    Assignee: THE BOEING COMPANY
    Inventor: Robert Tilman Worl
  • Patent number: 9502363
    Abstract: Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: November 22, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael B. Vincent, Trung Q. Duong, Zhiwei Gong, Scott M. Hayes, Alan J. Magnus, Douglas G. Mitchell, Eduard J. Pabst, Jason R. Wright, Weng F. Yap
  • Patent number: 9485863
    Abstract: A fabrication method of a coreless packaging substrate is provided, including the steps of: forming an inner built-up circuit board on a carrier; removing the carrier; and symmetrically forming a first outer built-up structure and a second outer built-up structure on top and bottom surfaces of the inner built-up circuit board, respectively. The present invention effectively increases the product yield, saves the fabrication cost, and reduces wastes.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: November 1, 2016
    Assignee: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Chung W. Ho, Dyi-Chung Hu, Huan-Ling Lee, Sheng-Yuah He
  • Patent number: 9443834
    Abstract: Solid state lights (SSLs) including a back-to-back solid state emitters (SSEs) and associated methods are disclosed herein. In various embodiments, an SSL can include a carrier substrate having a first surface and a second surface different from the first surface. First and second through substrate interconnects (TSIs) can extend from the first surface of the carrier substrate to the second surface. The SSL can further include a first and a second SSE, each having a front side and a back side opposite the front side. The back side of the first SSE faces the first surface of the carrier substrate and the first SSE is electrically coupled to the first and second TSIs. The back side of the second SSE faces the second surface of the carrier substrate and the second SSE is electrically coupled to the first and second TSIs.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: September 13, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Casey Kurth, Kevin Tetz
  • Patent number: 9420706
    Abstract: In a method of manufacturing a multilayer board, including: a drilling step for forming a via hole through a pre-preg by laser beam machining, a step of filling the via hole with conductive paste containing a resin component and metal powder, and a step of arranging copper layers or copper layer portions of patterned boards on and under the filled conductive paste and pressing the same, a multilayer printed wiring board superior in conductivity and long-term stability is obtained by using alloying paste as the conductive paste in which at least part of the metal powder is melted and the metal powders adjacent to each other are alloyed, using a pre-preg having a ratio A/B of at least 10 before subjected to preheating, where A is a storage modulus at an inflection point where the storage modulus changes from increasing to decreasing and B is a storage modulus at an inflection point where the storage modulus changes from decreasing to increasing in a temperature profile rising from 60° C. to 200° C.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: August 16, 2016
    Assignee: Tatsuta Electric Wire & Cable Co., Ltd.
    Inventors: Norihiro Yamaguchi, Hiroaki Umeda, Ken Yukawa
  • Patent number: 9420683
    Abstract: A substrate embedding a passive element includes a first conductor pattern layer disposed on a lower surface thereof and a second conductor pattern layer disposed on an upper surface thereof; a first via electrically connecting between the passive element and the first conductor pattern layer; and a second via electrically connecting between the passive element and the second conductor pattern layer, in which a volume of the first via is larger than that of the second via.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: August 16, 2016
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Doo Hwan Lee, Yul Kyo Chung, Yee Na Shin, Seung Eun Lee
  • Patent number: 9406532
    Abstract: A method for making an interconnection component is disclosed, including forming a plurality of metal posts extending away from a reference surface. Each post is formed having a pair of opposed end surface and an edge surface extending therebetween. A dielectric layer is formed contacting the edge surfaces and filling spaces between adjacent ones of the posts. The dielectric layer has first and second opposed surfaces adjacent the first and second end surfaces. The dielectric layer has a coefficient of thermal expansion of less than 8 ppm/° C. The interconnection component is completed such that it has no interconnects between the first and second end surfaces of the posts that extend in a lateral direction. First and second pluralities of wettable contacts are adjacent the first and second opposed surfaces. The wettable contacts are usable to bond the interconnection component to a microelectronic element or a circuit panel.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: August 2, 2016
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Ilyas Mohammed
  • Patent number: 9351407
    Abstract: A method of forming a multilayer device includes providing a core substrate having opposing first and second core surfaces and forming top and bottom inner conductive patterns on each of the first and second core surfaces, respectively. A first dielectric layer is formed on the first core surface, and the top inner conductive pattern. A second dielectric layer is formed on the second core surface, and the bottom inner conductive pattern. The first and second dielectric layers are laminated with top and bottom outer conductive layers, respectively. A first via is provided through the core substrate extending from the top outer conductive layer to the bottom outer conductive layer. The first via is filled with solder. Magnetic particles are attracted by a magnetic force into the first via.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: May 24, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Boon Yew Low
  • Patent number: 9314764
    Abstract: The invention features methods of making devices, or “platens”, having a high-density array of through-holes, as well as methods of cleaning and refurbishing the surfaces of the platens. The invention further features methods of making high-density arrays of chemical, biochemical, and biological compounds, having many advantages over conventional, lower-density arrays. The invention includes methods by which many physical, chemical or biological transformations can be implemented in serial or in parallel within each addressable through-hole of the devices. Additionally, the invention includes methods of analyzing the contents of the array, including assaying of physical properties of the samples.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: April 19, 2016
    Assignee: Life Technologies Corporation
    Inventors: Robert Hess, John Linton, Tanya S. Kanigan, Colin Brenan, Can Ozbal
  • Patent number: 9320154
    Abstract: An electrode connected to a TH pad requiring electric conduction is formed on a bonded surface of a first multilayer substrate having piercing TH to form a solder bump on the electrode. An electrode connected to the TH pad is formed on a bonded surface of a second multilayer substrate to be bonded having a piercing TH at a position opposite the electrode formed on the first multilayer substrate to form a solder bump on the electrode. A three-layered sheet is formed by applying an adhesive as a resin material that is not completely cured to both surfaces of a core material as the cured resin, and has holes at positions corresponding to the TH and the solder bump, respectively. The first and the second multilayer substrates are then laminated having the bonded surfaces facing each other while having the three-layered sheet positioned and interposed therebetween, and batch thermocompression bonded.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: April 19, 2016
    Assignee: HITACHI, LTD.
    Inventors: Akira Soeda, Chiko Yorita, Shinichirou Tooya, Takayuki Ono, Mitsuru Takahira, Yuuichi Sekino, Akira Goto, Yoshimasa Tashiro, Hiroyuki Doi, Tsutomu Sakamoto
  • Patent number: 9315014
    Abstract: In a screen printing apparatus, a squeegee is slid on a mask contacting a board to print paste onto the board via pattern holes formed in the mask. The screen printing apparatus includes: a box-like member including a top-plate portion in which first suction hole and a second section hole are formed and which is allowed to contact the board; a blower suction pipe communicating with an internal space of the box-like member and extending outside the box-like member; a blower suction source sucking air through the blower suction pipe to generate a blower suction force in the first suction hole; a vacuum suction pipe connected to the second suction hole and extending through the internal space to an outside of the box-like member; and a vacuum pressure supplying device supplying a vacuum pressure to the second suction hole through the vacuum suction pipe.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: April 19, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Isao Horie, Yusuke Sueyasu
  • Patent number: 9318466
    Abstract: A methodology for a thin, flexible substrate having integrated passive circuit elements, and the resulting device are disclosed. Embodiments may include integrating one or more passive circuit components on a first or second surface of a substrate, and interconnecting one or more integrated circuit (IC) dies on a second surface of the interposer to the one or more passive circuit components with one or more metal-filled vias between the first and second surfaces, the first and second surfaces being opposite surfaces of the substrate.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: April 19, 2016
    Assignee: GlobalFoundries Inc.
    Inventors: Saket Chadda, Ramakanth Alapati, Adam Beece
  • Patent number: 9269602
    Abstract: A fabrication method of a wafer level semiconductor package includes: forming on a carrier a first dielectric layer having first openings exposing portions of the carrier; forming a circuit layer on the first dielectric layer, a portion of the circuit layer being formed in the first openings; forming on the first dielectric layer and the circuit layer a second dielectric layer having second openings exposing portions of the circuit layer; forming conductive bumps in the second openings; mounting a semiconductor component on the conductive bumps; forming an encapsulant for encapsulating the semiconductor component; and removing the carrier to expose the circuit layer. By detecting the yield rate of the circuit layer before mounting the semiconductor component, the invention avoids discarding good semiconductor components together with packages as occurs in the prior art, thereby saving the fabrication cost and improving the product yield.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: February 23, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventor: Lu-Yi Chen
  • Patent number: 9265146
    Abstract: A method for manufacturing a multi-layer circuit board includes steps of: providing three copper clad laminates; forming trace layers in each copper clad laminate by selectively removing portions of copper layer of each copper clad laminate to obtain three first circuit substrates; laminating a dielectric layer on two of the first circuit substrates to obtain two second circuit substrates; forming a metal bump on the trace layer he other one of the three first circuit substrate to obtain a third circuit substrate; stacking and laminating the third circuit substrate between the two second circuit substrate to obtain a multi-layer circuit board.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: February 16, 2016
    Assignee: Zhen Ding Technology Co., Ltd.
    Inventors: Che-Wei Hsu, Shih-Ping Hsu
  • Patent number: 9225103
    Abstract: A connector comprises a connector housing receiving therein a terminal fitting connected to an electrode of a connector-mounting portion and an electrical wire at an end of which the terminal fitting is provided; a cap for the connector housing; and a packing for the cap. The packing includes a mushroom-like locking projection with an enlarged end portion. The cap includes a locking hole into which the end portion of the locking projection is inserted so that the end portion is placed in locking engagement with the locking hole.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: December 29, 2015
    Assignee: Yazaki Corporation
    Inventor: Kenichi Okamoto
  • Patent number: 9210809
    Abstract: Embodiments are directed to semiconductor packaging having reduced sized plated through hole (PTH) pads by eliminating the margin of the pad-to-PTH alignment and enabling finer traces on the core of the substrate.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: December 8, 2015
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Mihir Roy