Product Is Circuit Board Or Printed Circuit Patents (Class 205/125)
  • Patent number: 10595416
    Abstract: A circuit apparatus includes a first circuit feature upon a first insulator and a second circuit feature upon the first insulator. The first circuit feature includes a planarized surface and the second circuit feature includes an irregular surface. The first circuit feature and the second circuit feature may be formed from patterning a conductive sheet that is upon the first insulator. The conductive sheet includes an irregular surface and a planarized surface. Conductive sheet roughness is minimized in first regions thereof and is maintained in second regions thereof. Selectively planarizing portions of the conductive sheet allows for the utilization of lower cost rougher conductive sheets. The planarized surface allows for increased signal integrity and reduced insertion loss and the irregular surface allows for increased adhesion and enhancing reliability of the circuit apparatus.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Brian L. Carlson, John R. Dangler, Roger S. Krabbenhoft, Kevin A. Splittstoesser
  • Patent number: 10490497
    Abstract: A method includes etching a mandrel layer to form mandrel strips, and selectively depositing metal lines on sidewalls of the mandrel strips. During the selective deposition, top surfaces of the mandrel strips are masked by dielectric masks. The method further includes removing the mandrel layer and the dielectric masks, filling spaces between the metal lines with a dielectric material, forming via openings in the dielectric material, with top surfaces of the metal lines exposed to the via openings, and filling the via openings with a conductive material to form vias.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: November 26, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Hsien Peng, Hsiang-Huan Lee, Shau-Lin Shue
  • Patent number: 10492303
    Abstract: A substrate includes a substrate body, a flux coating portion which is coated with flux promoting solder fluidity on a surface of the substrate body, a conduction portion which is disposed on the surface of the substrate body to be separated from the flux coating portion and is conductive, and a silk portion which is disposed between the flux coating portion and the conduction portion on the surface of the substrate body and is provided by silk printing.
    Type: Grant
    Filed: September 5, 2016
    Date of Patent: November 26, 2019
    Assignee: MITSUBISHI HEAVY INDUSTRIES THERMAL SYSTEMS, LTD.
    Inventors: Makoto Hattori, Hiroyuki Kamitani, Hiroto Higuchi, Takayuki Takashige
  • Patent number: 10465276
    Abstract: The present invention relates to methods for fabricating a laterally-limited two-dimensional structure through template synthesis. The methods of the invention are useful in forming homogenous and heterogeneous layered materials. The invention also provides structures and devices formed by the method of the present invention and uses thereof.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: November 5, 2019
    Assignee: The Penn State Research Foundation
    Inventors: Joshua Alexander Robinson, Sarah Marie Eichfeld, Aleksander Felipe Piasecki, Brian Michael Bersch
  • Patent number: 10381326
    Abstract: A method of forming a semiconductor package comprises forming one or more first vias in a first side of a substrate and attaching a first side of a first microelectronic element to the first side of the substrate. The first microelectronic element is electrically coupled to at least one of the one or more first vias. The method further comprise obtaining a second microelectronic element including one or more second vias in a first side of the second microelectronic element, and attaching a second side of the substrate to the first side of the second microelectronic element. The second microelectronic element is electrically coupled to at least one of the one or more first vias. Each of one or more connecting elements has a first end attached to a first side of the second microelectronic element and a second end extends beyond a second side of the first microelectronic element.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: August 13, 2019
    Assignee: Invensas Corporation
    Inventors: Charles G. Woychik, Arkalgud R. Sitaram, Andrew Cao, Bong-Sub Lee
  • Patent number: 10312178
    Abstract: In a semiconductor device, a thinly-molded portion covering a whole of a heat dissipating surface portion of a lead frame and a die pad space filled portion are integrally molded from a second mold resin, because of which adhesion between the thinly-molded portion and lead frame improves owing to the die pad space filled portion adhering to a side surface of the lead frame. Also, as the thinly-molded portion is partially thicker owing to the die pad space filled portion, strength of the thinly-molded portion increases, and a deficiency or cracking is unlikely to occur.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: June 4, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takanobu Kajihara, Katsuhiko Omae, Shunsuke Fushie, Muneaki Mukuda, Daisuke Nakashima, Masahiro Motooka, Hiroyuki Miyanishi, Yuki Nakamatsu, Junya Suzuki
  • Patent number: 10273573
    Abstract: A method of depositing coating onto both sides of a substrate is provided, which includes steps of upwardly sputtering one or more lower targets to deposit a sacrificial coating onto a second surface and downwardly sputtering one or more upper targets to deposit a first functional coating onto a first surface, washing the substrate with one or more washers to remove the sacrificial coating from the second surface while leaving intact the first functional coating on the first surface, and downwardly sputtering the one or more upper targets to deposit a second functional coating onto the second surface.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: April 30, 2019
    Assignee: CARDINAL CG COMPANY
    Inventors: Kari B. Myli, Gary L. Pfaff, Keith James Burrows, Dylan Schweiss
  • Patent number: 10237971
    Abstract: A wiring board assembly (1) includes: a flexible printed wiring board (2) which includes at least an insulating substrate (5) including a through-hole (53), and wiring patterns (61) and (62) provided on the insulating substrate (5) and extending to peripheral edge portions (531n) and (532n) of the through-hole (53); a metal reinforcing plate (3) attached to the flexible printed wiring board (2) and facing the through-hole (53); and a solder connection portion (4) covering an inner wall surface (534) of the through-hole (53) and electrically connecting the wiring patterns (61) and (62) to the metal reinforcing plate (3).
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: March 19, 2019
    Assignee: FUJIKURA LTD.
    Inventors: Ryotaro Takagi, Kosuke Shimozuru, Yuji Inatani
  • Patent number: 10138130
    Abstract: An ultra dense and ultra low power microhotplates using silica aerogel and method of making the same, comprising creating a sol-gel by impregnation of ethanol with functional colloidal alcogel particles is described. The technique further comprises forming tiny aerogel particles on the wafer and networking the particles together just by exposure to air during spin coating. The novelty of this technique is not limited to the processing of thin film and thick film silica aerogel.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: November 27, 2018
    Assignee: The University of Louisiana at Lafayette
    Inventors: Mohammad Reza Madani, Seyedmohammad Seyedjalaliaghdam
  • Patent number: 10128195
    Abstract: A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer overlying the middle layer, and a bottom metal layer underlying the middle layer. All metal layers overlying the middle layer have a first total metal density that is equal to a sum of all densities of all metal layers over the middle layer. All metal layers underlying the middle layer have a second total metal density that is equal to a sum of all densities of all metal layers under the middle layer. An absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: November 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Lin, Guan-Yu Chen, Yu-Min Liang, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 10090264
    Abstract: A microelectronic device is formed by providing a substrate having a recess at a top surface, and a liner layer formed over the top surface of the substrate, extending into the recess. A protective layer is formed over the liner layer, extending into the recess. A CMP process removes the protective layer and the liner layer from over the top surface of the substrate, leaving the protective layer and the liner layer in the recess. The protective layer is subsequently removed from the recess, leaving the liner layer in the recess. The substrate may include an interconnect region with a bond pad and a PO layer having an opening which forms the recess; the bond pad is exposed in the recess. The liner layer in the recess may be a metal liner suitable for a subsequently-formed wire bond or bump bond.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: October 2, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jonathan Philip Davis, Andrew Frank Burnett, Brian Edward Zinn
  • Patent number: 10008638
    Abstract: The present invention relates to a method of manufacturing an optical device for a back light unit, and an optical device and an optical device array manufactured by the method, in which optical device chips constituting the optical device array are each laid the sides thereof on a printed circuit board in such a manner that light can be emitted from the optical device chips in a lateral direction, thus reducing the overall thickness of the back light unit.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: June 26, 2018
    Assignee: Point Engineering Co., Ltd.
    Inventors: Bum Mo Ahn, Seung Ho Park, Ki Myung Nam
  • Patent number: 9997354
    Abstract: There is provided a method of manufacturing a semiconductor device, including forming a seed layer on a substrate by performing a cycle a predetermined number of times, the cycle including supplying a halogen-based first processing gas to the substrate; supplying a non-halogen-based second processing gas to the substrate; and supplying a hydrogen-containing gas to the substrate. Further, the method further includes forming a film on the seed layer by supplying a third processing gas to the substrate.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: June 12, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Yugo Orihashi, Kazuhiro Yuasa, Atsushi Moriya, Naoharu Nakaiso
  • Patent number: 9980393
    Abstract: A pattern-forming method for forming a conductive circuit pattern, the pattern-forming method including the steps of: preparing a pattern-forming composition composed of: Cu powder; solder particles for electrically coupling the Cu powder; a polymer resin; a deforming agent that is selected from among acrylate oligomer, polyglycols, glycerides, polypropylene glycol, dimethyl silicon, simethinecone, tributyl phosphare, and polymethylsiloxane, and that increases bonding force between the Cu powder and the solder particles; a curing agent; and a reductant; forming a circuit pattern by printing the pattern-forming composition on a substrate; heating the circuit pattern at a temperature effective to cure the pattern-forming composition and provide the conductive circuit pattern; and electrolytically plating a metal layer onto the conductive circuit pattern. A circuit pattern having superior conductivity is formed at low cost.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: May 22, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yong Sung Eom, Kwang-Seong Choi, Hyun-cheol Bae, Jung Hyun Noh, Jong Tae Moon
  • Patent number: 9967974
    Abstract: The present invention relates to a composition for forming a conductive pattern, which is able to form a fine conductive pattern onto a variety of polymer resin products or resin layers by a very simple process, a method for forming the conductive pattern using the same, and a resin structure having the conductive pattern.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: May 8, 2018
    Assignee: LG CHEM, LTD.
    Inventors: Chee-Sung Park, Cheol-Hee Park, Shin Hee Jun, Sang Yun Jung, Han Nah Jeong
  • Patent number: 9947611
    Abstract: Disclosed is an integrated circuit arrangement including a two sided circuit board, having a first surface and a second surface. A plurality of electrical conductors is incorporated as part of the two sided circuit board. An array of through holes extend through the first surface and the second surface, arranged in a pattern and are configured to provide a common electrical connection area, wherein the common electrical connection area is associated with a portion of a particular one of the plurality of electrical conductors.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: April 17, 2018
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Ping Mei, Brent S. Krusor, David K. Biegelsen
  • Patent number: 9846364
    Abstract: A method of forming a resist pattern including forming a first resist pattern on a substrate; applying a cross-linking composition so as to cover the first resist pattern; heating the covered first resist pattern and crosslinking an isocyanate group in the cross-linking composition with the first resist pattern; and developing the covered first resist pattern, wherein the cross-linking composition includes a blocked isocyanate compound having a protected isocyanate group.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: December 19, 2017
    Assignee: TOKYO OHKA KOGYO CO., LTD.
    Inventors: Tomoyuki Hirano, Junichi Tsuchiya, Takayoshi Mori
  • Patent number: 9843216
    Abstract: A first coil portion is formed in a first coil region of an upper surface of an insulating layer, and a second coil portion is formed on a lower surface of the insulating layer. A second terminal is formed at a position outside the first coil region. One or more intersection regions, in which a path, extending from an inner end of the first coil portion to the second terminal, intersects the first coil portion, are provided on the upper surface. The first coil portion is parted in each intersection region. A second lead portion passes between one portion and another portion of the first coil portion parted in said each intersection region and extends from the inner end of the first coil portion to the second terminal. The first coil portion and the second coil portion are connected together in parallel via through holes formed in the insulating layer.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: December 12, 2017
    Assignee: NITTO DENKO CORPORATION
    Inventors: Tadao Ookawa, Emiko Tani, Akihito Matsutomi, Shotaro Masuda
  • Patent number: 9768092
    Abstract: A carrier is disclosed, including: a main body having a first surface and a second surface opposing the first surface; a conductive part formed on the first surface of the main body; and a plurality of heat conductors that are not in contact with the conductive part and penetrate the main body to connect the first surface with the second surface. Therefore, heat generated by electronic elements can be effectively dissipated outside to improve the functionality and lifetime of electronic elements.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: September 19, 2017
    Assignee: Viking Tech Corporation
    Inventors: Chien-Hung Ho, Chiu-Min Lee, Chen-Shen Kuo
  • Patent number: 9698475
    Abstract: A first resin layer (11) is provided with a first through hole (12), a conductive pattern (31, 41, 51) extends from a first surface of the first resin layer (11) to a second surface of the first resin layer (11) through the first through hole (12), and a second resin layer (21) is provided with a first protrusion (22) which fills at least a portion of the first through hole (12).
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: July 4, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Tomofumi Katayama
  • Patent number: 9678033
    Abstract: An electrochemical biosensor includes a substrate, a plurality of layered active metal parts, a plurality of layered electrodes, a reaction confinement layer, an electrochemical reactive layer and a cover piece. The substrate is formed with through holes each of which is defined by an interior wall surface and penetrates top and bottom surfaces. Each of the layered active metal parts is formed at least upon a respective one of the interior wall surfaces. The layered electrodes are formed on the layered active metal parts. The reaction confinement layer confines a reactor space over a region where the through holes are formed. The electrochemical reactive layer is disposed in the reactor space and is electrically coupled to the layered electrodes.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: June 13, 2017
    Assignee: Taiwan Green Point Enterprises Co., Ltd.
    Inventors: Yu-Chuan Lin, Sung-Yi Yang, Yi-Cheng Lin
  • Patent number: 9674896
    Abstract: An ultra dense and ultra low power microhotplates using silica aerogel and method of making the same, comprising spin coating an aerogel layer followed by SiO2 as capping interlayer, and Nichrome (Ni80/Cr20) for heating element to increase the efficiency of metal oxide gas sensors. There may be multiple thin layers of aerogel separated by interlayers such as of SiO2.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: June 6, 2017
    Assignee: The University of Louisiana at Lafayette
    Inventors: Mohammad Reza Madani, Seyedmohammad Seyedjalaliaghdam
  • Patent number: 9648757
    Abstract: A method of manufacturing a space transformer includes providing a carrier substrate made for a chip package, forming an insulated layer disposed on the carrier substrate, and forming a conductive block. The carrier substrate is formed with elongated first and second wires. The first wire has an elongated contact which is longer than the width of the first wire. The insulated layer is formed with a hole corresponding in position to the elongated contact. The conductive block is formed with an elongated connecting column located in the hole and connected with the elongated contact, and a cylindrical contact pad exposed at the outside of the insulated layer, larger-sized than the elongated connecting column is connected with the elongated connecting column. As a result, the cylindrical contact pad has sufficient area and structural strength for contact with a probe needle.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: May 9, 2017
    Assignee: MPI CORPORATION
    Inventors: Chung-Tse Lee, Chien-Chou Wu, Tsung-Yi Chen
  • Patent number: 9629260
    Abstract: Disclosed herein are a printed circuit board and a method of manufacturing the same. The printed circuit board according to a preferred embodiment of the present invention includes a base substrate; a through via formed to penetrate through the base substrate; and circuit patterns formed on one side and the other side of the base substrate and formed to be thinner than an inner wall of the through via.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: April 18, 2017
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Seung Wook Park, Young Do Kweon, Jin Gu Kim
  • Patent number: 9593431
    Abstract: Electroplating systems that include a plurality of electrodes, a power supply operably coupled to the plurality of electrodes, a platen for bearing a substrate on which metal features are to be formed, and an electrode support are disclosed. The electrode support may be configured for suspending the electrode assembly over an upper surface of the substrate disposed on the platen in spaced relation to and in alignment with the substrate or for supporting the electrode assembly in a stationary position over the substrate when the voltage is applied across the plurality of electrodes. The electrodes may be adjacent, mutually spaced and electrically isolated and connected in series so as to be oppositely polarized when the voltage is applied thereacross or may be connected so as to have alternating polarities when the voltage is applied thereacross.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: March 14, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Suresh Ramarajan, Whonchee Lee
  • Patent number: 9588090
    Abstract: Within a method for the determination of film-forming amines in liquids by adding a reacting agent with the amine to form a colored complex to be measured by photometric method for the reaction the pH of the liquid mixture is lowered by using hydrochloric acid.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: March 7, 2017
    Assignee: SWAN ANALYTISCHE INSTRUMENTE AG
    Inventor: Marco Lendi
  • Patent number: 9587318
    Abstract: Method for continuously producing flexible copper clad laminates includes performing continuous ion implantation and/or plasma deposition on the surface of an organic macromolecular polymer film, and performing continuous copper plating. The bonding force between the copper film and the substrate in a two-layer flexible copper clad laminate produced by the method is much larger than that in a flexible copper clad laminate produced by a sputtering/plating method and equivalent to that in a flexible copper clad laminate produced by a coating method and a lamination method. Meanwhile the thickness of the copper film can be easily controlled to be less than 18 microns.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: March 7, 2017
    Assignee: RICHVIEW ELECTRONICS CO., LTD.
    Inventors: Xinlin Xie, Nianqun Yang
  • Patent number: 9539611
    Abstract: A method for electroless coating of substrates by applying an activating coat of polyelectrolyte or salt with a first aqueous composition; rinsing the activating coat such that the activating coat not being entirely removed; contacting and coating of the activated surfaces that have remained after rinsing with an aqueous composition in the form of a solution, emulsion or suspension, to form an organic secondary coat; and drying. The activating coat is a solution, emulsion or suspension containing a anionic polyelectrolyte or at least one anionic salt in solution in water. The aqueous composition forming the secondary coat has constituents which can be precipitated, deposited or salted out and which are anionically, zwitterionically, sterically or cationically stabilized. The dry film formed in the process, comprising the activating coat and the secondary coat, has a thickness of at least 1 ?m.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: January 10, 2017
    Assignee: Chemetall GmbH
    Inventors: Daniel Wasserfallen, Michael Schwamb, Cindy Ettrich, Vera Sotke, Martin Droll, Oliver Seewald, Wolfgang Bremser, Aliaksandr Frenkel
  • Patent number: 9533288
    Abstract: The present invention relates to a method for preparing a supported metal catalyst for the selective hydrogenation of unsaturated hydrocarbons, characterized in that it comprises the following steps: a) electroplating a layer of nickel on a metallic support, and then b) electroplating a top layer of platinum and/or palladium. The present invention also relates to the supported metal catalyst obtained by this process, and the use thereof in hydrogenation reactions of unsaturated hydrocarbons, in particular for the selective hydrogenation of light olefins.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: January 3, 2017
    Assignee: Eurecat S.A.
    Inventors: Pierre Dufresne, Sharath Kirumakki
  • Patent number: 9451065
    Abstract: Housings for electronic devices including adaptive plugs, and the use of adaptive plugs in methods of manufacturing housings. The housing may include an opening, and an adaptive plug releasably positioned within the opening. A method of forming a housing may include forming an opening within the housing, disposing a curable material within the opening of the housing, and curing the material to form an adaptive plug. The adaptive plug may be positioned within the opening of the housing. The method may also include performing at least one surface treatment on the housing. A method of protecting an edge of an opening in a housing may include providing the housing including the opening, forming an adaptive plug within the opening of the housing, and forming a barrier on the edge of the opening using the adaptive plug.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: September 20, 2016
    Assignee: APPLE INC.
    Inventors: Brandon J. Van Asseldonk, Brett A. Rosenthal, Chien-Ming Huang
  • Patent number: 9445510
    Abstract: The present invention relates to a galvanic process for filling through-holes with metals. The process is particularly suitable for filling through-holes of printed circuit boards with copper. The process comprises the following steps: (i) formation of a narrow part in the center of a through-hole by electroplating; and (ii) filling the through-hole obtained in step (i) with metal by electroplating.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: September 13, 2016
    Assignee: Atotech Deutschland GmbH
    Inventors: Bert Reents, Thomas Pliet, Bernd Roelfs, Toshiya Fujiwara, Rene Wenzel, Markus Youkhanis, Soungsoo Kim
  • Patent number: 9385073
    Abstract: An embodiment device package includes a discrete device, a first connector on a bottom surface of the discrete device, and a second connector on a top surface of the discrete device. The first connector bonds the discrete device to a first package component, and the second connector bonds the discrete device to a second package component.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: July 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chao-Yang Yeh
  • Patent number: 9327984
    Abstract: A method for preparing graphene nanoplate (GNP) is provided and includes preparing expanded graphite (EG) and exfoliating, grinding, or cracking the expanded graphite to crack the EG induced by gas-phase-collision. A graphene nanoplate paste and a conductive coating layer formed of the graphene nanoplate paste are provided and are prepared by the method for preparing graphene nanoplate.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: May 3, 2016
    Assignees: Hyundai Motor Company, Korea Institute of Ceramic Engineering and Technology
    Inventors: Kwang Il Chang, Chul Kyu Song, Dha Hae Kim, Seung Hun Hur
  • Patent number: 9282628
    Abstract: A component built-in board, wherein at least two layers of a plurality of printed wiring bases are disposed on a rear surface side of an electronic component; the at least two layers of the printed wiring bases include a heat radiation-dedicated wiring pattern that is disposed above the rear surface of the electronic component; the heat radiation-dedicated wiring pattern is formed such that a heat radiation-dedicated wiring line and a signal-dedicated wiring line are continuous; a via includes a plurality of heat radiation-dedicated vias which connects the rear surface of the electronic component and the heat radiation-dedicated wiring pattern; and the heat radiation-dedicated wiring pattern is continuous from a place where connected to the heat radiation-dedicated via to be connected also to another via disposed at an outer peripheral side of the electronic component.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: March 8, 2016
    Assignee: FUJIKURA LTD.
    Inventor: Masahiro Okamoto
  • Patent number: 9277653
    Abstract: Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of manufacturing a PCB. Embodiments include depositing upon layers of laminate printed circuit traces and joining the layers of laminate. Embodiments also include drilling at least one via hole through the layers of laminate and placing in the via hole a via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a second metal having a conductivity lower than the conductivity of copper.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: March 1, 2016
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Moises Cases, Tae Hong Kim, Rohan U. Mandrekar, Nusrat I. Sherali
  • Patent number: 9236338
    Abstract: A method for manufacturing a build-up substrate, the build-up substrate comprising an insulating layer and a wiring pattern layer stacked over a circuit substrate, said method comprising the steps of: (i) applying a photoactive metal oxide precursor material to one or both sides of the circuit substrate with a wiring pattern, and drying the applied photoactive metal oxide precursor material to form an insulating film; (ii) forming an opening for a via hole in the insulating film by exposure and development of the insulating film; (iii) applying a heat treatment to the insulating film to convert the insulating film into a metal oxide film, thereby forming a build-up insulating layer of the metal oxide film; and (iv) plating the build-up insulating layer to form via holes in the openings, forming a metal layer on the build-up insulating layer, and etching the metal layer to form a build-up wiring pattern; and (v) repeating the steps from (i) to (iv) at least one time.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: January 12, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Seiichi Nakatani, Koji Kawakita, Susumu Sawada, Yoshihisa Yamashita
  • Patent number: 9169576
    Abstract: An electrolytic copper plating solution is provided which has an excellent via filling ability without using formaldehyde, which is harmful to the environment. An electrolytic copper plating solution which contains compounds which have an —X—S—Y— structure wherein X and Y are individually atoms selected from a group comprising hydrogen, carbon, sulfur, nitrogen, and oxygen atoms and X and Y can be the same only when they are carbon atoms and specific nitrogen-containing compounds. Good filled vias can be made without causing a worsening of the exterior appearance of the plating by using this electrolytic copper plating solution.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: October 27, 2015
    Inventors: Mutsuko Saito, Makoto Sakai, Yoko Mizuno, Toshiyuki Morinaga, Shinjiro Hayashi
  • Patent number: 9159671
    Abstract: Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: October 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Fen Chen, Jeffrey P. Gambino, Zhong-Xiang He, Trevor A. Thompson, Eric J. White
  • Patent number: 9131614
    Abstract: A method for manufacturing an embedded wiring board is provided. An activating insulation layer is formed. The activating insulation layer includes a plurality of catalyst particles, and covers a first wiring layer. An intaglio pattern and at least one blind via partially exposing the first wiring layer are formed on the activating insulation layer, in which some of the catalyst particles are activated and exposed in the intaglio pattern and the blind via. The activating insulation layer is dipped in a first chemical plating solution, and a solid conductive pillar is formed in the blind via through electroless plating. The activating insulation layer is dipped in a second chemical plating solution after the solid conductive pillar is formed, and a second wiring layer is formed in the intaglio pattern through the electroless plating. Components of the first chemical plating solution and the second chemical plating solution are different.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 8, 2015
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Cheng-Po Yu, Chai-Liang Hsu
  • Publication number: 20150136467
    Abstract: A method of making an array of integral terminals on a circuit assembly. The method includes the steps of depositing at least a first liquid dielectric layer on the first surface of a first circuit member, imaged to include a plurality of first recesses corresponding to the array of integral terminals. The selected surfaces of the first recesses are processed to accept electro-less conductive plating deposition. Electro-lessly plating is applied to the selected surfaces of the first recesses to create a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. Electro-plating is applied to the electro-less plating to substantially first recesses with a conductive material. The steps of depositing, processing, electro-less plating, and electro-plating are repeated to form the integral terminals of a desired shape. The dielectric layers are removed to expose the terminals.
    Type: Application
    Filed: March 13, 2013
    Publication date: May 21, 2015
    Inventor: James Rathburn
  • Publication number: 20150129288
    Abstract: A circuit substrate includes: a substrate; an insulating coating layered structure formed on the substrate, having top and bottom surfaces, and formed with a patterned recess that is indented inwardly from the top surface, that is disposed above the bottom surface, and that is defined by a recess-defining wall, the recess-defining wall having a bottom wall portion and a surrounding wall portion that extends upwardly from a periphery of the bottom wall portion; and a patterned metallic layered structure including an electroless plating metal layer formed on the bottom wall portion of the recess-defining wall.
    Type: Application
    Filed: November 13, 2013
    Publication date: May 14, 2015
    Applicant: TAIWAN GREEN POINT ENTERPRISES CO., LTD.
    Inventors: Pen-Yi LIAO, Tsung-Han WU, Fu-Pin TANG, Mei-Chun CHEN, Yu-Jen CHOU
  • Patent number: 9021669
    Abstract: Provided is a method for manufacturing a surface acoustic wave apparatus that can reduce degradation of electric characteristics and also reduce the number of manufacturing processes. The method for manufacturing a surface acoustic wave apparatus includes the steps of: forming an IDT electrode on an upper surface of a piezoelectric substrate, forming a frame member surrounding a formation area in which the IDT electrode is formed on the piezoelectric substrate, and mounting a film-shaped lid member on the upper surface of the frame member so as to be joined to the frame member so that a protective cover, used for covering the formation area and for providing a tightly-closed space between it and the formation area, is formed.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: May 5, 2015
    Assignee: KYOCERA Corporation
    Inventor: Toru Fukano
  • Publication number: 20150118391
    Abstract: A thermal management circuit material comprises a thermally conductive metallic core substrate, metal oxide dielectric layers on both sides of the metallic core substrate, electrically conductive metal layers on the metal oxide metal oxide dielectric layers, and at least one through-hole via filled with an electrically conductive metal-containing core element connecting at least a portion of each of the electrically conductive metal layers, wherein the containing walls of the through-hole via are covered by a metal oxide dielectric layer connecting at least a portion of the metal oxide dielectric layers on opposite sides of the metallic core substrate. Also disclosed are methods of making such circuit materials, comprising forming metal oxide dielectric layers by oxidative conversion of a surface portion of the metallic core substrate. Articles having a heat-generating electronic device such as an HBLED mounted in the circuit material are also disclosed.
    Type: Application
    Filed: October 24, 2014
    Publication date: April 30, 2015
    Inventor: Brett W. Kilhenny
  • Patent number: 9017540
    Abstract: Systems and methods for reducing overhang on electroplated surfaces of printed circuit boards are described. One such method includes applying a first resist layer on a substrate having a first copper layer, applying a first image to the first resist layer, developing the first resist layer in accordance with the first image, applying a second copper layer on the first copper layer, electroplating a first metallic layer on the second copper layer, removing the first resist layer, etching a portion of the first copper layer, removing the first metallic layer, depositing a third copper layer on a surface of the assembly, applying a second resist layer on the third copper layer, applying a second image to the second resist layer, developing the second resist layer in accordance with the second image, electroplating a preselected metal layer on the third copper layer, removing the second resist layer, and etching a portion of the third copper layer.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: April 28, 2015
    Assignee: Viasystems Technologies Corp. L.L.C.
    Inventors: Rajwant S. Sidhu, Ruben A. Zepeda, Carlos A. Lopez
  • Publication number: 20150108003
    Abstract: A method for producing ceramic circuit boards from ceramic substrates having metal-filled vias. In order to be able to fill the vias by means of a single filling process, either a planar copper metallization is applied on one side to the ceramic substrate having vias by means of scren printing, or a copper film of 100-300 ?m is bonded on one side to the ceramic substrate having vias in a DCB/DBC process and the vias are filled from the ceramic side by means of an electrogalvanic process in a copper bath by the deposition of copper.
    Type: Application
    Filed: April 30, 2013
    Publication date: April 23, 2015
    Applicant: CeramTec GmbH
    Inventor: Dietmar Jaehnig
  • Patent number: 9011666
    Abstract: A composition comprising a source of metal ions and at least one leveling agent obtainable by condensing at least one trialkanolamine of the general formula N(R1—OH)3 (Ia) and/or at least one dialkanolamine of the general formula R2—N(R1—OH)2 (Ib) to give a polyalkanolamine(II), wherein the R1 radicals are each independently selected from a divalent, linear or branched aliphatic hydrocarbon radical having from 2 to 6 carbon atoms, and the R2 radicals are each selected from hydrogen and linear or branched aliphatic, cycloaliphatic and aromatic hydrocarbon radicals having from 1 to 30 carbon atoms, or derivatives obtainable by alkoxylation, substitution or alkoxylation and substitution of said polyalkanolamine(II).
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: April 21, 2015
    Assignee: BASF SE
    Inventors: Cornelia Roeger-Goepfert, Roman Benedikt Raether, Sophia Ebert, Charlotte Emnet, Alexandra Haag, Dieter Mayer
  • Publication number: 20150090481
    Abstract: A manufacturing method of a package carrier includes the following steps. Firstly, two base metal layers are bonded together. Then, two supporting layers are laminated onto the base metal layers respectively. Next, two release metal films are disposed on the supporting layers respectively, wherein each of the release metal films includes a first metal film and a second metal film separable from each other. Next, two patterned metal layers are formed on the release metal films respectively, wherein each of the patterned metal layers is suitable for carrying and electrically connected to a chip. Then, the base metal layers are separated from each other to form two package carriers independent from each other. A package carrier formed by the manufacturing method described above is also provided.
    Type: Application
    Filed: November 22, 2013
    Publication date: April 2, 2015
    Applicant: Subtron Technology Co., Ltd.
    Inventor: Shih-Hao Sun
  • Publication number: 20150092378
    Abstract: A circuit board upon which to mount an integrated circuit chip may include a first interconnect zone on the surface of the circuit board having first contacts with a first pitch, and a second interconnect zone, surrounding the first zone, having second contacts or traces with a second pitch that is smaller than the first pitch. The first contacts may have a design rule (DR) for direct chip attachment (DCA) to an integrated circuit chip. The first contacts may be formed by bonding a sacrificial substrate having the first contacts to a surface of the board; or by laser scribing trenches where the conductor will be plated to create the first contacts. Such a board allows DCA of smaller footprint processor chips for devices, such as tablet computers, cell phones, smart phones, and value phone devices.
    Type: Application
    Filed: September 28, 2013
    Publication date: April 2, 2015
    Inventors: Mihir K. ROY, Mathew J. MANUSHAROW
  • Publication number: 20150090476
    Abstract: A manufacturing method of a package carrier includes the following steps. Two base metal layers are bonded together. Two supporting layers are laminated onto the base metal layers respectively. Two release metal films are disposed on the supporting layers respectively. Each release metal film includes a first metal film and a second metal film separable from each other. Two first patterned metal layers are formed on the release metal films respectively. Each first patterned metal layer includes a pad pattern. Two dielectric layers are formed on the release metal films respectively and cover the corresponding first patterned metal layers. Each dielectric layer has a conductive via connecting to the corresponding pad pattern. Two second patterned metal layers are formed on the dielectric layers respectively. Each second patterned metal layer at least covers the conductive via. The base metal layers are separated from each other to form two independent package carriers.
    Type: Application
    Filed: December 5, 2013
    Publication date: April 2, 2015
    Applicant: SUBTRON TECHNOLOGY CO., LTD.
    Inventor: Shih-Hao Sun
  • Patent number: 8992756
    Abstract: A surface of an object to be plated is subjected to a treatment for palladium catalyst impartation to impart a palladium catalyst to the surface of an insulating part thereof. A palladium conductor layer is formed on the insulating part from a solution for palladium conductor layer formation which contains a palladium compound, an amine compound, and a reducing agent. On the palladium conductor layer is then directly formed a copper deposit by electroplating. Thus, the work is converted to a conductor with the solution for palladium conductor layer formation, which is neutral, without using an electroless copper plating solution which is highly alkaline. Consequently, the polyimide is prevented from being attacked and no adverse influence is exerted on adhesion. By adding an azole compound to the solution for palladium conductor layer formation, a palladium conductor layer is prevented from depositing on copper.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: March 31, 2015
    Assignee: C. Uyemura & Co., Ltd.
    Inventor: Hisamitsu Yamamoto