DAMASCENE REPLACEMENT METAL GATE PROCESS WITH CONTROLLED GATE PROFILE AND LENGTH USING Si1-xGex AS SACRIFICIAL MATERIAL
A method of forming a metal gate in a wafer. PolySi1-xGex and polysilicon are used to form a tapered groove. Gate oxide, PolySi1-xGex, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi1-xGex, and gate oxide is removed to provide a tapered profile. The resist is removed; a dielectric liner is deposited, and then at least a portion of the dielectric liner is removed, thereby exposing the polysilicon and leaving the dielectric liner in contact with the polysilicon, PolySi1-xGex, and gate oxide. A dielectric is deposited, and a portion is removed thereby exposing the polysilicon. The polysilicon, PolySi1-xGex, and gate oxide is removed from inside the dielectric liner, thereby leaving a tapered gate groove. Metal is then deposited in the groove.
Latest LSI LOGIC CORPORATION Patents:
- Flipchip bump patterns for efficient I-mesh power distribution schemes
- Semiconductor package and method using isolated Vplane to accommodate high speed circuitry ground isolation
- Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures
- Integrated circuit cell architecture configurable for memory or logic elements
- Method characterizing materials for a trench isolation structure having low trench parasitic capacitance
This patent application is a divisional of U.S. patent application Ser. No. 10/889,901, filed on Jul. 13, 2004.
BACKGROUNDThe present invention generally relates to damascene metal gate processes, and more specifically relates to a damascene metal gate process which uses Si1-xGex as a sacrificial member.
The aggressive scaling of metal oxide semiconductor (MOS) devices is quickly reaching the fundamental limits of SiO2 as the gate dielectric. Scaling requirements can no longer be achieved with SiO2 or nitrided-SiO2 gate dielectrics due to the presence of excessive leakage currents arising from direct tunneling and the lack of manufacturability of sub-1 nm oxides. Moreover, poly-Si depletion and threshold voltage shifts due to boron penetration into the channel region severely degrade device performance. Replacement of SiO2-based gate dielectrics with a high dielectric constant (high-k) material provides a means to address scaling issues. A high-k material allows for a physically thicker film to meet the required gate capacitance, while reducing the leakage current due to direct tunneling and improving manufacturability.
The issue of poly-Si depletion is still not overcome when using a high-k material, since the 3-6A contribution to EOT due to poly-Si depletion is still about 30-50% of the target EOT. As a result, the semiconductor industry began investigating metal gate electrodes. Replacement of poly-Si with a metal electrode solves both the boron penetration and poly-Si depletion issues. Moreover, the introduction of metal gates can prolong the use of SiO2 for one or two technology generations for high performance applications before requiring a switch to high-k dielectrics.
A major challenge to the introduction of metal electrodes is addressing the issue of how to integrate the material into conventional transistor processing. In the case of CMOS and partially depleted SOI, two metal types will be needed, one with an n-type work function and one with a p-type work function. In the case of fully depleted SOI, a single metal with a mid-gap work function can be used. Whether one type or two types of metals are used, the integration question is still open. Many candidate metals will not sustain a standard source/drain activation anneal due to either reaction with the gate dielectric or the low melting temperature of many metal materials. In order to increase the number of candidate metal materials, a replacement gate approach is very appealing.
A replacement gate approach using a damascene scheme has been proposed previously, and is illustrated in
A major problem of the existing damascene replacement scheme for metal gates is associated with the dummy polysilicon profile. The standard CMOS polysilicon gate etch process in general can only achieve a tapered polysilicon profile 40 with an angle of 87-89 degrees as shown in
-
- (a). Dummy polysilicon residue 44 as illustrated in
FIG. 7 : Incomplete removal of dummy polysilicon the sidewall, especially when a RIE is used to remove the dummy polysilicon. - (b). Incomplete dummy gate dielectric removal or undercut beneath residue polysilicon.
- (c). Difficulty of groove filling with new gate dielectric and metal electrode. Voids could be formed due to the lack of gap filling capability for the gate dielectric and metal electrode inside these narrow and high aspect ratio grooves, which will in turn limit the scalability of this scheme for the future technology nodes.
- (a). Dummy polysilicon residue 44 as illustrated in
An object of an embodiment of the present invention is to provide a method of forming a metal gate in a wafer which does not result in polysilicon residue being left in a groove before the groove is filled with metal.
Another object of an embodiment of the present invention is to provide a method of forming a metal gate in a wafer wherein a tapered groove is formed that tapers from an opening at its top to the bottom of the groove.
Yet another object of an embodiment of the present invention is to provide a metal gate in a wafer, where there is a groove which has a tapered profile which converges from an opening to a base, and there is metal in the groove, thereby providing the metal gate.
Briefly, and in accordance with at least one of the foregoing objects, an embodiment of the present invention provides a method of forming a metal gate in a wafer wherein PolySi1-xGex is used as a sacrificial member to form a tapered groove. Specifically, gate oxide, PolySi1-xGex, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySi1-xGex, and gate oxide is removed to provide a tapered profile. The resist is removed; a dielectric liner is deposited, and then at least a portion of the dielectric liner is removed, thereby exposing the polysilicon and leaving the dielectric liner in contact with the polysilicon, PolySi1-xGex, and gate oxide. A dielectric is deposited, and a portion is removed thereby exposing the polysilicon. The polysilicon, PolySi1-xGex, and gate oxide is removed from inside the dielectric liner, thereby leaving a tapered gate groove. Metal is then deposited in the groove.
The organization and manner of the structure and operation of the invention, together with further objects and advantages thereof, may best be understood by reference to the following description, taken in connection with the accompanying drawings, wherein:
While the invention may be susceptible to embodiment in different forms, there are shown in the drawings, and herein will be described in detail, specific embodiments of the invention. The present disclosure is to be considered an example of the principles of the invention, and is not intended to limit the invention to that which is illustrated and described herein.
The present invention aims to improve the dummy gate profile, eliminate the re-entrant profile of gate grooves, and extend the damascene replacement scheme to future technology nodes.
Instead of using pure polysilicon as dummy gate, the new method involves the use of a polysilicon/PolySi1-xGex film stacks as a dummy gate.
By manipulating the Ge composition in the PolySi1-xGex, the plasma etching chemistries of Si1-xGex, oxidation, and oxide wet etching, a re-entrant PolySi1-xGex profile can be achieved (as shown in
The capability of the manipulation of Si1-xGex resides in the fact that the Si1 Gex has higher oxidation rate than silicon, and germanium oxide is a volatile compound. The present method involves the use of F/Cl2 based chemistries for plasma etching of polysilicon portion as well as the use of Cl2/HBr/O2 based chemistries for etching the PolySi1-xGex portion of the film stack. The inclusion of O2 in the etch chemistry results in a diminished Si1-xGex dimension with respect to the polysilicon (LsiGe/LSi=0.8 with LsiGe and Lsi being the dimensions of the PolySi1-xGex and silicon, respectively).
The profile of Si1-xGex can be further manipulated by using a wet chemistry (such as SCl) that includes an oxidizing agent (such as H2O2 or O3) and an acid or base, such as NH4OH, to dissolve the oxidized surface. The film thickness of polysilicon/Poly Si1-xGex, and the composition of Ge in the Si1-xGex alloy can also be adjusted to fit the requirements of the final profile and CDs.
Hence, the process has the following features:
-
- (a). Deposition of polysilicon/Poly Si1-xGex film stacks as damascene replacement dummy gate materials.
- (b). Manipulation of the plasma etch chemistries, Ge composition, film stack thickness, and wet clean chemistries to achieve a desired re-entrant dummy gate profile.
- (c). Dielectric liner deposition and plasma etching to provide a dielectric sidewall for preserving the gate groove profile.
- (d). A unique gate profile.
- (e). Scalability: can be used to achieve small gate length without the need of small line print.
- (f). Prevention of the incomplete polysilicon strip and undercut after dummy gate dielectric removal.
- (g). Improved subsequent new gate dielectric and metal gate electrode gap fill capability.
While embodiments of the present invention are shown and described, it is envisioned that those skilled in the art may devise various modifications of the present invention without departing from the spirit and scope of the appended claims.
Claims
1. A metal gate in a wafer comprising: a groove which has a tapered profile which converges from an opening to a base; metal in the groove, thereby providing said metal gate.
2. A metal gate as recited in claim 1, further comprising a dielectric liner on a side of said groove.
3. A metal gate as recited in claim 2, further comprising a dielectric layer, said dielectric liner being disposed between said dielectric layer and said metal.
Type: Application
Filed: Jan 29, 2008
Publication Date: Jun 26, 2008
Applicant: LSI LOGIC CORPORATION (Milpitas, CA)
Inventors: Hong Lin (Vancouver, WA), Wai Lo (Lake Oswego, OR), Sey-Shing Sun (Portland, OR), Richard Carter (Fairview, OR)
Application Number: 12/021,728
International Classification: H01L 29/40 (20060101);