Groove Patents (Class 257/622)
  • Patent number: 11171193
    Abstract: A semiconductor device includes a base substrate, a first transistor disposed on the base substrate, the first transistor including a first input electrode, a first output electrode, a first control electrode, and a first semiconductor pattern including a crystalline semiconductor, a second transistor disposed on the base substrate, the second transistor including a second input electrode, a second output electrode, a second control electrode, and a second semiconductor pattern including an oxide semiconductor, a plurality of insulating layers disposed on the base substrate, and an upper electrode disposed on the first control electrode with at least one insulating layer of the plurality of insulating layers interposed between the upper electrode and the first control electrode. The upper electrode overlaps the first control electrode and forms a capacitor with the first control electrode.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: November 9, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kyoungseok Son, Dohyun Kwon, Jonghan Jeong, Jonghyun Choi, Eoksu Kim, Jaybum Kim, Junhyung Lim, Jihun Lim
  • Patent number: 11139285
    Abstract: A semiconductor package includes a first package component include a first side, a second side opposite to the first side, and a plurality of recessed corners over the first side. The semiconductor package further includes a plurality of first stress buffer structures disposed at the recessed corners, and each of the first stress buffer structures has a curved surface. The semiconductor package further includes a second package component connected to the first package component and a plurality of connectors disposed between the first package component and the second package component. The connectors are electrically coupled the first package component and the second package component. The semiconductor package further includes an underfill material between the first package component and the second package component, and at least a portion of the curved surface of the first stress buffer structures is in contact with and embedded in the underfill material.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsien-Ju Tsou, Chih-Wei Wu, Pu Wang, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin
  • Patent number: 11101167
    Abstract: A semiconductor device manufacturing method of an embodiment includes forming a first layer in a region of a first substrate excluding an outer peripheral portion thereof; forming a first semiconductor circuit above the first layer; forming a second semiconductor circuit on a second substrate; forming a second layer with a predetermined width at an outer peripheral portion of the second substrate; bonding a surface of the first substrate on a side provided with the first semiconductor circuit and a surface of the second substrate on a side provided with the second semiconductor circuit; and applying tensile stress to the first layer and the second layer to debond the first layer and the second layer, thereby forming the second substrate including the first semiconductor circuit and the second semiconductor circuit.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: August 24, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Mie Matsuo
  • Patent number: 11081475
    Abstract: An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: August 3, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Hsien-Wen Liu, Min-Chen Lin
  • Patent number: 11069789
    Abstract: A method to fabricate a non-planar memory device including forming a multi-layer silicon nitride structure substantially perpendicular to a top surface of the substrate. There may be multiple non-stoichiometric silicon nitride layers, each including a different or same silicon richness value from one another.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: July 20, 2021
    Assignee: MONTEREY RESEARCH, LLC
    Inventors: Yi Ma, Shenqing Fang, Robert Ogle
  • Patent number: 10985151
    Abstract: The present disclosure relates to a semiconductor package and a method for preparing the same. The semiconductor package includes a lower semiconductor layer, an upper semiconductor layer, a fixturing structure, and a molding layer. The lower semiconductor layer includes an attached region and a fixturing region adjacent to the attached region. The upper semiconductor layer is disposed over the attached region. The fixturing structure is disposed adjacent to the upper semiconductor layer. The fixturing structure has at least one fixturing hole, the fixturing hole has an opening corresponding to the fixturing region, and the opening has a first width. The molding layer covers side walls of the upper semiconductor layer. The molding layer has at least one fixturing protrusion extending into the fixturing hole, the fixturing protrusion has a first expanding portion below the opening, and the first expanding portion has a second width greater than the first width.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: April 20, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Kuo-Hui Su
  • Patent number: 10957543
    Abstract: A method includes forming an interlayer dielectric (ILD) and a gate structure over a substrate. The gate structure is surrounded by the ILD. The gate structure is etched to form a recess. A first dielectric layer is deposited over sidewalls and a bottom of the recess and over a top surface of the ILD using a first Si-containing precursor. A second dielectric layer is deposited over and in contact with the first dielectric layer using a second Si-containing precursor different from the first Si-containing precursor. A third dielectric layer is deposited over and in contact with the second dielectric layer using the first Si-containing precursor. Portions of the first, second, and third dielectric layer over the top surface of the ILD are removed.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Yun Peng, Chung-Chi Ko, Keng-Chu Lin
  • Patent number: 10937689
    Abstract: In one embodiment, a trench may be formed in a dielectric surface, and the trenched may be lined with a liner. The trench may be filled with a metal, and the metal may be recessed below an opening of the trench. The liner may be converted into a dielectric, and a hard mask may be deposited into the trench.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: March 2, 2021
    Assignee: INTEL CORPORATION
    Inventors: Manish Chandhok, Satyarth Suri, Tristan A. Tronic, Christopher J. Jezewski, Richard E. Schenker
  • Patent number: 10937946
    Abstract: A semiconductor structure is provided in the present invention, including a substrate having a device region and an alignment mark region defined thereon, a dielectric layer disposed on the substrate, a conductive via formed in the dielectric layer on the device region, a first trench formed in the dielectric layer on the alignment mark, a plurality of second trenches formed in the dielectric layer directly under the first trench and exposed from a bottom surface of the first trench, and a memory stacked structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trench.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: March 2, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chia-Chang Hsu, Rai-Min Huang
  • Patent number: 10818584
    Abstract: A package substrate including a redistribution structure and a core is provided. The redistribution structure has a first redistribution surface and a bonding pad disposed on the first redistribution surface. The core is disposed on the redistribution structure and has a first core surface facing towards the first redistribution surface of the redistribution structure. The core has a first core pad disposed on the first core surface and directly bonded to the bonding pad, and the first core pad is offset from the bonding pad. A package structure is also provided.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: October 27, 2020
    Inventor: Dyi-Chung Hu
  • Patent number: 10811385
    Abstract: A wafer-level system-in-package structure and an electronic apparatus are provided. The wafer-level system-in-package structure includes a substrate having a plurality of first chips formed therein. A first chip is formed by being grown on the substrate through a semiconductor process. The wafer-level system-in-package structure also includes an encapsulation layer having a plurality of second chips embedded therein. The encapsulation layer covers the substrate and the first chips. At least one of the plurality of second chips is electrically connected to at least one of the plurality of first chips through a conductive bump, and electrically-connected first and second chips have an overlapping portion.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: October 20, 2020
    Assignee: Ningbo Semiconductor International Corporation
    Inventor: Mengbin Liu
  • Patent number: 10804360
    Abstract: A semiconductor layer has a first face, a second face, and a first side face. A silicon carbide substrate has a third face facing the second face, a fourth face, and a second side face. A first electrode layer forms an interface with part of the first face. An insulation film is provided around the first electrode layer on the first face of the semiconductor layer. A second electrode layer is provided on the fourth face and extends outward of the interface between the first face and the first electrode layer in an in-plane direction. A crush layer is provided on the first side face of the semiconductor layer and on the second side face of the silicon carbide substrate. The thickness of the crush layer on the second side face is greater than the thickness of the crush layer on the first side face.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: October 13, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Kazunari Nakata
  • Patent number: 10790154
    Abstract: Methods and systems for line cut by multi-color patterning techniques are presented. In an embodiment, a method may include providing a substrate. The method may also include forming a first feature on the substrate, the first feature having a cap formed of a first material. Additionally, the method may include forming a second feature on the substrate, the second feature having a cap formed of a second material. In still a further embodiment, the method may include selectively removing the second feature using an etch process that etches the first material at a first etch rate and etches the second material at a second etch rate, wherein the second etch rate is higher than the first etch rate.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: September 29, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Eric Chih-Fang Liu, Akiteru Ko
  • Patent number: 10685964
    Abstract: A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: June 16, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chih-Chieh Tsai, Pin-Hong Chen, Tzu-Chieh Chen, Tsun-Min Cheng, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Shih-Fang Tzou
  • Patent number: 10682523
    Abstract: A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung
  • Patent number: 10664019
    Abstract: This is directed to connecting two or more elements using an intermediate element constructed from a material that changes between states. An electronic device can include one or more components constructed by connecting several elements. To provide a connection having a reduced or small size or cross-section and construct a component having high tolerances, a material can be provided in a first state in which it flows between the elements before changing to a second state in which it adheres to the elements and provides a structurally sound connection. For example, a plastic can be molded between the elements. As another example, a composite material can be brazed between the elements. In some cases, internal surfaces of the elements can include one or more features for enhancing a bond between the elements and the material providing the interface between the elements.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: May 26, 2020
    Assignee: APPLE INC.
    Inventors: Scott A. Myers, Mattia Pascolini, Richard Hung Minh Dinh, Trent Weber, Robert Schlub, Josh Nickel, Robert Hill, Nanbo Jin, Tang Yew Tan
  • Patent number: 10658252
    Abstract: A semiconductor structure with a stop layer for planarization process therein and a method for forming the same is disclosed. The method includes the steps of: forming a trench in a substrate and between active areas; filling the trench with isolation layer; doping the isolation layer with an element to form a doped isolation region; annealing the doped isolation region; and planarizing the annealed and doped isolation region and measuring a planarization depth thereof. The coefficients of thermal expansion (CTEs) of the stop layer, the dielectric layer, and the active area are different.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jia-Ming Lin, Wei-Ken Lin, Shiu-Ko JangJian, Chun-Che Lin
  • Patent number: 10658175
    Abstract: A semiconductor device and a manufacturing method therefor are provided. The semiconductor device includes a semiconductor substrate including a trench used for a source/drain region; and a SiGe seed layer formed simultaneously on the sidewall and bottom of the trench, and the SiGe seed layer on the sidewall of the trench has an uneven thickness with a maximum thickness at a location corresponding to the channel region in the semiconductor substrate. The semiconductor device and the manufacturing method therefor according to the present disclosure enable the SiGe seed layer to block diffusion of elements such as boron more effectively.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: May 19, 2020
    Assignee: Semiconductor Manufacturing International Corporation (Shanghai)
    Inventor: Ajin Tu
  • Patent number: 10636798
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first trench and a second trench in substrate on the memory region, wherein a width of the second trench is greater than a width of the first trench; forming a first liner, a second liner, and a third liner in the first trench and the second trench; performing a surface treatment process to lower stress of the third liner; and planarizing the third liner, the second liner, and the first liner to form a first isolation structure and a second isolation structure.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: April 28, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Shan Su, Chia-Wei Wu, Ting-Pang Chung
  • Patent number: 10580656
    Abstract: A semiconductor wafer having a main surface is provided. A first etch resistant mask is provided on the main surface. A first reactive ion etching step that forms a first group of trenches using the first etch resistant mask is performed. Each of the trenches in the first group is covered with a second etch resistant mask after performing the first reactive ion etching step. A second reactive ion etching step that forms a second group of trenches using one or both of the first etch resistant mask and the second etch resistant mask is performed. The trenches in the second group are laterally offset from the trenches in the first group. The first and second reactive ion etching processes are performed such that a depth of the trenches of the first group is substantially equal to a depth of the trenches in the second group.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: March 3, 2020
    Assignee: Infineon Technologies AG
    Inventors: Marija Borna Tutuc, Daniel Tutuc, Andrew Christopher Graeme Wood
  • Patent number: 10546923
    Abstract: Some embodiments include an integrated assembly having a region of first semiconductor material. The region has an upper surface along a cross-section. The upper surface has a flat-topped peak and a concavity adjacent the flat-topped peak. A pillar of second semiconductor material is over the region and directly against the region. The pillar extends vertically from the upper surface. Some embodiments include a method of forming an integrated assembly. A construction is formed to have a semiconductor region, and to have an insulative region extending over the semiconductor region and alongside the semiconductor region. A combination of three etches is utilized to expose an upper surface of the semiconductor region and to modify the upper surface of the semiconductor region to form said upper surface to include, along a cross-section, a flat-topped peak portion and an adjacent concavity portion.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: January 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Pranav P. Sharma, Vinay Nair, Sanjeev Sapra
  • Patent number: 10541205
    Abstract: Fabrication methods for monolithic dies that integrate multiple integrated circuits, such as System-on-Chips are described. A substrate having an interconnect may be coupled via electrical terminations to the integrated circuits. Fabrication methods provide multiple electrical termination regions on a surface, with each region having geometrical properties that are appropriate for the coupled integrated circuit. Electrical terminations with different directions may be produced employing a single reactive ion etching process under conditions that enhance micro loading effects during fabrication.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: January 21, 2020
    Assignee: INTEL CORPORATION
    Inventors: Ning Cheng, Fangyun Richter, Andy Louie Lee
  • Patent number: 10527954
    Abstract: A system for measuring overlay from a multi-layer overlay target for use in imaging based metrology is disclosed. The system is configured for measuring overlay from a multi-layer overly target that includes three or more target structures, wherein a first target structure is disposed in a first process layer, a second target structure is disposed in a second process layer, and at least a third target structure is disposed in at least a third process layer. The system includes an illumination source configured to illuminate the target structures of the multi-layer overlay target, a detector configured to collect light reflected from the target structures, and one or more processors configured to execute a set of program instructions to determine overlay error between two or more structures based on the collected light from the plurality of targets.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: January 7, 2020
    Assignee: KLA-Tencor Corporation
    Inventors: Daniel Kandel, Vladimir Levinski, Guy Cohen
  • Patent number: 10490694
    Abstract: A method of manufacturing a plurality of light emitting elements, the method includes: providing a semiconductor wafer; dividing the p-side nitride semiconductor layer into a plurality of demarcated element regions; forming a protective layer on regions including an outer periphery of an upper surface of the p-side nitride semiconductor layer of each of the plurality of demarcated element regions and exposed side surfaces in the semiconductor structure that are formed by the selectively removing the portion of the p-side nitride semiconductor layer; reducing a resistance of regions of the p-side nitride semiconductor layer; and dividing the semiconductor wafer into a plurality of light emitting elements.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: November 26, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Kazuhiro Nagamine, Yoshiki Inoue, Susumu Toko, Junya Narita
  • Patent number: 10490556
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first trench and a second trench in substrate on the memory region, wherein a width of the second trench is greater than a width of the first trench; forming a first liner, a second liner, and a third liner in the first trench and the second trench; performing a surface treatment process to lower stress of the third liner; and planarizing the third liner, the second liner, and the first liner to form a first isolation structure and a second isolation structure.
    Type: Grant
    Filed: July 29, 2018
    Date of Patent: November 26, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Shan Su, Chia-Wei Wu, Ting-Pang Chung
  • Patent number: 10446480
    Abstract: A through-substrate vias structure includes a substrate having opposing first and second major surfaces. One or more conductive via structures are disposed extending from the first major surface to a first vertical distance within the substrate. A recessed region extends from the second major surface to a second vertical distance within the substrate and adjoining a lower surface of the conductive via. In one embodiment, the second vertical distance is greater than the first vertical distance. A conductive region is disposed within the recessed region and is configured to be in electrical and/or thermal communication with the conductive via.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: October 15, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Francis J. Carney
  • Patent number: 10396150
    Abstract: Various improvements in vertical transistors, such as IGBTs, are disclosed. The improvements include forming periodic highly-doped p-type emitter dots in the top surface region of a growth substrate, followed by growing the various transistor layers, followed by grounding down the bottom surface of the substrate, followed by a wet etch of the bottom surface to expose the heavily doped p+ layer. A metal contact is then formed over the p+ layer. In another improvement, edge termination structures utilize p-dopants implanted in trenches to create deep p-regions for shaping the electric field, and shallow p-regions between the trenches for rapidly removing holes after turn-off. In another improvement, a dual buffer layer using an n-layer and distributed n+ regions improves breakdown voltage and saturation voltage. In another improvement, p-zones of different concentrations in a termination structure are formed by varying pitches of trenches. In another improvement, beveled saw streets increase breakdown voltage.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: August 27, 2019
    Assignee: MaxPower Semiconductor, Inc.
    Inventor: Hamza Yilmaz
  • Patent number: 10395927
    Abstract: The present application relates to the field of semiconductor technologies, and discloses methods for manufacturing a semiconductor device. The manufacturing method includes: forming an etchable material layer on a substrate; forming multiple openings on the etchable material layer by means of patterning processing to determine a position of a core; etching the substrate at bottoms of the multiple openings, so that the bottoms of the multiple openings extend into the substrate; depositing a material of the core to fill the multiple openings; etching the material of the core so as to expose the etchable material layer; removing the etchable material layer to leave multiple cores; depositing spacers; over etching the spacers so as to expose the multiple cores, and etching a part of the substrate, where an etching depth of the substrate is the same as a depth to which the openings extend into the substrate; and removing the multiple cores.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: August 27, 2019
    Assignees: SEMICONDUCTOR MFG. INTL. (SHANGHAI) CORP., SEMICONDUCTOR MFG. INTL. (BEIJING) CORP.
    Inventor: Cheng Long Zhang
  • Patent number: 10389090
    Abstract: A method of forming a pair of edge-emitting lasers is provided. The method includes forming a mesa from a substrate, forming a cover layer on the substrate around the mesa, and forming a first barrier layer on each of opposite sidewalls of the mesa. The method further includes forming a quantum well layer on each of the barrier layers, forming a second barrier layer on each of the quantum well layers, and forming a cladding layer on each of the second barrier layers.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Effendi Leobandung, Ning Li, Tak H. Ning
  • Patent number: 10381403
    Abstract: A method for forming a MRAM device free of seal ring peeling defect, and the resulting device, are provided. Embodiments include forming magnetic tunnel junction (MTJ) over a metallization layer in a seal ring region of an MRAM device; forming a metal filled via connecting the MTJ and the metallization layer; forming a tunnel junction via over the MTJ; and forming a top electrode over the tunnel junction via.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: August 13, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yi Jiang, Bharat Bhushan, Curtis Chun-I Hsieh, Mahesh Bhatkar, Wanbing Yi, Juan Boon Tan
  • Patent number: 10381035
    Abstract: Methods for magnetic recording are provided. The method can include: assembling a plurality of nanoparticles into a pattern on a disc; applying a polymer composition onto the pattern of nanoparticles; curing the polymer composition to form a polymer film on the disc, wherein the plurality of nanoparticles are immobilized in the pattern within the polymer film upon curing; and removing the polymer film containing the plurality of nanoparticles in the pattern. Diffraction gratings are also provided that can include a polymeric film comprising a plurality of nanoparticles immobilized in a pattern, wherein the polymer film defines a curvature.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: August 13, 2019
    Assignee: University of South Carolina
    Inventors: Thomas M. Crawford, Longfei Ye, Jason Ryan Henderson
  • Patent number: 10374033
    Abstract: Some embodiments include an integrated assembly having a region of first semiconductor material. The region has an upper surface along a cross-section. The upper surface has a flat-topped peak and a concavity adjacent the flat-topped peak. A pillar of second semiconductor material is over the region and directly against the region. The pillar extends vertically from the upper surface. Some embodiments include a method of forming an integrated assembly. A construction is formed to have a semiconductor region, and to have an insulative region extending over the semiconductor region and alongside the semiconductor region. A combination of three etches is utilized to expose an upper surface of the semiconductor region and to modify the upper surface of the semiconductor region to form said upper surface to include, along a cross-section, a flat-topped peak portion and an adjacent concavity portion.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Pranav P. Sharma, Vinay Nair, Sanjeev Sapra
  • Patent number: 10332791
    Abstract: A semiconductor device includes an insulating interlayer disposed on a substrate, a first protection pattern, a first barrier pattern, a first adhesion pattern, and a first conductive pattern. The insulating interlayer includes a via hole and a first trench. The via hole extends through a lower portion of the insulating interlayer. The first trench is connected to the via hole and extends through an upper portion of the insulating interlayer. The first protection pattern covers a lower surface and sidewalls of the via hole and a portion of a lower surface and a lower sidewall of the first trench, and includes a conductive material. The first barrier pattern covers the protection pattern and an upper sidewall of the first trench. The first adhesion pattern covers the first barrier pattern. The first conductive pattern is disposed on the first adhesion pattern, and fills the via hale and the first trench.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho-Yun Jeon, Rak-Hwan Kim, Byung-Hee Kim, Kyoung-Hee Nam, Jong-Jin Lee, Jae-Won Hwang
  • Patent number: 10325804
    Abstract: In accordance with an embodiment of the present invention, a method of fabricating a semiconductor device includes forming openings partially filled with a sacrificial material, where the openings extend into a semiconductor substrate from a first side. A void region is formed in a central region of the openings. An epitaxial layer is formed over the first side of the semiconductor substrate and the openings, where the epitaxial layer covers the void region. From a second side of the semiconductor substrate opposite to the first side, the semiconductor substrate is thinned to expose the sacrificial material. The sacrificial material in the openings is removed and the epitaxial layer is exposed. A conductive material is deposited on the exposed surface of the epitaxial layer.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: June 18, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Oliver Hellmund, Johannes Baumgartl, Iris Moder, Ingo Muri, Thomas Christian Neidhart, Hans-Joachim Schulze
  • Patent number: 10256149
    Abstract: A semiconductor base substrate having a substantially planar growth surface is provided. A first type III-V semiconductor layer is epitaxially grown on the growth surface. First and second trenches that vertically extend from an upper surface of the first type III-V semiconductor layer at least to the growth surface are formed. The first and second trenches are filled with a filler material that is different from material of the type III-V semiconductor layer. A cut that separates the first type III-V semiconductor layer and the base substrate into two discrete semiconductor chips is formed. The cut is formed in a lateral section of the first type III-V semiconductor layer that is between the first and second trenches.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: April 9, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Arno Zechmann, Gianmauro Pozzovivo
  • Patent number: 10204843
    Abstract: A semiconductor device structure and a method of fabricating the same are provided. The method for manufacturing a semiconductor structure includes forming a dielectric layer over a substrate and forming a first structure through the dielectric layer such that a first portion of the dielectric layer is disposed in between the first structure. The method for manufacturing a semiconductor structure further includes forming a first via hole and a second via hole through the first portion of the dielectric layer and forming a trench connecting the first via hole and the second via hole in the dielectric layer. The method for manufacturing a semiconductor structure further includes forming a conductive feature in the first via hole, the second via hole, and the trench. In addition, the first structure and the dielectric layer are made of different materials from each other.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: February 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ruei Lin, Yen-Ming Peng, Han-Wei Yang, Chen-Chung Lai
  • Patent number: 10170461
    Abstract: Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the substrate, and a first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and is spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and is spaced apart from the first and second conductive pads. A fourth conductive pad is disposed over the interconnect structure and is spaced apart from the first, second, and third conductive pads. A first ESD protection element is electrically coupled between the first and second pads; and a second ESD protection element is electrically coupled between the third and fourth pads. A first device under test is electrically coupled between the first and third conductive pads; and a second device under test is electrically coupled between the second and fourth pads.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jen-Chou Tseng, Ming-Fu Tsai, Tzu-Heng Chang
  • Patent number: 10141274
    Abstract: A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: November 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Edward C. Cooney, III, Fen Chen, Jonathan M. Pratt, Jason P. Ritter, Patrick S. Spinney, Anna Tilley
  • Patent number: 10115665
    Abstract: A resistor structure composed of a metal liner is embedded within a MOL dielectric material and is located, at least in part, on a surface of a doped semiconductor material structure. The resistor structure is located on a same interconnect level of the semiconductor structure as a lower contact structure and both structures are embedded within the same MOL dielectric material. The metal liner that provides the resistor structure is composed of a metal or metal alloy having a higher resistivity than a metal or metal alloy that provides the contact metal of the lower contact structure.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: October 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Chih-Chao Yang
  • Patent number: 10083860
    Abstract: A method of forming a semiconductor structure includes; (i) forming an isolation structure in a semiconductor substrate, the isolation structure electrically isolating device regions of the semiconductor substrate; (ii) forming a gate structure extending from one of the device regions to the isolation structure; (iii) forming a resist protective oxide layer overlaying the gate structure and the isolation structure; and (iv) patterning the resist protective oxide layer to form a patterned resist protective oxide that covers at least a portion of the isolation structure and a portion of the gate structure on the isolation structure.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Liang Liao, Chia-Yao Liang, Jui-Long Chen, Sheng-Yuan Lin, Yi-Lii Huang, Kuo-Hsi Lee, Po-An Chen
  • Patent number: 10079199
    Abstract: A through-substrate vias structure includes a substrate having opposing first and second major surfaces. One or more conductive via structures are disposed extending from the first major surface to a first vertical distance within the substrate. A recessed region extends from the second major surface to a second vertical distance within the substrate and adjoining a lower surface of the conductive via. In one embodiment, the second vertical distance is greater than the first vertical distance. A conductive region is disposed within the recessed region and is configured to be in electrical and/or thermal communication with the conductive via.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: September 18, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Francis J. Carney
  • Patent number: 10056305
    Abstract: According to various embodiments, a wafer arrangement may be provided, the wafer arrangement may include: a wafer including at least one electronic component having at least one electronic contact exposed on a surface of the wafer; an adhesive layer structure disposed over the surface of the wafer, the adhesive layer structure covering the at least one electronic contact; and a carrier adhered to the wafer via the adhesive layer structure, wherein the carrier may include a contact structure at a surface of the carrier aligned with the at least one electronic contact so that by pressing the wafer in direction of the carrier, the contact structure can be brought into electrical contact with the at least one electronic contact of the at least one electronic component.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: August 21, 2018
    Assignee: Infineon Technologies Dresden GmbH
    Inventors: Peter Brockhaus, Uwe Koeckritz
  • Patent number: 10026724
    Abstract: A method of manufacturing a semiconductor package includes forming at least two partial package chip stacks, each partial package chip stack including at least two semiconductor chips each including a plurality of through substrate vias (TSVs), and including a first mold layer surrounding side surfaces of the at least two semiconductor chips, and sequentially mounting the at least two partial package chip stacks on a package substrate in a direction vertical to a top surface of the package substrate, such that the at least two partial package chip stacks include a first partial package chip stack and a second partial package chip stack directly connected to the first partial package chip stack.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: July 17, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-hwang Kim, Jong-bo Shim, Sang-uk Han, Cha-jea Jo, Gun-ho Chang
  • Patent number: 10002862
    Abstract: A solid-state light source (SSLS) with an integrated short-circuit protection approach is described. A device can include a SSLS having an n-type semiconductor layer, a p-type semiconductor layer and a light generating structure formed there between. A field-effect transistor (FET) can be monolithically connected in series with the SSLS. The FET can have a saturation current that is greater than the normal operating current of the SSLS and less than a predetermined protection current threshold specified to protect the SSLS and the FET.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: June 19, 2018
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Grigory Simin, Michael Shur
  • Patent number: 9984939
    Abstract: A method for manufacturing a semiconductor device includes providing a substrate, performing an N-type dopant implantation into a first region of the substrate to form an N-well, removing a portion of the substrate to form a first set of fins on the N-well and a second set of fins on a second region of the substrate adjacent the N-well, filling gap spaces between the fins to form an isolation region, and performing a P-type dopant implantation into the second region to form a P-well adjacent the N-well. The N-well and the P-well are formed separately at different times. The loss of the P-type dopant ions due to the diffusion of P-type dopant ions in the P-well into the isolation region can be eliminated, and the damage to the fins caused by N-type dopant ions can be avoided.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 29, 2018
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Fei Zhou
  • Patent number: 9960076
    Abstract: A method of fabricating a semiconductor device includes forming trenches filled with a sacrificial material. The trenches extend into a semiconductor substrate from a first side. An epitaxial layer is formed over the first side of the semiconductor substrate and the trenches. From a second side of the semiconductor substrate opposite to the first side, the sacrificial material in the trenches is removed. The trenches are filled with a conductive material.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: May 1, 2018
    Assignee: Infineon Technologies AG
    Inventors: Oliver Hellmund, Ingo Muri, Johannes Baumgartl, Iris Moder, Thomas Christian Neidhart, Hans-Joachim Schulze
  • Patent number: 9953966
    Abstract: A semiconductor device having a semiconductor substrate is provided. The semiconductor substrate includes an integrated circuit, which includes multi-layer structured metallization and inter-metal dielectric. The integrated circuit is below a passivation, which is over a metal structure. The metal structure includes a metal pad and an under bumper metallurgy, which is over and aligned with the metal pad. The metal pad is electrically connected to the integrated circuit, and the under bumper metallurgy is configured to electrically connect to a conductive component of another semiconductor device. The integrated circuit further includes a conductive trace, which is below and aligned with the metal structure. The conductive trace is connected to a power source such that an electromagnetic field is generated at the conductive trace when an electric current from the power source passes through the conductive trace.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: April 24, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Chun Miao, Shih-Wei Liang, Kai-Chiang Wu, Yen-Ping Wang
  • Patent number: 9917030
    Abstract: The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary semiconductor structure includes an insulation material layer having a top semiconductor layer having transistor regions formed on a top surface of the insulation material layer; isolation structures formed in the top semiconductor layer between adjacent transistor regions; a first dielectric layer formed over the top semiconductor layer; a first heat-conducting layer having a thermal conductivity higher than a thermal conductivity of the isolation structure and passing through the insulation material layer, the top semiconductor layer and the first dielectric layer; a second dielectric layer formed over the first dielectric layer; an interconnect structure formed in the second dielectric layer; and a bottom layer conductive via passing through the heat-conducting layer and a partial thickness of the second dielectric layer, and electrically connected with the interconnect structure.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: March 13, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Hong Tao Ge, Xiao Yan Bao
  • Patent number: 9894787
    Abstract: This is directed to systems and methods for coupling sections of an electronic device together. Sections of an electronic device can be coupled together via “knuckles.” The particular shape and structure of the knuckles can be based on various design considerations. For example, in some embodiments each section can function as an individual antenna. In this case, the knuckles can be designed in order to provide electrical isolation between the sections, thus allowing proper operation of the antennas. For example, the knuckles can be formed from a dielectric material, etc. As another design example, the knuckles can be designed in order to provide increased strength in areas of high strain, and/or to counteract torsional twisting in areas of high impact. As yet another design example, the knuckle can be designed in a manner that is aesthetically pleasing or which otherwise meets cosmetic requirements.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: February 13, 2018
    Assignee: APPLE INC.
    Inventors: Nicholas Merz, Daniel Jarvis
  • Patent number: 9881874
    Abstract: According to one embodiment, a forming method of superposition checking marks includes forming a first superposition checking mark to have a first step with respect to an arrangement surface for the first superposition checking mark, forming an opaque film having a second step resulting from the first step on the arrangement surface, and forming on the opaque film a second superposition checking mark provided with a transparent film allowing observation of the second step.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: January 30, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kenichi Yasuda, Shinya Arai