Planarization polishing method and method for manufacturing semiconductor device

Abstract

Disclosed herein is a planarization polishing method for polishing a polishing-target wafer for a planarized surface, the method including the step of polishing a polishing-target surface into a planarized surface by using polishing slurry that contains an abrasive grain and a surfactant encapsulated through surface coating.

Description

CROSS REFERENCES TO RELATED APPLICATIONS

The present invention contains subject matter related to Japanese Patent Application JP 2007-029798 filed in the Japan Patent Office on Feb. 8, 2007, the entire contents of which being incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a planarization polishing method used in a semiconductor manufacturing process and a method for manufacturing a semiconductor device.

2. Description of the Related Art

In a manufacturing process for a semiconductor device, i.e., a so-called semiconductor integrated circuit, a chemical mechanical polishing (CMP) technique is widely used as a technique for surface planarization in a step for forming shallow trench isolation (STI) regions serving as element isolation regions of the semiconductor integrated circuit. In general, STI regions in a semiconductor device are formed in the manner shown in FIG. 6.

Initially, as shown in FIG. 6A, a silicon nitride (SiN) film 2 is deposited on a surface of a silicon semiconductor substrate 1.

Subsequently, a resist mask (not shown) is formed on the silicon nitride film 2 by using a photolithography technique. This resist mask has a required pattern having apertures in the areas corresponding to the STI regions that are to be formed. Referring next to FIG. 6B, the silicon nitride film 2 is patterned by dry etching through the resist mask, and trenches 3 with the required pattern are formed in the silicon substrate 1 by dry etching with use of the silicon nitride film 2 as the etching mask. The regions in which the silicon nitride film 2 is formed will serve as element formation regions later.

Referring next to FIG. 6C, a silicon oxide (SiO2) film 4 is buried in the trenches 3 by chemical vapor deposition (CVD). In this burying, the silicon oxide film 4 is deposited also on the substrate surface (i.e., the silicon nitride film 2) outside the trenches 3.

Subsequently, as shown in FIG. 6D, the silicon oxide (SiO2) film deposited on the substrate surface outside the trenches 3 is polished and removed by CMP. This forms STI regions (element isolation regions) 5 arising from the burying of the silicon oxide film 4 in the trenches 3. In a subsequent step, the silicon nitride film 2 is removed, followed by formation of required semiconductor elements in the areas from which the silicon nitride film 2 has been removed.

Recent enhancement in the integration degree of semiconductor elements requires CMP treatment for the formation of the STI regions 5 (so-called STI-CMP process) to have higher planarization performance. However, silica-based slurry, which is used for polishing of an oxide film in related arts, is becoming incapable of meeting the required performance. This is due to unevenness, in the semiconductor wafer plane, of the area rate of the silicon nitride film 2 on which the silicon oxide film 4 is formed into a projection shape, i.e., the area rate of the region that will serve as the element formation region later. In a region in which the area rate of the silicon nitride film 2 is high, a silicon oxide film 4a with a large-height projection shape is deposited. In a region in which the area rate of the silicon nitride film 2 is low, a silicon oxide film 4b with a small-height projection shape is deposited.

Specifically, until the completion of the polishing-removal of the silicon oxide film 4a in a region in which the area rate of a projection is high, the silicon oxide film 4 in the trenches 3 around a region in which the area rate of a projection is low is excessively polished due to the selection ratio of the silicon oxide film 4 to the silicon nitride film 2. This excessive polishing causes so-called dishing 6 as shown in FIG. 6E, which deteriorates the planarity. The planarity deterioration causes the lowering of the reliability and yield of semiconductor elements.

As a method for improving planarization in the STI-CMP process, a polishing method is known that employs ceria-based slurry containing ceria (cerium oxide: CeO2) abrasive grains and an additive agent (so-called surfactant). In this method, in a projection part on a polishing-target surface, the additive agent is dislodged due to pressure concentration in the polishing and thus the polishing proceeds. In contrast, in a recess part to which low pressure is applied, the polishing is suppressed by the additive agent absorbed in the recess part. That is, this method is intended to selectively polish the projection part to thereby obtain a polished surface with high planarity. This ceria-based slurry is advantageous over the silica-based slurry not only in the planarity but also in the polishing rate and the selection ratio.

A high-planarization polishing method employing ceria abrasive grains is disclosed in e.g. Japanese Patent Laid-open No. 2004-14624 (hereinafter refereed to as Patent Document 1). In this method, a CMP polishing liquid (polishing slurry) that contains cerium oxide particles and a surfactant having selective absorbability to a silicon nitride film is used, and high-planarization polishing is carried out by using an effect of decreasing the polishing rate of a silicon nitride film due to the surfactant.

SUMMARY OF THE INVENTION

However, even for the STI-CMP process employing ceria-based slurry, it is becoming difficult to obtain a polished surface with high planarity due to the influence of difference in the density of the element formation region. A detailed description about this problem will be made below with reference to FIGS. 7A and 7B. This description will deal with the case of using ceria-based slurry containing ceria abrasive grains 12 and a surfactant 13 that acts on the abrasive grains 12, specifically, ceria-based slurry containing the surfactant 13 that offers an effect of protecting the film surface of the silicon oxide film 4 in the recesses 3. As shown in FIGS. 7A and 7B, when polishing is started in such a way that the ceria-based slurry is used and a polishing pad 11 is pressed against a polishing-target surface, high pressure is applied to a projection 4a and therefore the surfactant 13 is removed from the projection 4a. Thus, selective polishing proceeds for the projection 4a and hence the planarization of the polishing-target surface is progressed. However, in the case of using ceria-based slurry, the polishing rate of the silicon oxide film 4 is higher than that of the silicon nitride film 2. Accordingly, the dishing 6 becomes noticeable in a region in which the area of the element isolation region 5 is large in particular, which deteriorates the planarity.

Moreover, the ceria-based slurry has also a problem of causing more scratches compared with silica-based slurry. In particular, if scratches are generated in an element formation region and reach the underlying Si substrate, the yield is problematically deteriorated.

There is a need for the present invention to provide a planarization polishing method that allows polishing based on CMP to offer higher planarity, and a method for manufacturing a semiconductor device with use of this planarization polishing method.

According to an embodiment of the present invention, there is provided a planarization polishing method for polishing a polishing-target wafer for a planarized surface. The method includes the step of polishing a polishing target surface into a planarized surface by using polishing slurry that contains an abrasive grain and a surfactant encapsulated through surface coating.

In this planarization polishing, it is preferable that the polishing-target surface is an oxide film.

According to another embodiment of the present invention, there is provided a method for manufacturing a semiconductor device. The method includes the step of, for formation of an STI region serving as an element isolation region, polishing an oxide film deposited on a region other than a trench of a semiconductor substrate for a planarized surface by using polishing slurry that contains an abrasive grain and a surfactant encapsulated through surface coating.

In these methods, the surfactant contained in the polishing slurry is encapsulated through coating of its surface. Therefore, the surfactant is selectively supplied only to a small-height region that should be protected by the surfactant through the breaking of the capsules. In contrast, in the other region, the capsules are not broken, so that no protection effect is provided and thus the polishing proceeds. This feature allows high-planarization polishing.

In the planarization polishing method according to one embodiment of the present invention, the surfactant directly acts on the polishing-target surface in linkage with the progression of polishing in the polishing-target wafer plane, and thus high-planarization polishing can be carried out.

In the method for manufacturing a semiconductor device according to another embodiment of the present invention, the surfactant directly acts on the polishing-target surface in linkage with the progression of polishing in the polishing-target wafer plane, and thus high-planarization polishing free from the influence of difference in the density of the element formation region can be carried out.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a structural diagram showing the schematic structure of CMP apparatus used in embodiments of the present invention;

FIG. 2 is a schematic sectional view of an encapsulated surfactant;

FIGS. 3A to 3C are manufacturing step diagrams showing a planarization polishing method and a method for manufacturing a semiconductor device with use of this polishing method according to one embodiment of the present invention;

FIGS. 4D to 4G are manufacturing step diagrams showing the planarization polishing method and the method for manufacturing a semiconductor device with use of this polishing method according to the embodiment;

FIG. 5 is a step diagram showing a halfway state in a planarization polishing method and a method for manufacturing a semiconductor device with use of this polishing method according to another embodiment of the present invention;

FIGS. 6A to 6E are manufacturing step diagrams showing an example of a method for manufacturing a semiconductor device with use of a related-art planarization polishing method; and

FIGS. 7A and 7B are diagrams for explaining polished states in a related art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will be described below with reference to the drawings. It should be noted that embodiments of the present invention are not limited to the following exemplification.

In the following description, the embodiments are applied to manufacturing of a semiconductor device, specifically, a so-called semiconductor integrated circuit, and particularly to planarization polishing of an oxide film by CMP for formation of element isolation regions based on STI for the semiconductor integrated circuit. In the embodiments, the polishing-target film is a high-density plasma SiO2 film as one example.

FIG. 1 shows the schematic structure of general CMP apparatus used for the polishing of the embodiments. This CMP apparatus 21 has a platen 23 that is disposed rotatably around a rotation shaft 22, and a polishing pad 24 is disposed on the platen 23. Above the polishing pad 24, a slurry feed pipe 26 for supplying polishing slurry 25 according to the embodiments is disposed. A polishing target that is to be subjected to planarization polishing, i.e., a semiconductor wafer 27 in the present example, is so disposed that its polishing-target surface abuts against the polishing pad 24. A polishing head 28 is brought into abutting contact with the backside of the semiconductor wafer 27 with a required load. The polishing head 28 is so configured as to be rotated around a shaft 29 together with the semiconductor wafer 27 while applying the required load to the semiconductor wafer 27.

As shown in FIG. 3A, the semiconductor wafer 27 as the polishing-target wafer has a structure similar to the above-described structure shown in FIG. 6C. Specifically, a silicon nitride (SiN) film 31 is deposited on a surface of a silicon semiconductor substrate 27a, and a resist mask having apertures based on a required pattern is formed on the silicon nitride film 31 by using a photolithography technique. Subsequently, the silicon nitride film 31 is patterned by dry etching through this resist mask, and then trenches 32 based on the required pattern are formed in the silicon substrate 27a by using the silicon nitride film 31 as the etching mask. These trenches 32 are formed at the positions corresponding to STI regions serving as element isolation regions. Subsequently, a silicon oxide (SiO2) film 33 is deposited by CVD across the entire substrate surface in such a manner as to be buried in the trenches 32. In this manner, the semiconductor wafer 27 is formed that has projection regions 33a and 33b of the silicon oxide film depending on difference in the area rate of the silicon nitride film 31, i.e., the projection region 33a that has a high area rate and large height and the projection regions 33b that exist near the projection region 33a and has a low area rate and small height.

Next, a description will be made below about a planarization polishing method employing the CMP apparatus 21 in FIG. 1 according to one embodiment of the present invention and a method for manufacturing a semiconductor device in which the semiconductor wafer 27 is subjected to planarization polishing by using this planarization polishing method to thereby form STI regions.

In the present embodiment, as shown in FIG. 3A, initially the above-described semiconductor wafer 27 is so disposed that its polishing-target surface abuts on the polishing pad 24 of the CMP apparatus 21.

Subsequently, polishing is started in such a way that the polishing slurry 25 according to the present embodiment is dropped on the polishing pad 24 from the slurry feed pipe 26 and the polishing-target surface of the semiconductor wafer 27 held by the polishing head 28 is pressed against the polishing pad 24 to thereby apply a load to the semiconductor wafer 27 as shown in FIGS. 3A and 3B. The polishing slurry 25 contains ceria abrasive grains (not shown) and a surfactant 36 (indicated by the white circles) that is encapsulated through coating of its surface. This surfactant has an effect of protecting the silicon oxide film 33 that is to be polished. As shown in FIG. 2, this encapsulated surfactant 36 is formed by covering a surfactant 37 by a coating wall 35. The specific slurry composition will be described later.

Due to the supply of the polishing slurry 25 on the polishing pad 24 in the state of FIG. 3A, the encapsulated surfactant 36 is attached to the whole of the polishing-target surface, including the projection regions 33a and 33b.

Subsequently, in the state of FIG. 3B, the encapsulated surfactant 36 attached to the projection regions 33a and 33b on the polishing-target surface contacts with the polishing pad 24 and thus is pushed away by the polishing pad 24, so that the dislodged surfactant 36 attaches to recess regions 33c on the polishing-target surface.

Subsequently, polishing of the projection regions is progressed as shown in FIG. 3C. In this polishing, the polishing for the projection regions 33b, which have a low area rate and small height, proceeds fast. Therefore, as shown in enlarged view A, pressure and shear force are applied to the encapsulated surfactant 36 existing in the vicinity of the recess regions.

Consequently, as shown in FIG. 4D, the capsules are broken by the pressure and shear force, so that the surfactant 37 (indicated by the black circles) is discharged.

As shown in FIG. 4E, during the progression of the polishing of the projection region 33a, the recesses 33c are protected by the surfactant 37 and thus the progression of polishing of the recesses 33c is suppressed.

As shown in FIG. 4F, the capsules are broken in linkage with the progression of the polishing of the projection region 33a, so that the surfactant 37 works sequentially. As a result, as shown in FIG. 4G, planarization polishing is carried out across the entire region eventually irrespective of difference in the area rate of the silicon nitride film 31, i.e., difference in the density of the element formation region, and the planarization polishing treatment is completed at the timing when the silicon nitride film 31 is exposed. Thus, a polished surface with high planarity is obtained. In this manner, favorable STI regions 38 are formed without the occurrence of dishing.

Thereafter, the silicon nitride film 31 is removed, and then required semiconductor elements are formed in the element formation regions arising from the removal of the silicon nitride film 31, so that an intended semiconductor device is obtained.

In the procedure shown in FIGS. 3A to 4G, the planarization polishing until the silicon nitride film 31 is exposed is carried out in one time of polishing treatment. However, it is also possible to carry out it in two times of treatment.

Next, a description will be made below about a planarization polishing method in which planarization is carried out in two times of polishing treatment, according to another embodiment of the present invention, and a method for manufacturing a semiconductor device with use of this planarization polishing method. In the present embodiment, first polishing treatment until projection regions 33a and 33b of a silicon oxide film 33 on the polishing-target surface are planarized is carried out by using polishing slurry prepared by adding a capsulated surfactant to ceria-based slurry. Specifically, the procedure of the present embodiment leads to, through the above-described step of FIG. 4F, a step of FIG. 5 in which the silicon oxide film 33 is planarized. Subsequently, second polishing treatment until the silicon nitride film 31 is exposed is carried out, so that the high-planarization polishing for the above-described state of FIG. 4G is completed.

This second polishing treatment may be carried out by using only polishing slurry to which no surfactant is added. In the second polishing treatment, the polishing-target surface has been already planarized and the remaining film is thin. Therefore, without a surfactant, the polishing can be completed in such a way that a polished surface having high planarity is kept (see FIG. 4G). In the second polishing treatment, the same ceria-based slurry as that used in the first treatment may be used. Alternatively, silica-based, alumina-based, or ferric nitrate-based slurry can be used. In terms of scratches, it is desirable to complete a polished surface by using silica-based slurry in particular.

Next, a description will be made below about a specific polishing method that employs polishing slurry containing a surfactant encapsulated through coating thereof. In the method, the required amount (2 wt %, in the present example) of the coated surfactant is added to the polishing slurry in advance, and polishing is carried out under the following condition in such a way that the polishing slurry is supplied on a polishing-target wafer via a polishing pad.

[Polishing Condition]

• Rotation speed of platen: 100 rpm
• Rotation speed of polishing head: 107 rpm
• Polishing pressure: 300 hPa
• Condition of polishing pad conditioner: Ex-situ
• Flow rate of ceria-based slurry (including 2 wt % surfactant): 200 cc/min

The diameter of the ceria particles, i.e., the particle diameter of cerium oxide (CeO2), can be set to 50 nm to 250 nm.

Although acid ceria-based slurry is used as the polishing slurry in the present example, silica-based slurry, alumina-based slurry, ferric nitrate-based slurry, or the like may be used instead of the ceria-based slurry. It is desirable that the additive amount of the coated surfactant be in the range of 0.1 to 10 wt %. This concentration range offers favorable polishing characteristics (planarity, polishing rate).

As a method for supplying the coated surfactant, a method is available in which the coated surfactant is mixed into the polishing slurry in advance and the resultant slurry is supplied. As another method, the coated surfactant may be supplied as an aqueous solution separately from the polishing slurry. Alternatively, a surfactant feed pipe for supplying the surfactant aqueous solution may be communicated with a slurry feed pipe for the supply of the coated surfactant.

As the material of the surfactant that is to be coated, a substance having an effect of suppressing polishing of an oxide film is used. In the present method, alkylbenzene sulfonate is used as the surfactant. Alternatively, e.g. any of the following substances may be used: a fatty acid sodium salt, alkyl sulfate, sulfate ester salt, fatty acid potassium salt, polyoxyethylene alkyl ether sulfate, fatty acid ester, a-olefin sulfonate, monoalkyl phosphate ester salt, alkane sulfonate, amino acid, polyacrylate, polyacrylate ammonium salt, polycarboxylate ammonium salt, sulfosuccinate diester salt, alkylamine hydrochloride, and alkyl ether sulfonate.

As the coating material for encapsulation, a substance that can be easily treated in coating processing and will not alter the surfactant and polishing slurry is used. In the present method, polyurethane resin is used. Alternatively, e.g. any of the following polymer materials may be used as long as the material offers an unreactive combination with the surfactant and slurry: polystyrene resin, polyester resin, polyurea resin, polyamide resin, polyethylene resin, polyvinyl alcohol resin, polycarbonate resin, melamine resin, urea resin, and gelatin.

The size of the surfactant molecules is about 2 nm to 3 nm. The size of the coated surfactant can be set to about 10 nm to 5000 nm. The term “encapsulated surfactant” encompasses a coated single-substance surfactant and a matter arising from coating of an aggregation of plural single-substance surfactants. The thickness of the coating film with respect to the encapsulated surfactant is so designed that the coating film has such mechanical strength as to be broken by polishing pressure and shear force applied to the film at the time of polishing. That is, the mechanical strength of the coating film is set equal to or lower than that by the polishing pressure and shear force.

The methods for coating the surfactant are roughly categorized into chemical methods, physicochemical methods, and mechanical methods. Examples of the surfactant coating method according to the embodiments include seamless encapsulation, interfacial polymerization, in-situ polymerization, drying-in-liquid, coacervation, spray drying, and dry mixing. In particular, as a method for coating the surfactant as a liquid, interfacial polymerization, in-situ polymerization, coacervation, seamless encapsulation, and so on are suitable.

1. Chemical Methods (Coating Film is Formed by Chemical Reaction)

• In interfacial polymerization, separate monomers are supplied from both a dispersed phase and dispersion medium, so that a coating film is formed by polymerization reaction at the surface of the dispersed phase, i.e., at the interface.
• In in-situ polymerization, a monomer and other reactive agents are supplied only from either one of a dispersed phase and dispersion medium, so that a coating film is formed by polymerization reaction at the surface of the core substance.

2. Physicochemical Methods (Coating Film is Formed by Precipitation, Coagulation, or Another Phenomenon)

• In coacervation, a core substance is dispersed in a solution in which resin that will serve as a coating material is dissolved, so that a coating film is formed by the precipitation of the resin around the core substance.
• In drying-in-liquid, an emulsion is prepared by dispersing in a liquid medium a coating material solution that contains a core substance, so that a coating film is formed by removing the solvent through pressure reduction or heating.

3. Mechanical Methods (Coating Film is Formed Mechanically)

• In spray drying, a core substance is added and a coating material solution is turned to a spray state so as to be discharged into hot wind, so that a coating film is formed by evaporating the liquid in which the coating material is dissolved.

4. Other Methods

• In seamless encapsulation, a seamless coating film is formed by using a substance of which liquid becomes a spherical state due to the interfacial tension when being dropped.

In the planarization polishing method and the method for manufacturing a semiconductor device according to the above-described embodiments, polishing slurry to which a coated surfactant is added is used. Therefore, the surfactant as an additive agent directly acts on a polishing-target surface selectively in linkage with the progression of polishing in the polishing-target wafer plane. This allows high-planarization polishing free from the influence of difference in the density of the element formation region with high accuracy and efficiency, which enhances the reliability and yield of semiconductor elements. Furthermore, the use amount of the surfactant can be suppressed to the necessary minimum, and thus the manufacturing cost of the semiconductor device can be reduced.

The planarization polishing method according to the embodiments is carried out by using polishing slurry that contains abrasive grains and a surfactant encapsulated through surface coating. In this polishing method, along with planarization of projections on a polishing-target surface, polishing pressure and shear force are applied to the encapsulated surfactant attached to recesses in the vicinity of the projections. Consequently, the coating film is broken and thus the surfactant is discharged, so that the discharged surfactant selectively suppresses the progression of polishing of the vicinity. In the wafer plane, the surfactant sequentially works in linkage with the progression of polishing of projections. This allows high-planarization polishing free from the influence of difference in the density of the element formation region, and thus enhances the reliability and yield of semiconductor elements.

In the above-mentioned Patent document 1, the surfactant selectively works depending on the kind of film of a polishing-target surface. In contrast, in the embodiments, the surfactant works in linkage with the progression of polishing dependent upon difference in the pattern density. Thus, planarization can be carried out for a polishing-target surface of which entire region is composed of the same material, appearing before exposure of a different kind of material (e.g., when a polishing-target surface is composed of SiO2, SiN is the different kind of material) through the polishing-target surface, and thus higher-planarization polishing is possible. Moreover, because the remaining film is thin at the timing when the high-planarization polishing has been completed, it is also possible to carry out finishing polishing, with the high planarity kept, by using e.g. silica-based slurry involving fewer scratches. This can reduce scratches, which are a problem in ceria-based slurry, and thus enhances the flexibility in the polishing process.

In the above-described examples, the planarization polishing method of the embodiments is applied to polishing of a semiconductor wafer. However, the method can be applied also to polishing of another substrate (wafer) of which polishing-target surface has an oxide film.

It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof

Claims

1. A planarization polishing method for polishing a polishing-target wafer for a planarized surface, the method comprising the step of

polishing a polishing-target surface into a planarized surface by using polishing slurry that contains an abrasive grain and a surfactant encapsulated through surface coating.

2. The planarization polishing method according to claim 1, wherein

the polishing-target surface is an oxide film.

3. The planarization polishing method according to claim 2, wherein

ceria-based polishing slurry that contains a ceria particle as the abrasive grain is used.

4. The planarization polishing method according to claim 2, wherein

the surfactant acts on the oxide film that is to be polished.

5. The planarization polishing method according to claim 2, wherein

the oxide film is a silicon oxide film formed across a trench in a substrate and an underlying silicon nitride film outside the trench, and

the surfactant acts on the silicon oxide film.

6. The planarization polishing method according to claim 2, wherein

polishing is carried out by using first polishing slurry that contains an abrasive grain and a surfactant encapsulated through surface coating until a projection region on a polishing-target surface is planarized, and

subsequent polishing is carried out by using second polishing slurry that contains no surfactant.

7. The planarization polishing method according to claim 1, wherein

mechanical strength of a coating film of the encapsulated surfactant is equal to or lower than mechanical strength by polishing pressure and shear force.

8. A method for manufacturing a semiconductor device, the method comprising the step of

for formation of a shallow trench isolation region serving as an element isolation region, polishing an oxide film deposited on a region other than a trench of a semiconductor substrate for a planarized surface by using polishing slurry that contains an abrasive grain and a surfactant encapsulated through surface coating.

9. The method for manufacturing a semiconductor device according to claim 8, wherein

the oxide film on the region other than the trench is deposited on an underlying film formed of a nitride film.

10. The planarization polishing method according to claim 8, wherein

ceria-based polishing slurry that contains a ceria particle as the abrasive grain is used.

11. The planarization polishing method according to claim 8, wherein

the surfactant acts on the oxide film that is to be polished.

12. The method for manufacturing a semiconductor device according to claim 8, wherein

polishing is carried out by using first polishing slurry that contains an abrasive grain and a surfactant encapsulated through surface coating until a projection region of the oxide film is planarized, and

subsequent polishing is carried out by using second polishing slurry that contains no surfactant.

13. The method for manufacturing a semiconductor device according to claim 8, wherein

mechanical strength of a coating film of the encapsulated surfactant is equal to or lower than mechanical strength by polishing pressure and shear force.