Method for fabricating trench DMOS transistors and schottky elements
A method uses simplified processes to complete the forming of the trench DMOS transistors and Schottky contacts. In the processes, only four masks, i.e. a trench pattern mask, a contact-hole pattern mask, a P+ contact pattern mask and a conductive-wire pattern mask, are applied to create desired trench DMOS transistors. In addition to the trench DMOS transistors, a Schottky contact is simultaneously formed at a junction between a conductive layer and a doped body region in the trench DMOS transistors without additional photolithography process.
Latest PAN-JIT INTERNATIONAL INC. Patents:
- Manufacturing method of a heat conductive device for a light-emitting diode
- MANUFACTURING METHOD OF A HEAT CONDUCTIVE DEVICE FOR A LIGHT-EMITTING DIODE
- LED lighting device having heat convection and heat conduction effects dissipating assembly therefor
- LED module having heat dissipation structure and optimal light distribution
- LED lamp
1. Field of the Invention
The present invention relates to a method for fabricating trench double diffused metal oxide semiconductor (DMOS) transistors and Schottky elements, and more particularly to a method that uses simplified processes to form DMOS and Schottky elements.
2. Description of the Prior Arts
A double diffused metal oxide semiconductor (DMOS) transistor is typically employed as the power transistor for high voltage power integrated circuits. With a conventional process, six or seven different masks are generally used in the fabrication of the DMOS transistors.
With reference to
With reference to
With reference to
With reference to
With reference to
With reference to
With reference to
With reference to
With reference to
According to the foregoing discussion, the conventional method for fabrication of the DMOS transistors needs a great number of masks as shown in
To overcome the shortcomings, the present invention provides a method for fabricating trench DMOS transistors and Schottky elements to mitigate or obviate the aforementioned problems.
SUMMARY OF THE INVENTIONThe objective of the present invention is to provide a method that fabricates the trench double diffused metal oxide semiconductor (DMOS) transistors and Schottky elements simply by using only four masks to reduce cost in fabricating processes and obtain a superior production yield.
The four masks are respectively used to define trench patterns, contact hole patterns, doped contact patterns and conductive-wire pattern. When forming the trench DMOS transistors, a Schottky contact as a Schottky diode can be simultaneously formed in the DMOS transistors.
Other objectives, advantages and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.
With reference to
With reference to
With reference to
With reference to
With reference to
With reference to
With reference to
With reference to
With reference to
According to the foregoing descriptions, the manufacturing method of the trench DMOS transistors in accordance with the present invention significantly reduces the number of masks to only four, i.e. the trench pattern mask, the contact-hole pattern mask, the P+ contact pattern mask and the conductive-wire pattern mask. Accordingly, the fabricating cost is decreased with the simplified processes.
Even though numerous characteristics and advantages of the present invention have been set forth in the foregoing description, together with details of the structure and features of the invention, the disclosure is illustrative only. Changes may be made in the details, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
Claims
1. A method for fabricating trench double diffused metal oxide semiconductor (DMOS) transistors and Schottky elements, the method comprising:
- forming an epitaxial layer of a first type conductivity on a substrate of the first type conductivity;
- forming a first oxide layer on the epitaxial layer;
- defining trench patterns by using a first mask;
- forming a body region of a second type conductivity within the epitaxial layer;
- forming trenches through the body region based on the defined trench patterns;
- growing a gate oxide layer for covering the body region;
- filling the trenches with gate electrodes;
- forming multiple doped regions of the first type conductivity within the body region between the trenches;
- forming a passivation layer over the first oxide layer and covering the gate electrodes;
- defining contact hole patterns by using a second mask;
- forming contact holes through the passivation layer and the first oxide layer according to the defined contact hole patterns to expose portions of the body region;
- defining contact region patterns by using a third mask;
- forming contact regions of the second type conductivity within the exposed portions of the body region in the contact holes according to the defined contact region patterns;
- defining conductive wire patterns by using a fourth mask; and
- forming a conductive layer on the passivation layer, filling the contact holes and covering exposed portions of the epitaxial layer to form a Schottky contact at a junction between the conductive layer and the epitaxial layer.
2. The method as claimed in claim 1, wherein the first conductivity is an N type conductivity and the second conductivity is a P type conductivity.
3. The method as claimed in claim 1, the step of defining trench patterns further comprising:
- coating a first photoresist layer on the first oxide layer; and
- etching back the first oxide layer according to the defined trench patterns.
4. The method as claimed in claim 2, the step of defining trench patterns further comprising:
- coating a first photoresist layer on the first oxide layer; and
- etching back the first oxide layer according to the defined trench patterns.
5. The method as claimed in claim 2, after the forming of the body region, the method further comprising:
- forming a second oxide layer on the first oxide layer and etching back to form sidewall oxide spacers abutting the first oxide layer.
6. The method as claimed in claim 2, the step of filling the trenches with gate electrodes further comprising:
- depositing a polysilicon layer to fill the trenches and cover the first oxide layer; and
- etching the polysilicon layer on the first oxide layer to retain the polysilicon layer within trenches as the gate electrodes.
7. The method as claimed in claim 1, wherein the first conductivity is a P type conductivity and the second conductivity is an N type conductivity.
8. The method as claimed in claim 7, the step of defining trench patterns further comprising:
- coating a first photoresist layer on the first oxide layer; and
- etching back the first oxide layer according to the defined trench patterns.
9. The method as claimed in claim 7, after the forming of the body region, the method further comprising:
- forming a second oxide layer on the first oxide layer and etching back to form sidewall oxide spacers abutting the first oxide layer.
10. The method as claimed in claim 7, the step of filling the trenches with gate electrodes further comprising:
- depositing a polysilicon layer to fill the trenches and cover the first oxide layer; and
- etching the polysilicon layer on the first oxide layer to retain the polysilicon layer within trenches as the gate electrodes.
Type: Application
Filed: Feb 23, 2007
Publication Date: Aug 28, 2008
Applicant: PAN-JIT INTERNATIONAL INC. (KANG-SHAN TOWN)
Inventors: Chiao-Shun Chuang (Kaohsiung), Hung-Ta Weng (Taipei)
Application Number: 11/709,715
International Classification: H01L 21/8234 (20060101);