Including Diode Patents (Class 438/237)
  • Patent number: 10461125
    Abstract: In an example, a memory array may include a plurality of first dielectric materials and a plurality of stacks, where each respective first dielectric material and each respective stack alternate, and where each respective stack comprises a first conductive material and a storage material. A second conductive material may pass through the plurality of first dielectric materials and the plurality of stacks. Each respective stack may further include a second dielectric material between the first conductive material and the second conductive material.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: October 29, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Agostino Pirovano, Andrea Redaelli, Fabio Pellizzer, Innocenzo Tortorelli
  • Patent number: 10211332
    Abstract: A semiconductor device including a field-effect transistor having source and drain source regions, first and second gate electrodes and a protective diode connected to the transistor. The first gate electrode is formed over a first gate insulating film in a lower part of a trench. The second gate electrode is formed over a second gate insulating film in an upper part of the trench. The first gate electrode includes a first polysilicon film, and the second gate electrode includes a second polysilicon film, wherein an impurity concentration of the first polysilicon film is lower than an impurity concentration of the second polysilicon film.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: February 19, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshito Nakazawa, Yuji Yatsuda
  • Patent number: 9735142
    Abstract: With a microwave FET, an incorporated Schottky junction capacitance or PN junction capacitance is small and such a junction is weak against static electricity. However, with a microwave device, the method of connecting a protecting diode cannot be used since this method increases the parasitic capacitance and causes degradation of the high-frequency characteristics. In order to solve the above problems, a protecting element, having a first n+-type region—insulating region—second n+-type region arrangement is connected in parallel between two terminals of a protected element having a PN junction, Schottky junction, or capacitor. Since discharge can be performed between the first and second n+ regions that are adjacent each other, electrostatic energy that would reach the operating region of an FET can be attenuated without increasing the parasitic capacitance.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: August 15, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Tetsuro Asano, Mikito Sakakibara, Toshikazu Hirai
  • Patent number: 9671363
    Abstract: A chemical sensor is described. The chemical sensor includes a chemically-sensitive field effect transistor including a floating gate conductor having an upper surface. A material defines an opening extending to the upper surface of the floating gate conductor, the material comprising a first dielectric underlying a second dielectric. A conductive element contacts the upper surface of the floating gate conductor and extending a distance along a sidewall of the opening.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: June 6, 2017
    Assignee: Life Technologies Corporation
    Inventors: Keith G. Fife, Jordan Owens, Shifeng Li, James Bustillo
  • Patent number: 9281185
    Abstract: Methods for passivating a nanotube fabric layer within a nanotube switching device to prevent or otherwise limit the encroachment of an adjacent material layer are disclosed. In some embodiments, a sacrificial material is implanted within a porous nanotube fabric layer to fill in the voids within the porous nanotube fabric layer while one or more other material layers are applied adjacent to the nanotube fabric layer. Once the other material layers are in place, the sacrificial material is removed. In other embodiments, a non-sacrificial filler material (selected and deposited in such a way as to not impair the switching function of the nanotube fabric layer) is used to form a barrier layer within a nanotube fabric layer. In other embodiments, individual nanotube elements are combined with and nanoscopic particles to limit the porosity of a nanotube fabric layer.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: March 8, 2016
    Assignee: Nantero Inc.
    Inventors: Thomas Rueckes, H. Montgomery Manning, Rahul Sen
  • Patent number: 9236450
    Abstract: Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body; forming a source; forming an active region contact trench that extends through the source and the body into a drain; forming a Schottky barrier controlling layer in the epitaxial layer in bottom region of the active region contact trench; and disposing a contact electrode within the active region contact trench. The Schottky barrier controlling layer controls Schottky barrier height of a Schottky diode formed by the contact electrode and the drain.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: January 12, 2016
    Assignee: Alpha and Omega Semiconductor Limited
    Inventors: Anup Bhalla, Xiaobin Wang, Ji Pan, Sung-Po Wei
  • Patent number: 9224852
    Abstract: A corner layout for a semiconductor device that maximizes the breakdown voltage is disclosed. The device includes first and second subsets of the striped cell arrays. The ends of each striped cell in the first array is spaced a uniform distance from the nearest termination device structure. In the second subset, the ends of striped cells proximate a corner of the active cell region are configured to maximize breakdown voltage by spacing the ends of each striped cell a non-uniform distance from the nearest termination device structure. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: December 29, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Anup Bhalla
  • Patent number: 9209225
    Abstract: A cell structure of a non-volatile memory is provided. The cell structure includes a first metal layer, a first dielectric layer, a first material layer, a second material layer, a first transition layer, a second metal layer, a second dielectric layer, a third material layer, a fourth material layer, a second transition layer, and a third metal layer. The first dielectric layer has a first via, and the first metal layer is exposed through the first via. The first material layer and the second material layer are reacted with each other to form the first transition layer. The second dielectric layer has a second via, and the second metal layer is exposed through the second via. The third material layer and the fourth material layer are reacted with each other to form the second transition layer.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: December 8, 2015
    Inventor: Chrong-Jung Lin
  • Patent number: 9153570
    Abstract: An electrostatic discharge tolerant device includes a semiconductor body having a first conductivity type, and a pad. A surrounding well having a second conductivity type is laid out in a ring to surround an area for an electrostatic discharge circuit in the semiconductor body. The surrounding well is relatively deep, and in addition to defining the area for the electrostatic discharge circuit, provides the first terminal of a diode formed with the semiconductor body. Within the area surrounded by the surrounding well, a diode coupled to the pad and a transistor coupled to the voltage reference are connected in series and form a parasitic device in the semiconductor body.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: October 6, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Shih-Yu Wang, Chia-Ling Lu, Yan-Yu Chen, Yu-Lien Liu, Tao-Cheng Lu
  • Patent number: 9136833
    Abstract: There is provided a power source connection circuit, when a switch having a low dielectric strength is employed, capable of preventing excessive power consumption when the switch between an input terminal and an output terminal is turned off, and also discharging electric charges accumulated in a gate of the switch. A power source connection circuit includes a MOS switch connected to an output terminal; a step-up circuit for supplying electric charges to a gate of the MOS switch; an electric-charge discharging unit coupled between the gate and a ground terminal; and a comparator for comparing a voltage of the output terminal with a reference voltage, wherein the electric-charge discharging unit includes a rectifier unit coupled between the gate and the ground terminal, and a switch coupled in series with the rectifier unit between the gate and the ground terminal to receive an output signal of the comparator at a gate.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: September 15, 2015
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: Naoto Hayasaka
  • Patent number: 9130163
    Abstract: A method of forming a phase change material memory cell includes forming a number of memory structure regions, wherein the memory structure regions include a bottom electrode material and a sacrificial material, forming a number of insulator regions between the number of memory structure regions, forming a number of openings between the number of insulator regions and forming a contoured surface on the number of insulator regions by removing the sacrificial material and a portion of the number of insulator regions, forming a number of dielectric spacers on the number of insulator regions, forming a contoured opening between the number of insulator regions and exposing the bottom electrode material by removing a portion of the number of dielectric spacers, and forming a phase change material in the opening between the number of insulator regions.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: September 8, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Sanh D. Tang
  • Patent number: 9082896
    Abstract: A pixel of an image sensor, the pixel includes a floating diffusion node to sense photo-generated charge, a reset diode to reset the floating diffusion node in response to a reset signal, and a set diode to set the floating diffusion node.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: July 14, 2015
    Assignee: Intellectual Ventures II LLC
    Inventor: Jaroslav Hynecek
  • Patent number: 9077920
    Abstract: A solid-state image pickup device includes a pixel array section including an effective pixel region, an optical black pixel region, and a pixel region between the effective pixel region and the optical black pixel region; a vertical drive section which performs driving so that signals of pixels of the pixel region disposed at a side of the effective pixel region in a vertical direction are skipped and signals of pixels of the effective pixel region and the optical black pixel region are read; and a horizontal drive section which performs driving so that, from among the pixels selected by the vertical drive section, the signals of the pixels of the pixel region disposed at a side of the effective pixel region in a horizontal direction are skipped and the signals of the pixels of the effective pixel region and the optical black pixel region are read.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: July 7, 2015
    Assignee: Sony Corporation
    Inventors: Ryoji Suzuki, Takayuki Toyama, Koji Mishina, Hiroyuki Tsuchiya
  • Patent number: 9053936
    Abstract: A method for forming a unit layout pattern includes: forming first through third active regions in the unit layout pattern, each of the first through third active regions aligning and extending along a length in a first direction and having a width in a second direction perpendicular to the first direction; forming first and second gate regions on the first and second active regions, the first and second gate regions electrically connected to each other; forming the first active region of a first conductive type within a second conductive type well region; forming the second active region of a second conductive type; and forming the third active region connected with the first and second gate regions to form a junction diode, the third active region being located between the first or the second active region and an end of the length in the first direction of the unit pattern.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: June 9, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soo-Young Kim, Jong-Hak Won
  • Publication number: 20150147855
    Abstract: A semiconductor device includes: first and second n-type wells formed in p-type semiconductor substrate, the second n-type well being deeper than the first n-type well; first and second p-type backgate regions formed in the first and second n-type wells; first and second n-type source regions formed in the first and second p-type backgate regions; first and second n-type drain regions formed in the first and second n-type wells, at positions opposed to the first and second n-type source regions, sandwiching the first and the second p-type backgate regions; and field insulation films formed on the substrate, at positions between the first and second p-type backgate regions and the first and second n-type drain regions; whereby first transistor is formed in the first n-type well, and second transistor is formed in the second n-type well with a higher reverse voltage durability than the first transistor.
    Type: Application
    Filed: February 5, 2015
    Publication date: May 28, 2015
    Inventor: Kazuhiko Takada
  • Publication number: 20150137135
    Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes an upper surface and a channel, a gate electrode disposed over the substrate electrically coupled to the channel, and a Schottky metal layer disposed over the substrate adjacent the gate electrode. The Schottky metal layer includes a Schottky contact electrically coupled to the channel which provides a Schottky junction and at least one alignment mark disposed over the semiconductor substrate. A method for fabricating the semiconductor device includes creating an isolation region that defines an active region along an upper surface of a semiconductor substrate, forming a gate electrode over the semiconductor substrate in the active region, and forming a Schottky metal layer over the semiconductor substrate. Forming the Schottky metal layer includes forming at least one Schottky contact electrically coupled to the channel and providing a Schottky junction, and forming an alignment mark in the isolation region.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 21, 2015
    Inventors: BRUCE M. GREEN, DARRELL G. HILL, KAREN E. MOORE
  • Patent number: 9029235
    Abstract: A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.
    Type: Grant
    Filed: May 26, 2014
    Date of Patent: May 12, 2015
    Assignee: PFC Device Corp.
    Inventors: Mei-Ling Chen, Hung-Hsin Kuo, Kuo-Liang Chao
  • Publication number: 20150115351
    Abstract: An integrated circuit includes a power component including a plurality of first trenches in a cell array and a first conductive material in the first trenches electrically coupled to a gate terminal of the power component, and a diode component including a first diode device trench and a second diode device trench disposed adjacent to each other. A second conductive material in the first and the second diode device trenches is electrically coupled to a source terminal of the diode component. The first trenches, the first diode device trench and the second diode device trench are disposed in a first main surface of a semiconductor substrate. The integrated circuit further includes a diode gate contact including a connection structure between the first and the second diode device trenches. The connection structure is in contact with the second conductive material in the first and the second diode device trenches.
    Type: Application
    Filed: October 30, 2013
    Publication date: April 30, 2015
    Inventor: Britta Wutte
  • Patent number: 9012997
    Abstract: A semiconductor device includes a semiconductor-on-insulator (SOI) substrate having a bulk substrate layer, an active semiconductor layer and a buried insulator layer disposed between the bulk substrate layer and the active semiconductor layer. A trench is formed through the SOI substrate to expose the bulk substrate layer. A doped well is formed in an upper region of the bulk substrate layer adjacent trench. The semiconductor device further includes a first doped region different from the doped well that is formed in the trench.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: April 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tenko Yamashita, Terence B. Hook, Veeraraghavan S. Basker, Chun-Chen Yeh
  • Publication number: 20150084119
    Abstract: A semiconductor device includes a vertical field-effect-transistor (FET) and a bypass diode. The vertical FET device includes a substrate, a drift layer formed over the substrate, a gate contact and a plurality of source contacts located on a first surface of the drift layer opposite the substrate, a drain contact located on a surface of the substrate opposite the drift layer, and a plurality of junction implants, each of the plurality of junction implants laterally separated from one another on the surface of the drift layer opposite the substrate and extending downward toward the substrate. Each of the one or more bypass diodes are formed by placing a Schottky metal contact on the first surface of the drift layer, such that each Schottky metal contact runs between two of the plurality of junction implants.
    Type: Application
    Filed: September 20, 2013
    Publication date: March 26, 2015
    Applicant: Cree, Inc.
    Inventors: Vipindas Pala, Edward Robert Van Brunt, Lin Cheng, John Williams Palmour
  • Publication number: 20150087122
    Abstract: Provided is a semiconductor device that can be manufactured at low cost and that can reduce a reverse leak current, and a manufacturing method thereof. A semiconductor device has: a source region and a drain region having a body region therebetween; a source trench that reaches the body region, penetrating the source region; a body contact region formed at the bottom of the source trench; a source electrode embedded in the source trench; and a gate electrode that faces the body region. The semiconductor device also has: an n-type region for a diode; a diode trench formed reaching the n-type region for a diode; a p+ region for a diode that forms a pn junction with the n-type region for a diode at the bottom of the diode trench; and a schottky electrode that forms a schottky junction with the n-type region for a diode at side walls of the diode trench.
    Type: Application
    Filed: December 4, 2014
    Publication date: March 26, 2015
    Applicant: ROHM CO., LTD.
    Inventor: Kenichi YOSHIMOCHI
  • Publication number: 20150084059
    Abstract: A semiconductor device according to an embodiment includes a first GaN based semiconductor layer of a first conductive type, a second GaN based semiconductor layer of the first conductive type provided above the first GaN based semiconductor layer, a third GaN based semiconductor layer of a second conductive type provided above a part of the second GaN based semiconductor layer, a epitaxially grown fourth GaN based semiconductor layer of the first conductive type provided above the third GaN based semiconductor layer, a gate insulating film provided on the second, third, and fourth GaN based semiconductor layer, a gate electrode provided on the gate insulating film, a first electrode provided on the fourth GaN based semiconductor layer, a second electrode provided at the side of the first GaN based semiconductor layer opposite to the second GaN based semiconductor layer, and a third electrode provided on the second GaN based semiconductor layer.
    Type: Application
    Filed: August 6, 2014
    Publication date: March 26, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Miki YUMOTO, Masahiko Kuraguchi
  • Publication number: 20150084118
    Abstract: A semiconductor device includes a vertical FET device and a Schottky bypass diode. The vertical FET device includes a gate contact, a source contact, and a drain contact. The gate contact and the source contact are separated from the drain contact by at least a drift layer. The Schottky bypass diode is coupled between the source contact and the drain contact and monolithically integrated adjacent to the vertical FET device such that a voltage placed between the source contact and the drain contact is distributed throughout the drift layer by the Schottky bypass diode in such a way that a voltage across each one of a plurality of P-N junctions formed between the source contact and the drain contact within the vertical FET device is prevented from exceeding a barrier voltage of the respective P-N junction.
    Type: Application
    Filed: September 20, 2013
    Publication date: March 26, 2015
    Applicant: Cree, Inc.
    Inventors: Edward Robert Van Brunt, Vipindas Pala, Lin Cheng
  • Patent number: 8975123
    Abstract: Device structures, fabrication methods, and design structures for tunnel field-effect transistors. A drain comprised of a first semiconductor material having a first band gap and a source comprised of a second semiconductor material having a second band gap are formed. A tunnel barrier is formed between the source and the drain. The second semiconductor material exhibits a broken-gap energy band alignment with the first semiconductor material. The tunnel barrier is comprised of a third semiconductor material with a third band gap larger than the first band gap and larger than the second band gap. The third band gap is configured to bend under an external bias to assist in aligning a first energy band of the first semiconductor material with a second energy band of the second semiconductor material.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: March 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Douglas M. Daley, Hung H. Tran, Wayne H. Woods, Ze Zhang
  • Patent number: 8969150
    Abstract: A trench gate type MISFET and a diode are formed in a semiconductor substrate. First and second trenches are formed in the semiconductor substrate. A gate electrode is formed in the first trench through a gate insulating film. A dummy gate electrode is formed in the second trench through a dummy gate insulating film. A cathode n+-type semiconductor region and an anode p-type semiconductor region are formed in the semiconductor substrate and the second trench is formed so as to surround the n+-type semiconductor region in a planar view. A part of the anode p-type semiconductor region is formed directly below the n+-type semiconductor region, so that a PN junction is formed between the part of the anode p-type semiconductor region and the n+-type semiconductor region. Thereby a diode is formed. The dummy gate electrode is electrically coupled to one of an anode and a cathode.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: March 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroaki Katou, Taro Moriya, Hiroyoshi Kudou, Satoshi Uchiya
  • Publication number: 20150035006
    Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.
    Type: Application
    Filed: October 17, 2014
    Publication date: February 5, 2015
    Inventor: Kenichi YOSHIMOCHI
  • Patent number: 8947936
    Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: February 3, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun-Hsiung Hung, Shin-Jang Shen, Hang-Ting Lue
  • Patent number: 8946018
    Abstract: Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second semiconductor material is epitaxially grown over the first semiconductor material. The second semiconductor material is patterned to form circuit components, and the heavily-doped region is patterned to form spaced-apart buried lines electrically coupling pluralities of the circuit components to one another. At least some of the patterning of the heavily-doped region occurs simultaneously with at least some of the patterning of the second semiconductor material.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Jaydip Guha, Shyam Surthi
  • Publication number: 20150021680
    Abstract: A FET incorporating a Schottky diode has a structure allowing the ratio of an area in which the Schottky diode is formed and an area in which the FET is formed to be freely adjusted. A trench extending for a long distance is utilized. Schottky electrodes are interposed at positions appearing intermittently in the longitudinal direction of the trench. By taking advantage of the growth rate of a thermal oxide film formed on SiC being slower, and the growth rate of a thermal oxide film formed on polysilicon being faster, a structure can be obtained in which insulating film is formed between gate electrodes and Schottky electrodes, between the gate electrodes and a source region, between the gate electrodes and a body region, and between the gate electrodes and a drain region, and in which insulating film is not formed between the Schottky electrodes and the drain region.
    Type: Application
    Filed: June 9, 2014
    Publication date: January 22, 2015
    Inventors: Yukihiko WATANABE, Sachiko AOI, Hidefumi TAKAYA, Atsuya AKIBA
  • Publication number: 20150014769
    Abstract: A high-voltage LDMOS device with voltage linearizing field plates and methods of manufacture are disclosed. The method includes forming a continuous gate structure over a deep well region and a body of a substrate. The method further includes forming oppositely doped, alternating segments in the continuous gate structure. The method further includes forming a contact in electrical connection with a tip of the continuous gate structure and a drain region formed in the substrate. The method further includes forming metal regions in direct electrical contact with segments of at least one species of the oppositely doped, alternating segments.
    Type: Application
    Filed: July 11, 2013
    Publication date: January 15, 2015
    Inventors: John J. ELLIS-MONAGHAN, Theodore J. LETAVIC, Santosh SHARMA, Yun SHI, Michael J. ZIERAK
  • Patent number: 8928072
    Abstract: Provided is a semiconductor device that can be manufactured at low cost and that can reduce a reverse leak current, and a manufacturing method thereof. A semiconductor device has: a source region and a drain region having a body region therebetween; a source trench that reaches the body region, penetrating the source region; a body contact region formed at the bottom of the source trench; a source electrode embedded in the source trench; and a gate electrode that faces the body region. The semiconductor device also has: an n-type region for a diode; a diode trench formed reaching the n-type region for a diode; a p+ region for a diode that forms a pn junction with the n-type region for a diode at the bottom of the diode trench; and a schottky electrode that forms a schottky junction with the n-type region for a diode at side walls of the diode trench.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: January 6, 2015
    Assignee: Rohm Co., Ltd.
    Inventor: Kenichi Yoshimochi
  • Publication number: 20150001579
    Abstract: A capacitive component region is formed below a temperature detecting diode or below a protective diode. In addition, the capacitive component region is formed below an anode metal wiring line connecting the temperature detecting diode and an anode electrode pad and below a cathode metal wiring line connecting the temperature detecting diode and a cathode electrode pad. The capacitive component region is an insulating film interposed between polysilicon layers. Specifically, a first insulating film, a polysilicon conductive layer, and a second insulating film are sequentially formed on a first main surface of a semiconductor substrate, and the temperature detecting diode, the protective diode, the anode metal wiring line, or the cathode metal wiring line is formed on the upper surface of the second insulating film. Therefore, it is possible to improve the static electricity resistance of the temperature detecting diode or the protective diode.
    Type: Application
    Filed: September 12, 2014
    Publication date: January 1, 2015
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi NISHIMURA
  • Publication number: 20140374824
    Abstract: Aspects of the present disclosure describe a Schottky structure with two trenches formed in a semiconductor material. The trenches are spaced apart from each other by a mesa. Each trench may have first and second conductive portions lining the first and second sidewalls. The first and second portions of conductive material are electrically isolated from each other in each trench. The Schottky contact may be formed at any location between the outermost conductive portions. The Schottky structure may be formed in the active area or the termination area of a device die. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Application
    Filed: June 25, 2013
    Publication date: December 25, 2014
    Inventors: Daniel Calafut, Yeeheng Lee
  • Publication number: 20140374766
    Abstract: A semiconductor device includes a bidirectional GaN FET formed on a non-insulating substrate. The semiconductor device further includes a first electrical clamp connected between the substrate and a first source/drain node of the bidirectional GaN FET, and a second electrical clamp connected between the substrate and a second source/drain node of the bidirectional GaN FET. The first clamp and the second clamp are configured to bias the substrate at a lower voltage level of an applied bias to the first source/drain node and an applied bias to the second source/drain node, within an offset voltage of the relevant clamp.
    Type: Application
    Filed: June 20, 2013
    Publication date: December 25, 2014
    Inventors: Sandeep R. BAHL, Matthew SENESKY, Naveen TIPIRNENI, David I. ANDERSON, Sameer PENDHARKAR
  • Patent number: 8907393
    Abstract: A semiconductor device including buried bit lines formed of a metal silicide and silicidation preventing regions formed in a substrate under trenches that separate the buried bit lines.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: December 9, 2014
    Assignee: SK Hynix Inc.
    Inventor: Ju-Hyun Myung
  • Patent number: 8907414
    Abstract: Aspects of the present disclosure describe high voltage fast recovery trench diodes and methods for make the same. The device may have trenches that extend at least through a top P-layer and an N-barrier layer. A conductive material may be disposed in the trenches with a dielectric material lining the trenches between the conductive material and sidewalls of the trenches. A highly doped P-pocket may be formed in an upper portion of the top P-layer between the trenches. A floating N-pocket may be formed directly underneath the P-pocket. The floating N-pocket may be as wide as or wider than the P-pocket. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: December 9, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Jun Hu, Karthik Padmanabhan, Madhur Bobde, Hamza Yilmaz
  • Publication number: 20140357030
    Abstract: Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body; forming a source; forming an active region contact trench that extends through the source and the body into a drain; forming a Schottky barrier controlling layer in the epitaxial layer in bottom region of the active region contact trench; and disposing a contact electrode within the active region contact trench. The Schottky barrier controlling layer controls Schottky barrier height of a Schottky diode formed by the contact electrode and the drain.
    Type: Application
    Filed: June 10, 2014
    Publication date: December 4, 2014
    Inventors: Anup Bhalla, Xiaobin Wang, Ji Pan, Sung-Po Wei
  • Publication number: 20140346594
    Abstract: A semiconductor device with an embedded schottky diode and a manufacturing method thereof are provided. A semiconductor device having a schottky diode include: an epilayer of a first conductivity type, a body layer of a second conductivity type, and a source layer of the first conductivity type arranged in that order; a gate trench that extends from the source layer to a part of the epilayer; a body trench formed a predetermined distance from the gate trench and extends from the source layer to a part of the epilayer; and a guard ring of the second conductivity type that contacts an outer wall of the body trench and formed in the epilayer.
    Type: Application
    Filed: August 27, 2013
    Publication date: November 27, 2014
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventor: Francois HEBERT
  • Publication number: 20140342515
    Abstract: An ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. A method of forming an ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device.
    Type: Application
    Filed: August 7, 2014
    Publication date: November 20, 2014
    Inventors: Ponnarith POK, Kyle SCHULMEYER, Roger A. CLINE, Charvaka DUVVURY
  • Publication number: 20140342510
    Abstract: Aspects of the disclosure provide a dual electrostatic discharge (ESD) protection device in fin field effect transistor (FinFET) process technology and methods of forming the same. In one embodiment, the dual ESD protection device includes: a bulk silicon substrate; a shallow trench isolation (STI) region formed over the bulk silicon substrate; a first ESD device positioned above the STI region; and a second ESD device positioned below the STI region, wherein the first ESD device conducts current above the STI region and the second ESD device conducts current below the STI region.
    Type: Application
    Filed: August 4, 2014
    Publication date: November 20, 2014
    Inventors: Robert J. Gauthier, JR., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher Stephen Putnam
  • Patent number: 8890279
    Abstract: A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: November 18, 2014
    Assignee: PFC Device Corp.
    Inventors: Kou-Liang Chao, Mei-Ling Chen, Tse-Chuan Su, Hung-Hsin Kuo
  • Publication number: 20140335670
    Abstract: A semiconductor device comprises a first substrate portion and a second substrate portion disposed a distance away from the first substrate portion. The first substrate portion includes a first active semiconductor layer defining at least one semiconductor fin and a first polycrystalline layer formed directly on the fin. The first polycrystalline layer is patterned to define at least one semiconductor gate. The second substrate portion includes a doped region interposed between a second active semiconductor region and an oxide layer. The oxide layer protects the second active semiconductor region and the doped region. The doped region includes a first doped area and a second doped area separated by the first doped region to define a depletion region.
    Type: Application
    Filed: June 4, 2013
    Publication date: November 13, 2014
    Inventors: Veeraraghavan S. Basker, Tenko Yamashita
  • Patent number: 8883589
    Abstract: A method of forming a memory cell is provided, the method including forming a diode including a first region having a first conductivity type, counter-doping the diode to change the first region to a second conductivity type, and forming a memory element coupled in series with the diode. Other aspects are also provided.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: November 11, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Xiying Costa, Abhijit Bandyopadhyay, Kun Hou, Brian Le, Yung-Tin Chen
  • Patent number: 8883590
    Abstract: A phase change memory apparatus is provided that includes a first electrode that is longer than it is wide, the first electrode having a trench formed on an active region of a semiconductor substrate, a second electrode formed in a bottom portion of the trench, and a bottom electrode contact formed on the second electrode.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: November 11, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jang Uk Lee
  • Patent number: 8865540
    Abstract: A method for forming a Schottky diode including forming first and second trenches in a semiconductor layer, forming a thin dielectric layer lining sidewalls of the first and second trenches; forming a trench conductor layer in the first and second trenches where the trench conductor layer fills a portion of each of the first and second trenches and being the only one trench conductor layer in the first and second trenches; forming a first dielectric layer in the first and second trenches to fill the remaining portions of the first and second trenches; and forming a Schottky metal layer on a top surface of the lightly doped semiconductor layer between the first trench and the second trench to form a Schottky junction. The Schottky diode is formed with the Schottky metal layer as the anode and the lightly doped semiconductor layer between the first and second trenches as the cathode.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: October 21, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Daniel Calafut, Yi Su, Jongoh Kim, Hong Chang, Hamza Yilmaz, Daniel S. Ng
  • Patent number: 8865541
    Abstract: An integrated circuit contains a voltage protection structure having a diode isolated DENMOS transistor with a guard element proximate to the diode and the DENMOS transistor. The guard element includes an active area coupled to ground. The diode anode is connected to an I/O pad. The diode cathode is connected to the DENMOS drain. The DENMOS source is grounded. A process of forming the integrated circuit is also disclosed.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: October 21, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Farzan Farbiz, Akram A. Salman
  • Publication number: 20140308784
    Abstract: A three-dimensional (3D) gate driver integrated circuit includes a high-side integrated circuit stacked on a low-side integrated circuit where the high-side integrated circuit and the low-side integrated circuit are interconnected using through-silicon vias (TSV). As thus formed, the high-side integrated circuit and the low-side integrated circuit can be formed without termination regions and without buried layers. The 3D gate driver integrated circuit improves ease of high voltage integration and improves the ruggedness and reliability of the gate driver integrated circuit.
    Type: Application
    Filed: June 24, 2014
    Publication date: October 16, 2014
    Inventor: Shekar Mallikarjunaswamy
  • Publication number: 20140264586
    Abstract: A laterally diffused metal oxide semiconductor (LDMOS) device, and a method of manufacturing the same are provided. The LDMOS device can include a drain region of a bootstrap field effect transistor (FET), a source region of the bootstrap FET, a drift region formed between the drain region and the source region, and a gate formed at one side of the source region and on the drift region.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: DONGBU HITEK CO., LTD.
    Inventor: Nam Chil MOON
  • Patent number: 8835934
    Abstract: A semiconductor device includes a first conduction type semiconductor substrate, a first conduction type semiconductor deposition layer, a trench, second conduction type wells, a JFET region, a first conduction type first source region, a first source region, a trench-type source electrode, a gate insulator film, a gate electrode, and a drain electrode. The trench is formed substantially perpendicularly to the semiconductor deposition layer so that the semiconductor deposition layer exposes to a bottom of the trench. The second conduction type second source region are formed in the first conduction type first source region. The trench-type source electrode is in contact with the first source region, the second source region, and the first conduction type semiconductor deposition layer to configure a Schottky junction.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaishia Toshiba
    Inventor: Makoto Mizukami
  • Patent number: 8829650
    Abstract: A zener diode in a SiGe BiCMOS process is disclosed. An N-type region of the zener diode is formed in an active region and surrounded by an N-deep well. A pseudo buried layer is formed under each of the shallow trench field oxide regions on a corresponding side of the active region, and the N-type region is connected to the pseudo buried layers via the N-deep well. The N-type region has its electrode picked up by deep hole contacts. A P-type region of the zener diode is formed of a P-type ion implanted region in the active region. The P-type region is situated above and in contact with the N-type region, and has a doping concentration greater than that of the N-type region. The P-type region has its electrode picked up by metal contact. A method of fabricating zener diode in a SiGe BiCMOS process is also disclosed.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: September 9, 2014
    Assignee: Shanghai Hua Hong Nec Electronics Co., Ltd.
    Inventors: Donghua Liu, Jun Hu, Wenting Duan, Wensheng Qian, Jing Shi