Mis Technology (epo) Patents (Class 257/E21.616)

  • Patent number: 10468410
    Abstract: In some embodiments, the present disclosure, relates to an integrated chip. The integrated chip has an isolation structure arranged within a substrate. The isolation structure has interior surfaces defining one or more divots recessed below an uppermost surface of the isolation structure and sidewalls defining an opening exposing the substrate. A source region is disposed within the opening. A drain region is also disposed within the opening and is separated from the source region by a channel region along a first direction. A gate structure extends over the channel region. The gate structure includes a first gate electrode region having a first composition of one or more materials and a second gate electrode region disposed over the one or more divots and having a second composition of one or more materials different than the first composition of one or more materials.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: November 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Han Lin, Te-Hsin Chiu, Wei Cheng Wu
  • Patent number: 9496144
    Abstract: A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; depositing a first cap layer comprising an oxide over the dielectric stack; forming a second cap layer comprising a nitride over the first cap layer; patterning the first and second cap layers and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to form a blocking oxide over the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: November 15, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Hui-Mei Shih
  • Patent number: 8981530
    Abstract: A semiconductor device includes a first NMOS device with a first threshold voltage and a second NMOS device with a second threshold voltage. The first NMOS device includes a first gate structure over a semiconductor substrate, first source/drain (S/D) regions in the semiconductor substrate and adjacent to opposite edges of the first gate structure. The first S/D regions are free of dislocation. The second NMOS device includes a second gate structure over the semiconductor substrate, second S/D regions in the semiconductor substrate and adjacent to opposite edges of the second gate structure, and a dislocation in the second S/D regions.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: March 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Ming Zhu
  • Patent number: 8975133
    Abstract: One illustrative integrated circuit product disclosed herein includes a metal-1 metallization layer positioned above a semiconducting substrate, a capacitor positioned between a surface of the substrate and a bottom of the metal-1 metallization layer, wherein the capacitor includes a plurality of conductive plates that are oriented in a direction that is substantially normal relative to the surface of the substrate, and at least one region of insulating material positioned between the plurality of conductive plates.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: March 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kok Yong Yiang, Patrick R. Justison
  • Patent number: 8975712
    Abstract: One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively. A device disclosed herein includes a gate structure, source/drain regions, first and second unitary conductive source/drain contact structures, each of which contacts one of the source/drain regions, and first and second conductive vias that contact the first and second unitary conductive source/drain contact structures, respectively.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: March 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, Juhan Kim, Yunfei Deng, Suresh Venkatesan
  • Patent number: 8921181
    Abstract: Methods for forming an electronic device having a fluorine-stabilized semiconductor substrate surface are disclosed. In an exemplary embodiment, a layer of a high-? dielectric material is formed together with a layer containing fluorine on a semiconductor substrate. Subsequent annealing causes the fluorine to migrate to the surface of the semiconductor (for example, silicon, germanium, or silicon-germanium). A thin interlayer of a semiconductor oxide may also be present at the semiconductor surface. The fluorine-containing layer can comprise F-containing WSix formed by ALD from WF6 and SiH4 precursor gases. A precise amount of F can be provided, sufficient to bind to substantially all of the dangling semiconductor atoms at the surface of the semiconductor substrate and sufficient to displace substantially all of the hydrogen atoms present at the surface of the semiconductor substrate.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: December 30, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Dipankar Pramanik
  • Patent number: 8865540
    Abstract: A method for forming a Schottky diode including forming first and second trenches in a semiconductor layer, forming a thin dielectric layer lining sidewalls of the first and second trenches; forming a trench conductor layer in the first and second trenches where the trench conductor layer fills a portion of each of the first and second trenches and being the only one trench conductor layer in the first and second trenches; forming a first dielectric layer in the first and second trenches to fill the remaining portions of the first and second trenches; and forming a Schottky metal layer on a top surface of the lightly doped semiconductor layer between the first trench and the second trench to form a Schottky junction. The Schottky diode is formed with the Schottky metal layer as the anode and the lightly doped semiconductor layer between the first and second trenches as the cathode.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: October 21, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Daniel Calafut, Yi Su, Jongoh Kim, Hong Chang, Hamza Yilmaz, Daniel S. Ng
  • Patent number: 8841723
    Abstract: The present invention discloses an LDMOS device having an increased punch-through voltage and a method for making same. The LDMOS device includes: a substrate; a well of a first conductive type formed in the substrate; an isolation region formed in the substrate; a body region of a second conductive type in the well; a source in the body region; a drain in the well; a gate structure on the substrate; and a first conductive type dopant region beneath the body region, for increasing a punch-through voltage.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: September 23, 2014
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Tsung-Yi Huang, Huan-Ping Chu, Ching-Yao Yang, Hung-Der Su
  • Patent number: 8765549
    Abstract: Capacitor designs for substrates, such as interposers, and methods of manufacture thereof are disclosed. In an embodiment, a capacitor is formed between a through via and a lower level metallization layer. The capacitor may be, for example, a planar capacitor formed on the substrate or on a dielectric layer formed over the substrate.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: July 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hua Chang, Shin-Puu Jeng, Der-Chyang Yeh, Shang-Yun Hou, Wen-Chih Chiou
  • Patent number: 8766348
    Abstract: A non-volatile semiconductor memory device comprises a semiconductor substrate and a plurality of gate structures formed on a cell region of the semiconductor substrate. The plurality of gate structures include a first select-gate and a second select-gate disposed on the cell region, the first select-gate and the second select-gate spaced apart from each other. A plurality of cell gate structures are disposed between the first select-gate and the second select-gate. The first select-gate and an adjacent cell gate structure have no air gap defined therebetween. At least a pair of adjacent cell gate structures have an air gap defined therebetween.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: July 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Kyung Kim, Woosung Choi
  • Patent number: 8753941
    Abstract: An integrated circuit with a LV transistor and a high performance asymmetric transistor. A power amplifier integrated circuit with a core transistor and a high performance asymmetric transistor. A method of forming an integrated circuit with a core transistor and a high performance asymmetric transistor. A method of forming a power amplifier integrated circuit with an nmos core transistor and an nmos high performance asymmetric transistor, a resistor, and an inductor.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: June 17, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Kamel Benaissa, Vijay K. Reddy, Samuel Martin, T Krishnaswamy
  • Patent number: 8697523
    Abstract: A method of fabricating a FINFET includes the following steps. A plurality of fins is patterned in a wafer. A dummy gate is formed covering a portion of the fins which serves as a channel region. Spacers are formed on opposite sides of the dummy gate. The dummy gate is removed thus forming a trench between the spacers that exposes the fins in the channel region. A nitride material is deposited into the trench so as to cover a top and sidewalls of each of the fins in the channel region. The wafer is annealed to induce strain in the nitride material thus forming a stressed nitride film that covers and induces strain in the top and the sidewalls of each of the fins in the channel region of the device. The stressed nitride film is removed. A replacement gate is formed covering the fins in the channel region.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: April 15, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ming Cai, Dechao Guo, Chun-Chen Yeh
  • Patent number: 8674458
    Abstract: When forming sophisticated semiconductor devices including transistors with sophisticated high-k metal gate electrode structures and a strain-inducing semiconductor alloy, transistor uniformity and performance may be enhanced by providing superior growth conditions during the selective epitaxial growth process. To this end, a semiconductor material may be preserved at the isolation regions in order to avoid the formation of pronounced shoulders. Furthermore, in some illustrative embodiments, additional mechanisms are implemented in order to avoid undue material loss, for instance upon removing a dielectric cap material and the like.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: March 18, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan-Detlef Kronholz, Rohit Pal, Gunda Beernink
  • Publication number: 20140070328
    Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. Two or more layers can be formed on a silicon substrate, wherein one or more of the layers are used for controlling an isolation recess. A first layer can comprise a first material and a second layer can comprise a second material.
    Type: Application
    Filed: September 12, 2012
    Publication date: March 13, 2014
    Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventors: Masakazu Goto, Akira Hokazono
  • Patent number: 8664716
    Abstract: In a lateral-type power MOSFET, high breakdown voltage is achieved with suppressing to increase a cell pitch, and a feedback capacity and an ON resistance are decreased. An n? type silicon region having a high resistance to be a region of maintaining a breakdown voltage is vertically provided with respect to a main surface of an n+ type silicon substrate, and the n? type silicon region having the high resistance is connected to the n+ type silicon substrate. Also, a conductive substance is filled through an insulating substance inside a trench formed to reach the n+ type silicon substrate from the main surface of the n+ type silicon substrate so as to contact with the n? type silicon region having the high resistance, and the conductive substance is electrically connected to a source electrode.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: March 4, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Takayuki Hashimoto, Takashi Hirao, Noboru Akiyama
  • Patent number: 8653601
    Abstract: This invention provides a current control semiconductor element in which dependence of a sense ratio on a temperature distribution is eliminated and the accuracy of current detection using a sense MOSFET can be improved, and to provide a control device using the current control semiconductor element. The current control semiconductor element 1 includes a main MOSFET 7 that drives a current and a sense MOSFET 8 that is connected to the main MOSFET in parallel and detects a current shunted from a current of the main MOSFET. The main MOSFET is formed using a multi-finger MOSFET that has a plurality of channels and is arranged in a row. When a distance between the center of the multi-finger MOSFET 7 and a channel located farthest from the center of the multi-finger MOSFET 7 is indicated by L, a channel that is located closest to a position distant by a distance of (L/(?3)) from the center of the multi-finger MOSFET is used as a channel for the sense MOSFET 8.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: February 18, 2014
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Teppei Hirotsu, Nobuyasu Kanekawa, Itaru Tanabe
  • Publication number: 20140042510
    Abstract: One illustrative integrated circuit product disclosed herein includes a metal-1 metallization layer positioned above a semiconducting substrate, a capacitor positioned between a surface of the substrate and a bottom of the metal-1 metallization layer, wherein the capacitor includes a plurality of conductive plates that are oriented in a direction that is substantially normal relative to the surface of the substrate, and at least one region of insulating material positioned between the plurality of conductive plates.
    Type: Application
    Filed: August 7, 2012
    Publication date: February 13, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Kok Yong Yiang, Patrick R. Justison
  • Patent number: 8643071
    Abstract: A MOSFET device includes one or more active device structures and one or more dummy structures formed from semiconductor drift region and body regions. The dummy structures are electrically connected in parallel to the active device structures. Each dummy structure includes an electrically insulated snubber electrode formed proximate the body region and the drift region, an insulator portion formed over the snubber electrode and a top surface of the body region, and one or more electrical connections between the snubber electrode and portions of the body region and a source electrode. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: February 4, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Ji Pan, Daniel Ng, Anup Bhalla
  • Publication number: 20140021560
    Abstract: Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a transistor having a gate, a source, and a drain. The source and the drain are formed in a doped substrate and are separated by a drift region of the substrate. The gate is formed over the drift region and between the source and the drain. The transistor is configured to handle high voltage conditions that are at least a few hundred volts. The high voltage semiconductor device includes a dielectric structure formed between the source and the drain of the transistor. The dielectric structure protrudes into and out of the substrate. Different parts of the dielectric structure have uneven thicknesses. The high voltage semiconductor device includes a resistor formed over the dielectric structure. The resistor has a plurality of winding segments that are substantially evenly spaced apart.
    Type: Application
    Filed: July 17, 2012
    Publication date: January 23, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Ker Hsiao Huo, Jen-Hao Yeh, Chun-Wei Hsu
  • Patent number: 8633549
    Abstract: A semiconductor device comprises a metal gate electrode, a passive device and a hard mask layer. The passive device has a poly-silicon element layer. The hard mask layer is disposed on the metal gate electrode and the passive electrode and has a first opening and a second opening substantially coplanar with each other, wherein the metal gate electrode and the poly-silicon element layer are respectively exposed via the first opening and the second opening; and there is a distance between the first opening and the metal gate electrode substantially less than the distance between the second opening and the poly-silicon element layer.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: January 21, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chieh-Te Chen, Shih-Fang Tzou, Jiunn-Hsiung Liao, Yi-Po Lin
  • Publication number: 20140001526
    Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. A silicide-block film comprised of a layer of silicon dioxide underlying a top layer of silicon nitride blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit, such as polysilicon-to-metal capacitors, are silicide-clad. Following silicidation, a capacitor dielectric is deposited over the remaining polysilicon structures, followed by formation of an upper metal plate.
    Type: Application
    Filed: June 27, 2012
    Publication date: January 2, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kaiping Liu, Amitava Chatterjee, Imran Mahmood Khan
  • Publication number: 20140001562
    Abstract: An integrated circuit is provided. The integrated circuit includes a substrate, a first FinFET device supported by the substrate, the first FinFET device having a first fin with a non-tiered fin profile, and a second FinFET supported by the substrate, the second FinFET having a second fin with a tiered fin profile.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jhon-Jhy Liaw
  • Publication number: 20130341724
    Abstract: A semiconductor device has a FinFET with at least two independently controllable FETs on a single fin. The fin may have a body area with a width between two vertical sides, each side has a single FET. The fin also may have a top fin area that is wider than the body area and is electrically independent from the two FETs. The top fin area may be capable of receiving a body contact structure which may be connected to an electrical conductor as to regulate the voltage in the body area of the fin.
    Type: Application
    Filed: June 25, 2012
    Publication date: December 26, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, Gregory J. Uhlmann, Kelly L. Williams
  • Publication number: 20130313647
    Abstract: A method of forming a semiconductor structure on a substrate is provided. The method may include preparing a continuous active layer on a region of the substrate and depositing a first raised epitaxial layer on a first region of the continuous active layer. A second raised epitaxial layer is also deposited on a second region of the continuous active layer such that the first raised epitaxial layer is in close proximity to the second raised epitaxial layer. A mask may be used to etch a trench structure into the continuous active layer at both the first and the second raised epitaxial layer, whereby the etched trench structure is filled with isolation material for electrically isolating the first raised epitaxial layer from the second raised epitaxial layer.
    Type: Application
    Filed: May 23, 2012
    Publication date: November 28, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael Vincent Aquilino, Byeong Yeol Kim, Ying Li, Carl John Radens
  • Patent number: 8587224
    Abstract: Provided are a variable field effect transistor (FET) designed to suppress a reduction of current between a source and a drain due to heat while decreasing a temperature of the FET, and an electrical and electronic apparatus including the variable gate FET. The variable gate FET includes a FET and a gate control device that is attached to a surface or a heat-generating portion of the FET and is connected to a gate terminal of the FET so as to vary a voltage of the gate terminal. A channel current between the source and drain is controlled by the gate control device that varies the voltage of the gate terminal when the temperature of the FET increases above a predetermined temperature.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: November 19, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hyun-Tak Kim, Bongjun Kim
  • Patent number: 8580652
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate having first and second main surfaces, and a through hole passing through between the first and second main surfaces, a pad on the first main surface, a through electrode in the through hole, and a connection structure including a connection portion to directly connect the pad and the through electrode, and another connection portion to indirectly connect the pad and the through electrode. The method includes forming an isolation region in the first main surface, the isolation region being in a region where the through electrode is to be formed and being in a region other than the region where the through hole is to be formed, forming the pad, and forming the through hole by processing the substrate to expose a part of the pad.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: November 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Kawasaki, Kenichiro Hagiwara, Ikuko Inoue, Kazutaka Akiyama, Itsuko Sakai, Mie Matsuo, Masahiro Sekiguchi, Yoshiteru Koseki, Hiroki Neko, Koushi Tozuka, Kazuhiko Nakadate, Takuto Inoue
  • Patent number: 8580632
    Abstract: To provide a semiconductor device and a method of manufacturing the same capable of suppressing, when a plurality of MIS transistors having different absolute values of threshold voltage is used, the reduction of the drive current of a MIS transistor having a greater absolute value of threshold voltage. The threshold voltage of a second nMIS transistor is greater than the threshold voltage of a first nMIS transistor and the sum of the concentration of lanthanum atom and the concentration of magnesium atom in a second nMIS high-k film included in the second nMIS transistor is lower than the sum of the concentration of lanthanum atom and the concentration of magnesium atom in a first nMIS high-k film included in the first nMIS transistor.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: November 12, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuhiro Onishi, Kazuhiro Tsukamoto
  • Patent number: 8574982
    Abstract: A method and circuit for implementing an embedded dynamic random access memory (eDRAM), and a design structure on which the subject circuit resides are provided. The embedded dynamic random access memory (eDRAM) circuit includes a stacked field effect transistor (FET) and capacitor. The capacitor is fabricated directly on top of the FET to build the eDRAM.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: November 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Karl Robert Erickson, David Paul Paulsen, John Edward Sheets, II, Kelly L. Williams
  • Publication number: 20130277758
    Abstract: A method of fabricating a FET device is provided that includes the following steps. A wafer is provided. At least one active area is formed in the wafer. A plurality of dummy gates is formed over the active area. Spaces between the dummy gates are filled with a dielectric gap fill material such that one or more keyholes are formed in the dielectric gap fill material between the dummy gates. The dummy gates are removed to reveal a plurality of gate canyons in the dielectric gap fill material. A mask is formed that divides at least one of the gate canyons, blocks off one or more of the keyholes and leaves one or more of the keyholes un-blocked. At least one gate stack material is deposited onto the wafer filling the gate canyons and the un-blocked keyholes. A FET device is also provided.
    Type: Application
    Filed: April 19, 2012
    Publication date: October 24, 2013
    Applicant: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight
  • Publication number: 20130264653
    Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device including an n-type field effect transistor (NFET) and an p-type field effect transistor (PFET) having fully silicided gates electrode in which an improved dual stress buried insulator is employed to incorporate and advantageous mechanical stress into the device channel of the NFET and PFET. The method can be imposed on a bulk substrate or extremely thin silicon on insulator (ETSOI) substrate. The device includes a semiconductor substrate, a plurality of shallow trench isolations structures formed in the ETSOI layer, NFET having a source and drain region and a gate formation, a PFET having a source and drain region, and a gate formation, an insulator layer, including a stressed oxide or nitride, deposited inside the substrate of the NFET, and a second insulator layer, including either an stressed oxide or nitride, deposited inside the substrate of the PFET.
    Type: Application
    Filed: April 10, 2012
    Publication date: October 10, 2013
    Applicant: International Business Machines Corporation
    Inventors: Ming Cai, Dechao Guo, Liyang Song, Chun-Chen Yeh
  • Publication number: 20130228866
    Abstract: Semiconductor devices and manufacturing and design methods thereof are disclosed. In one embodiment, a semiconductor device includes an active FinFET disposed over a workpiece comprising a first semiconductive material, the active FinFET comprising a first fin. An electrically inactive FinFET structure is disposed over the workpiece proximate the active FinFET, the electrically inactive FinFET comprising a second fin. A second semiconductive material is disposed between the first fin and the second fin.
    Type: Application
    Filed: March 1, 2012
    Publication date: September 5, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung Ying Lee, Wen-Huie Guo, Chih-Hao Chang, Shou-Zen Chang
  • Publication number: 20130222950
    Abstract: A device is presented. The device includes a first circuit coupled to first and second power rails of the device. The first circuit is subject to a latch up event in the presence of a latch up condition. The latch up event includes a low resistance path created between the first and second power rails. The device also includes a latch up sensing (LUS) circuit coupled to the first circuit. The LUS circuit is configured to receive a LUS input signal from the first circuit and generates a LUS output signal to the first circuit. When the input signal is an active latch up signal which indicates the presence of a latch up condition, the LUS circuit generates an active LUS output signal which creates a break in the low resistance path to terminate the latch up event.
    Type: Application
    Filed: February 28, 2012
    Publication date: August 29, 2013
    Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Da-Wei LAI, Mahadeva Iyer NATARAJAN
  • Patent number: 8513058
    Abstract: a method for producing a semiconductor device provided in such a manner that a first layer and a second layer are laminated to ensure that their TSVs are arranged in almost a straight line, including: first layer production steps including steps of preparing a substrate, forming a transistor of an input/output circuit on an upper surface of the substrate, forming an insulation layer so as to cover the transistor, and forming a TSV in the insulation layer; second layer production steps including steps of preparing a substrate, forming a transistor of a logic circuit on an upper surface of the substrate, forming an insulation layer so as to cover the transistor, and forming a TSV in the insulation layer; a connection step of connecting surfaces of the first layer and the second layer on a side opposite to substrates of the first layer and the second layer to ensure that the TSV of the first layer and the TSV of the second layer are arranged in almost a straight line; and a step of removing the substrate of the
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: August 20, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Iwamatsu, Yuichi Hirano
  • Publication number: 20130210201
    Abstract: A method for manufacturing an active array substrate is provided herein. The active array substrate can be manufactured by using only two photolithography process steps. The photolithography process step using a first photomask may be provided for forming a drain electrode, a source electrode, a data line and/or a data line connecting pad and a patterned transparent conductive layer, etc. The photolithography process step using a second photomask may be utilized for forming a gate electrode, a gate line, a gate insulating layer, a channel layer and/or a gate line connecting pad, and so forth.
    Type: Application
    Filed: September 14, 2012
    Publication date: August 15, 2013
    Applicant: E INK HOLDINGS INC.
    Inventors: Wen-Chung TANG, Fang-An SHU, Yao-Chou TSAI, Ted-Hong SHINN
  • Patent number: 8507994
    Abstract: In a memory cell including CMOS inverters, an increase in an area of the memory cell caused by restrictions on a gate wiring due to a leakage current and restrictions due to design rules is suppressed. A first wiring and a second wiring are laid out as a first metal layer in the memory cell that includes a first inverter and a second inverter. The first wiring is connected with two drains in the first inverter and a second gate wiring in the second inverter. The second wiring is connected with two drains in the second inverter and a first gate wiring in the first inverter. The first wiring is laid out to overlap with the second gate wiring, and the second wiring is laid out to overlap with the first gate wiring. A second metal layer is laid out above the first metal layer, and a third metal layer is laid out above the second metal layer.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: August 13, 2013
    Assignee: ON Semiconductor Trading, Ltd.
    Inventor: Kouichi Yamada
  • Publication number: 20130200468
    Abstract: A method of fabricating a FINFET includes the following steps. A plurality of fins is patterned in a wafer. A dummy gate is formed covering a portion of the fins which serves as a channel region. Spacers are formed on opposite sides of the dummy gate. The dummy gate is removed thus forming a trench between the spacers that exposes the fins in the channel region. A nitride material is deposited into the trench so as to cover a top and sidewalls of each of the fins in the channel region. The wafer is annealed to induce strain in the nitride material thus forming a stressed nitride film that covers and induces strain in the top and the sidewalls of each of the fins in the channel region of the device. The stressed nitride film is removed. A replacement gate is formed covering the fins in the channel region.
    Type: Application
    Filed: February 6, 2012
    Publication date: August 8, 2013
    Applicant: International Business Machines Corporation
    Inventors: Ming Cai, Dechao Guo, Chun-Chen Yeh
  • Publication number: 20130203226
    Abstract: A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a forntside heating is different from a power for a backside heating.
    Type: Application
    Filed: February 7, 2012
    Publication date: August 8, 2013
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chan-Lon Yang, Ching-Nan Hwang, Chi-Heng Lin, Chun-Yao Yang, Ger-Pin Lin, Ching-I Li
  • Publication number: 20130200466
    Abstract: A method for forming an integrated circuit (IC) including a silicide block poly resistor (SIBLK poly resistor) includes forming a dielectric isolation region in a top semiconductor surface of a substrate. A polysilicon layer is formed including patterned resistor polysilicon on the dielectric isolation region and gate polysilicon on the top semiconductor surface. Implanting is performed using a first shared metal-oxide-semiconductor (MOS)/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon and gate polysilicon of a MOS transistor with at least a first dopant. Implanting is then performed using a second shared MOS/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon, gate polysilicon and source and drain regions of the MOS transistor with at least a second dopant. A metal silicide is formed on a first and second portion of a top surface of the patterned resistor polysilicon to form the SIBLK poly resistor.
    Type: Application
    Filed: February 6, 2012
    Publication date: August 8, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: SONG ZHAO, GREGORY CHARLES BALDWIN, SHASHANK S. EKBOTE, YOUN SUNG CHOI
  • Publication number: 20130200448
    Abstract: A meander line resistor structure comprises a first resistor formed on a first active region, wherein the first resistor is formed by a plurality of first vias connected in series, a second resistor formed on a second active region, wherein the second resistor is formed by a plurality of second vias connected in series and a third resistor formed on the second active region, wherein the third resistor is formed by a plurality of third vias connected in series. The meander line resistor further comprises a first connector coupled between the first resistor and the second resistor.
    Type: Application
    Filed: February 3, 2012
    Publication date: August 8, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tsung Yen, Yu-Ling Lin
  • Patent number: 8502478
    Abstract: Provided are a variable field effect transistor (FET) designed to suppress a reduction of current between a source and a drain due to heat while decreasing a temperature of the FET, and an electrical and electronic apparatus including the variable gate FET. The variable gate FET includes a FET and a gate control device that is attached to a surface or a heat-generating portion of the FET and is connected to a gate terminal of the FET so as to vary a voltage of the gate terminal. A channel current between the source and drain is controlled by the gate control device that varies the voltage of the gate terminal when the temperature of the FET increases above a predetermined temperature.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: August 6, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hyun Tak Kim, Bong Jun Kim
  • Publication number: 20130193526
    Abstract: A semiconductor device may include body contacts on a finFET device for ESD protection. The semiconductor device comprises a semiconductor fin, a source/drain region and a body contact. The source/drain region and the body contact are in the semiconductor fin. A portion of the fin is laterally between the source/drain region and the body contact. The semiconductor fin is on a substrate.
    Type: Application
    Filed: January 31, 2012
    Publication date: August 1, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Hsiung Lo, Jam-Wem Lee, Wun-Jie Lin, Jen-Chou Tseng
  • Publication number: 20130183801
    Abstract: A method for manufacturing semiconductor devices includes providing a substrate having a first region and a second region defined thereon, and a shallow trench isolation (STI) formed in between the first region and the second region, the first region comprising a first gate structure and the second region comprising a second gate structure respectively formed therein; forming a patterned protecting layer covering at least the entire STI and the second region on the substrate; forming recesses not exposing the STI in the substrate respectively at two sides of the first gate structure; and forming an epitaxial layer in the recesses respectively, the epitaxial layer filling up the recesses.
    Type: Application
    Filed: January 18, 2012
    Publication date: July 18, 2013
    Inventors: Tsung-Min Kuo, Feng-Mou Chen, Wei-Che Chen, Chun-Chieh Fang
  • Publication number: 20130175596
    Abstract: An integrated circuit includes a transistor and a capacitor. The transistor includes a first semiconductor layer and a gate stack located on the first semiconductor layer. The gate stack includes a metal layer and a first high-k dielectric layer. A gate spacer is located on sidewalls of the gate stack. The first high-k dielectric layer is located between the first semiconductor layer and the metal layer and between the gate spacer and sidewalls of the metal layer. A first silicide region is located on a first source/drain region. A second silicide region is located on a second source/drain region. The capacitor includes a first terminal that comprises a third silicide region located on a portion of the second semiconductor. A second high-k dielectric layer is located on the silicide region. A second terminal comprises a metal layer that is located on the second high-k dielectric layer.
    Type: Application
    Filed: January 6, 2012
    Publication date: July 11, 2013
    Applicant: International Business Machines Corporation
    Inventors: Kangguo CHENG, Bruce Doris, Ali Khakifirooz, Ghavam G. Shahidi
  • Publication number: 20130161716
    Abstract: A non-volatile semiconductor memory device comprises a semiconductor substrate and a plurality of gate structures formed on a cell region of the semiconductor substrate. The plurality of gate structures include a first select-gate and a second select-gate disposed on the cell region, the first select-gate and the second select-gate spaced apart from each other. A plurality of cell gate structures are disposed between the first select-gate and the second select-gate. The first select-gate and an adjacent cell gate structure have no air gap defined therebetween. At least a pair of adjacent cell gate structures have an air gap defined therebetween.
    Type: Application
    Filed: December 21, 2011
    Publication date: June 27, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-Kyung KIM, Woosung CHOI
  • Patent number: 8466026
    Abstract: A semiconductor device having an MOSFET serving as an element to be protected, and an electrostatic protection MOSFET element mounted on the same substrate is produced with the small number of steps while implementing a high protection ability. Low concentration regions and gate electrodes are formed and then an insulation film is formed on a whole surface. Then, etching is performed using a resist pattern as a mask to leave the insulation film in a region from a part of the gate electrode to a part of the low concentration region in each of regions A1 and A3, and on a side wall of the gate electrode in a region A2. Then, a high concentration ion implantation is performed using the gate electrodes and the insulation films as masks, and then a silicide layer is formed.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: June 18, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Satoshi Hikida
  • Publication number: 20130119507
    Abstract: Semiconductor devices using a group III-V material, and methods of manufacturing the same, include a substrate having a groove, a group III-V material layer filling in the groove and having a height the same as a height of the substrate, a first semiconductor device on the group III-V material layer, and a second semiconductor device on the substrate near the groove. The group III-V material layer is spaced apart from inner side surfaces of the groove.
    Type: Application
    Filed: September 13, 2012
    Publication date: May 16, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-moon LEE, Young-jin CHO
  • Publication number: 20130105912
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the substrate of the resistor region; forming a tank in the STI of the resistor region; and forming a resistor in the tank and on the surface of the STI adjacent to two sides of the tank.
    Type: Application
    Filed: October 28, 2011
    Publication date: May 2, 2013
    Inventors: Chun-Wei Hsu, Po-Cheng Huang, Ren-Peng Huang, Jie-Ning Yang, Chia-Lin Hsu, Teng-Chun Tsai, Chih-Hsun Lin, Chang-Hung Kung, Yen-Ming Chen, Yu-Ting Li
  • Patent number: 8421139
    Abstract: A transistor includes a first fin structure and at least a second fin structure formed on a substrate. A deep trench area is formed between the first and second fin structures. The deep trench area extends through an insulator layer of the substrate and a semiconductor layer of the substrate. A high-k metal gate is formed within the deep trench area. A polysilicon layer is formed within the deep trench area adjacent to the metal layer. The polysilicon layer and the high-k metal layer are recessed below a top surface of the insulator layer. A poly strap in the deep trench area is formed on top of the high-k metal gate and the polysilicon material. The poly strap is dimensioned to be below a top surface of the first and second fin structures. The first fin structure and the second fin structure are electrically coupled to the poly strap.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: April 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Sivananda Kanakasabapathy, Hemanth Jagannathan, Geng Wang
  • Patent number: 8420432
    Abstract: Provided is a method of forming a semiconductor device. The method includes forming an insulating film on a semiconductor substrate, a conductive film on the insulating film, and a first structure and a second structure on the conductive film. The semiconductor substrate has first and second regions. The first and second structures are formed on the first and second regions, respectively. An impurity diffused region is formed in the semiconductor substrate using the first structure as a mask. The impurity diffused region overlaps the first structure. A portion of the first structure, and the conductive film are etched to respectively form a gate structure and a capacitor structure on the first and second regions.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: April 16, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Won Choi, Jun-Seok Yang, Keon-Yong Cheon, Sung-Hyun Yoon
  • Publication number: 20130087861
    Abstract: A semiconductor device comprises a metal gate electrode, a passive device and a hard mask layer. The passive device has a poly-silicon element layer. The hard mask layer is disposed on the metal gate electrode and the passive electrode and has a first opening and a second opening substantially coplanar with each other, wherein the metal gate electrode and the poly-silicon element layer are respectively exposed via the first opening and the second opening; and there is a distance between the first opening and the metal gate electrode substantially less than the distance between the second opening and the poly-silicon element layer.
    Type: Application
    Filed: October 6, 2011
    Publication date: April 11, 2013
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chieh-Te CHEN, Shih-Fang Tzou, Jiunn-Hsiung Liao, Yi-Po Lin