Clocking Or Synchronizing Of Logic Stages Or Gates Patents (Class 326/93)
  • Patent number: 10924091
    Abstract: A synchronizer circuit includes a first synchronizer having a first input for receiving a signal associated with a first clock signal, a second input for receiving a second clock signal, and an output for providing a synchronizer circuit output signal; a second synchronizer having a first input for receiving the signal associated with the first clock signal, a second input for receiving the second clock signal, and an output; a detection stage having a first input coupled to the output of the first synchronizer and to the output of the second synchronizer, a second input for receiving the second clock signal, and an output; and a fault output stage having a first input coupled to the detection stage, a second input for receiving the second clock signal, and an output for providing a fault output signal.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: February 16, 2021
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventor: Avneep Kumar Goyal
  • Patent number: 10892003
    Abstract: Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each other through a plurality of conductors. The logic die serves, for example, as a memory interface device to a memory access device, such as a processor. The logic die can include a command register that allows selective operation in either of two modes. In a direct mode, conventional command signals as well as row and column address signals are applied to the logic die, and the logic die can essentially couple these signals directly to the memory device dice. In an indirect mode, a packet containing a command and a composite address are applied to the logic die, and the logic die can decode the command and composite address to apply conventional command signals as well as row and column address signals to the memory device dice.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: January 12, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Joseph M. Jeddeloh
  • Patent number: 10884450
    Abstract: One embodiment includes a clock distribution system. The system includes at least one resonator spine that propagates a clock signal and at least one resonator rib conductively coupled to the at least one resonator spine and being arranged as a standing wave resonator. At least one of the at least one resonator rib has a thickness that varies along a length of the respective one of the at least one resonator rib. The system also includes at least one transformer-coupling line. Each of the at least one transformer-coupling line can be conductively coupled to an associated circuit and being inductively coupled to the at least one resonator rib to inductively generate a clock current corresponding to the clock signal to provide functions for the associated circuit.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: January 5, 2021
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Joshua A. Strong, Max E. Nielsen
  • Patent number: 10848140
    Abstract: System and method for detecting clock failure are disclosed. The system includes a pulse train generator, a delay circuit, and a failure detection circuit. The pulse train generator receives an input clock and generates a pulse train including a plurality of pulses aligned with a set of rising edges and a set of falling edges of the input clock. The delay circuit delays the input clock by a first time-interval to generate a first delayed clock. The failure detection circuit receives the pulse train and the first delayed clock from the pulse train generator and the delay circuit, respectively, and generates a clock detection signal that transitions from a first logic state to a second logic state based on a failure in the input clock.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: November 24, 2020
    Assignee: NXP USA, INC.
    Inventors: Dinesh Joshi, Nidhi Sinha, Akshay Kumar Pathak
  • Patent number: 10819342
    Abstract: A low-power low-setup integrated clock gating (ICG) cell is disclosed. The disclosed ICG cell includes a NOR gate configured to receive an enable (E) signal and a test enable (SE) signal, and to output an EN signal. The ICG cell may include a complex gate configured to receive the EN signal and a clock (CK) signal, and to output a latched enable (ELAT) signal. The ICG cell may further include a NAND gate configured to receive the ELAT signal and the CK signal, and to output an inverted enabled clock (ECKN) signal. The ICG cell may further include an inverter configured to receive the ECKN signal from the NAND gate, and to output an enable clock (ECK) signal.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: October 27, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Matthew Berzins, Lalitkumar Motagi
  • Patent number: 10809757
    Abstract: The preset invention provides a clock buffer including a first circuit, a second circuit and an edge collector, wherein the first circuit is arranged to receive an input clock signal to generate a first clock signal, the second circuit is arranged to receive the input clock signal to generate a second clock signal, and the edge collector is arranged to generate an output clock signal by using a falling edge of the first clock signal and a rising edge of the second clock signal.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: October 20, 2020
    Assignee: MEDIATEK INC.
    Inventors: Chien-Wei Chen, Yu-Li Hsueh
  • Patent number: 10797033
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for testing the resistance of through silicon vias (TSVs) which may be used, for example, to couple multiple memory dies of a semiconductor memory device. A force amplifier may selectively provide a known current along a mesh wiring structure and through the TSV to be tested. The force amplifier may be positioned on a vacant area of the memory device, while the mesh wiring structure may be positioned in an area beneath the TSVs of the layers of the device. A chopper instrumentation amplifier may be selectively coupled to the TSV to be tested to amplify a voltage across the TSV generated by the current passing through the TSV. The chopper instrumentation amplifier may be capable of determining small resistance values of the TSV.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Akira Ide
  • Patent number: 10756716
    Abstract: An electronic device according to the present disclosure is an electronic device having a function of removing glitches contained in a signal, and includes a glitch removal circuit which removes glitches from an inputted signal, and a count unit which counts a number of times removing glitches.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: August 25, 2020
    Assignee: FANUC CORPORATION
    Inventor: Takaaki Komatsu
  • Patent number: 10714165
    Abstract: Provided is a semiconductor controller that includes: an input buffer for comparing a data signal received from the outside with a reference voltage and storing the data signal; and a reference voltage control unit for generating the reference voltage corresponding to a protocol condition of the received data signal set between a first protocol condition and a second protocol condition and providing the reference voltage to the input buffer.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: July 14, 2020
    Assignee: SK hynix Inc.
    Inventors: Sang-Geun Bae, MinSoon Hwang
  • Patent number: 10673267
    Abstract: A charge and discharge control circuit operates between a first and a second power supply voltage of the secondary battery, and is used in a cascade-connection to the second charge and discharge control circuit having the same configuration, and includes an output circuit and an output terminal for discharge control, an input circuit and an input terminal for discharge control, and a control circuit. The input circuit includes a first MOS transistor having a source terminal connected to the input terminal and a gate terminal for receiving the first power supply voltage, a second MOS transistor having a drain terminal and a gate terminal connected to a drain terminal of the first MOS transistor and a source terminal for receiving the second power supply voltage, and a third MOS transistor current-mirror-connected to the second MOS transistor and having a drain terminal for supplying a discharge control input signal.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: June 2, 2020
    Assignee: ABLIC INC.
    Inventors: Hiroshi Saito, Kazuaki Sano, Takahiro Kashiuchi, Akihiko Suzuki, Takahiro Kuratomi
  • Patent number: 10671561
    Abstract: An integrated circuit device is disclosed including core circuitry and interface circuitry. The core circuitry outputs in parallel a set of data bits, while the interface circuitry couples to the core circuitry. The interface circuitry receives in parallel a first number of data bits among the set of data bits from the core circuitry and outputs in parallel a second number of data bits. The ratio of the first number to the second number is a non-power-of-2 value.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: June 2, 2020
    Assignee: Rambus Inc.
    Inventor: Frederick A Ware
  • Patent number: 10649484
    Abstract: The present disclosure provides devices and techniques to dynamically change the operating frequency of an interface where components on the interface have non-common clocks. An interface component may be provided with a frequency negotiation component to negotiate a shift in an operating frequency with other component on an interface where the different components have non-common clocks.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: May 12, 2020
    Assignee: INTEL CORPORATION
    Inventors: Anoop Mukker, Eng Hun Ooi, Robert J. Royer, Jr., Brian R. McFarlane
  • Patent number: 10558188
    Abstract: Digital systems formed on integrated circuits may include sequential logic circuitry. The sequential logic circuitry may form at least part of a finite state machine that records different logical states. The sequential logic circuitry may include a first latching circuit and a second latching circuit that each latch bits onto their respective outputs when clocked at different levels. The first latching circuit may output a first bit. Combinational logic circuitry may be distributed on both sides of the first latching circuit such that a combinational logic circuit interposed between the first and second latching circuits generates a second bit based on at least the first bit. The first and second bits may record one of two possible finite logical states of the sequential logic circuitry. By distributing combinational logic circuity on two sides of a given latching circuit, dynamic power consumption by the sequential logic circuitry may be optimized.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: February 11, 2020
    Assignee: 21, Inc.
    Inventors: Daniel Firu, Veerbhan Kheterpal, Nigel Drego
  • Patent number: 10560105
    Abstract: A delay-locked loop (DLL) is provided that includes both a first delay line and a second delay line. The delay-locked loop functions to synchronize a DLL output clock signal relative to a received clock signal using the first delay line while a phase difference between the received clock signal and a received data signal corresponds to a delay within an operating range for the first delay line. As the phase difference increases to force the first delay line out of its operating range, the delay-locked loop transitions to using the second delay line to synchronize the DLL output clock signal relative to the received clock signal.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: February 11, 2020
    Assignee: QUALCOMM Incorporated
    Inventor: Bo Sun
  • Patent number: 10541694
    Abstract: A PFD outputs a detection signal based on a phase difference or a frequency difference between a reference signal and a feedback signal, a charge pump circuit outputs a pulse signal based on the detection signal, and a loop filter outputs a control voltage based on the pulse signal. A VCO includes a ring oscillator where a plurality of delay element units, which include a plurality of delay elements (for example, inverter circuits) connected in parallel, are connected in series in a ring, controls the frequency of the output signal of the ring oscillator based on the control voltage, and controls the phase of the output signal of the ring oscillator by controlling the active number of delay elements, out of the plurality of delay elements, based on the detection signal. A frequency divider circuit generates and outputs a feedback signal by dividing the frequency of the output signal.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: January 21, 2020
    Assignee: SOCIONEXT INC.
    Inventors: Hajime Sato, Kenta Aruga
  • Patent number: 10536144
    Abstract: This disclosure relates to leakage current reduction in integrated circuits (ICs). In one aspect, an IC can include a digital logic circuit and a polarization circuit. The digital logic circuit can have a plurality of inputs and can include a plurality of logic gates. The polarization circuit can receive a standby signal and a digital input signal comprising a plurality of bits. When the standby signal is deactivated, the polarization circuit can control the plurality of inputs of the digital logic circuit based on the digital input signal. However, when the standby signal is activated the polarization circuit can control the plurality of inputs of the digital logic circuit to a low power state associated with a smaller leakage current of the plurality of logic gates relative to at least one other state of the digital logic circuit.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: January 14, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Christophe Vincent Antoine Laurent
  • Patent number: 10516383
    Abstract: Embodiments of the present disclosure pertain to reducing power consumption in a processor circuit. In one embodiment, a processor circuit comprises a plurality of data storage modules. The plurality of data storage modules each include one or more first multibit flip flop circuits having a first power consumption per bit and one or more second flip flop circuits having a second power consumption per bit. The first multibit flip flop circuits may have more bits than the second flip flop circuits. Additionally, the first power consumption per bit may be less than the second power consumption per bit such that power consumption is reduced when the first multibit flip flop circuits are used to store bits that change with a higher frequency than bits stored in the second flip flop circuits.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: December 24, 2019
    Assignee: Groq, Inc.
    Inventor: Sushma Honnavara-Prasad
  • Patent number: 10489536
    Abstract: A hardware verification system according to one embodiment includes, in part, a plurality of programmable devices. The plurality of programmable devices include a master scheduler, a plurality of schedulers and a plurality of programmable delay elements. A first one of the plurality of schedulers is configured to receive one or more delay values associated with one or more of the plurality of delay elements. Each of the plurality of programmable delay elements corresponds to a delay. The first scheduler is further configured to send a parameter corresponding to the one or more delay values to the master scheduler, and generate one or more signals corresponding to the one or more delay elements in response to a control signal the first scheduler receives from the master scheduler.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: November 26, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Alexander Rabinovitch, Cedric Jean Alquier, Sébastien Roger Delerse
  • Patent number: 10466739
    Abstract: A semiconductor device includes a clock selection block selecting a first or a second input clock as a reference clock based on a phase detection signal; a clock generation circuit outputting first to Nth sampling clocks by distributing the reference clock to first to Nth clock paths, and outputting a first training signal by delaying a test pulse through one clock path during a training operation; a data input circuit sampling input data based on the first and second input clocks and one sampling clock outputted through the same clock path as the first training signal among the first to Nth sampling clocks; and a training circuit delaying the test pulse by a reference delay value to output a second training signal, and comparing a phase of the first training signal with a phase of the second training signal to generate the phase detection signal, during the training operation.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: November 5, 2019
    Assignee: SK hynix Inc.
    Inventor: Ji-Eun Heo
  • Patent number: 10419016
    Abstract: An ADC and an analog-to-digital conversion method are provided. The ADC includes: a clock generator, including M transmission gates, where the M transmission gates are configured to receive a first clock signal that is periodically sent and separately perform gating control on the first clock signal, so as to generate M second clock signals, M is an integer that is greater than or equal to 2; M ADC channels that are configured in a time interleaving manner, configured to receive one analog signal and separately perform, under the control of the M second clock signals, sampling and analog-to-digital conversion on the analog signal, so as to obtain M digital signals, where each ADC channel is corresponding to one clock signal of the M second clock signals; and an adder, configured to add the M digital signals together in a digital field, so as to obtain a digital output signal.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: September 17, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jinda Yang, Liren Zhou
  • Patent number: 10401430
    Abstract: A semiconductor device according to an embodiment includes a plurality of scan chains each including a retention flip-flop, and a control section configured to perform restoration of data saved in a retention section of each retention flip-flop by reading the data from the retention section and after the data restoration, perform diagnosis of the retention flip-flops by performing comparison to determine whether or not an expected value of an output data string obtained as a result of a scan shift in the plurality of scan chains before the save and a value of an output data string obtained as a result of a scan shift of data in the plurality of scan chains after the restoration.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: September 3, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomoyuki Maekawa
  • Patent number: 10374584
    Abstract: An apparatus comprising: a flip-flip comprising a master stage and a slave stage, wherein the slave stage is coupled to the master stage, wherein the master and slave stages are coupled to a first power supply rail; and a scan circuitry coupled to the slave stage of the flip-flip, wherein at least a portion of the scan circuitry is coupled to a second power supply rail.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Charles Augustine, Muhammad Khellah, Arvind Raman, Feroze Merchant, Ashish Choubal
  • Patent number: 10368024
    Abstract: A stacked-type solid-state image sensor including a first semiconductor layer in which an imaging pixel portion is implemented, and a second semiconductor layer in which a digital signal processing unit is implemented, comprises a first timing control unit configured to generate a drive timing signal of the imaging pixel portion, an A/D converter configured to convert an analog signal output from each pixel of the imaging pixel portion into a digital signal, a second timing control unit configured to generate a drive timing signal of the A/D converter; and a status generation unit configured to receive an event signal generated by at least one of the first timing control unit and the second timing control unit and generate a status signal to restrict an operation of the digital signal processing unit.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: July 30, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yuichi Hirai
  • Patent number: 10355691
    Abstract: An apparatus, system and method are disclosed to block and replace intermediate combinatorial transitions that are correlated with secret data, also referred to as glitches, with random intermediate combinatorial transitions that are uncorrelated with the data being processed.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: July 16, 2019
    Assignee: THE ATHENA GROUP, INC.
    Inventor: Stuart Audley
  • Patent number: 10347536
    Abstract: Disclosed herein is a semiconductor structure including: a host substrate and one or more bonding layers on top of the host substrate. The structure further includes an entity on the one or more bonding layers, where the entity includes two transistors on opposite sides of a common layer of channel material, where each transistor includes a gate, where both gates overlap each other, where both transistors share the same source and drain regions, and where each transistor have a channel defined within a same portion of the common layer of channel material overlapped by both transistor gates.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: July 9, 2019
    Assignee: IMEC VZW
    Inventors: Amey Mahadev Walke, Nadine Collaert
  • Patent number: 10320386
    Abstract: The disclosed circuit arrangements include a logic circuit, multiple bi-stable circuits, and control circuitry coupled to the bi-stable circuits. Each bi-stable circuit has a data input, a clock input, and an output coupled to the logic circuit. The control circuitry is programmable to selectively connect outputs of the bi-stable circuits or signals at the data inputs of the plurality of bi-stable circuits to inputs of the logic circuit. The control circuitry generates one or more delayed clock signals from the clock signal, and selectively provides one of the one or more delayed clock signals or the clock signal without delay to the clock input of each of the first plurality of bi-stable circuits.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: June 11, 2019
    Assignee: XILINX, INC.
    Inventors: Ilya K. Ganusov, Brian C. Gaide, Henri Fraisse
  • Patent number: 10318305
    Abstract: Embodiments are provided for an asynchronous processor with pipelined arithmetic and logic unit. The asynchronous processor includes a non-transitory memory for storing instructions and a plurality of instruction execution units (XUs) arranged in a ring architecture for passing tokens. Each one of the XUs comprises a logic circuit configured to fetch a first instruction from the non-transitory memory, and execute the first instruction. The logic circuit is also configured to fetch a second instruction from the non-transitory memory, and execute the second instruction, regardless whether the one of the XUs holds a token for writing the first instruction. The logic circuit is further configured to write the first instruction to the non-transitory memory after fetching the second instruction.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: June 11, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Wuxian Shi, Yiqun Ge, Qifan Zhang, Tao Huang, Wen Tong
  • Patent number: 10305477
    Abstract: This disclosure relates to leakage current reduction in integrated circuits (ICs). In one aspect, an IC can include a digital logic circuit and a polarization circuit. The digital logic circuit can have a plurality of inputs and can include a plurality of logic gates. The polarization circuit can receive a standby signal and a digital input signal comprising a plurality of bits. When the standby signal is deactivated, the polarization circuit can control the plurality of inputs of the digital logic circuit based on the digital input signal. However, when the standby signal is activated the polarization circuit can control the plurality of inputs of the digital logic circuit to a low power state associated with a smaller leakage current of the plurality of logic gates relative to at least one other state of the digital logic circuit.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: May 28, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Christophe Vincent Antoine Laurent
  • Patent number: 10289775
    Abstract: Various embodiments described herein assign, within a circuit design, a clock tap to a clock device (e.g., flip-flop) to improve timing of a path between the clock tap and the clock device. In particular, some embodiments identify which clock devices should be assigned to a clock tap so as to improve final timing as seen under an on-chip variation timing analysis, such an AOCV/CPPR (advanced on-chip variation/common clock path pessimism removal) timing analysis. Some such embodiments may achieve this by identifying, after post-route-optimization, critical clock-tap-to-clock-device assignments based on timing analysis results (e.g., from AOCV/CPPR timing analysis) and feeding back those critical clock-tap-to-clock-device assignments to a process performing new clock tap assignments.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Brian Wilson, Charles Jay Alpert, Zhuo Li
  • Patent number: 10249241
    Abstract: The present disclosure provides a method and a device of driving a display and a display device. The method includes: conducting first image data combined with image data relevant to the first image data in time/space by a micro disturbance operation processing, to obtain second image data; and outputting the second image data. By changing the conventional driving mechanism, conducting the first image data combined with relevant image data with respect to a time axis by an operation processing, for example, adding a time axis correction parameter which may be dynamically adjusted and conducting a micro disturbance operation, so as to determine color gray scales of respective sub-pixels on the display according to an adjusted driving circuit, which may make colors of image data on the display more plentiful and optimize display effect.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: April 2, 2019
    Assignee: EverDisplay Optronics (Shanghai) Limited
    Inventor: Ren-Hung Lin
  • Patent number: 10248155
    Abstract: A semiconductor device includes a first clock generating circuit including a first control circuit and a first clock gating circuit, a first channel management circuit which communicates with the first clock generating circuit according to a full handshake method, a second clock generating circuit including a second control circuit and a second clock gating circuit, and a second channel management circuit which communicates with the second clock generating circuit according to the full handshake method. The first clock gating circuit outputs a first clock, and the second clock gating circuit outputs a second clock different from the first clock.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: April 2, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se Hun Kim, Ah Chan Kim, Youn Sik Choi, Jae Gon Lee
  • Patent number: 10216885
    Abstract: A method includes receiving a circuit design comprising an input scan chain comprising a plurality of latches connected by one or more scan connections, dividing the plurality of latches into one or more clusters, determining a number of scan controls for each cluster, placing the determined scan controls in selected locations; and adjusting the scan connections based on the scan control location. A corresponding computer system and computer program product are also disclosed.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Raghu G. GopalaKrishnaSetty, Ankit N. Kagliwal, Sridhar H. Rangarajan, James D. Warnock
  • Patent number: 10211820
    Abstract: Embodiments of a multi-stage clock generator architecture that generates multiple non-overlapping clock phase signals includes: a first stage clock generator configured to: divide an input clock signal into a number of clock signals, synchronize each clock signal to a transition edge of a synchronization signal to produce synchronized clock signals, wherein the synchronization signal is a delayed version of the input clock signal by at least an amount sufficient to ensure that each of the clock signals become stable in response to a transition edge of the input clock signal, and generate a number of clock phase signals based on the synchronized clock signals. The architecture also includes a later stage clock generator configured to: generate a set of mutually non-overlapping clock phase signals based on the input clock signal.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: February 19, 2019
    Assignee: NXP USA, Inc.
    Inventors: Mohammad Nizam Kabir, Mariam Hoseini, Rakesh Shiwale, Doug Garrity
  • Patent number: 10192635
    Abstract: A test methodologies for detecting both known and potentially unknown FinFET-specific faults by way of implementing an efficient and reliable base set of March elements in which multiple sequential March-type read operations are performed immediately after logic values (i.e., logic-0 or logic-1) are written into each FinFET cell of a memory array. For example, a March-type write-1 operation is performed, followed immediately by multiple sequentially-executed March-type read-1 operations, then a March-type write-0 operation is performed followed immediately by multiple sequentially-executed March-type read-0 operations. An optional additional March-type read-0 operation is performed before the March-type write-1 operation, and an optional additional March-type read-1 operation is performed before the March-type write-0 operation. The write-1-multiple-read-1 and write-0-multiple-read-0 sequences are performed using one or both of an increasing address order and a decreasing address order.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: January 29, 2019
    Assignee: Synopsys, Inc.
    Inventors: Grigor Tshagharyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
  • Patent number: 10176281
    Abstract: A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test (DUT). In one embodiment, the DUT includes multiple device clocks generating multiple device clock signals at multiple frequencies and at a defined frequency ratio; and the FPG hardware accelerator includes multiple accelerator clocks generating multiple accelerator clock signals to operate the FPGA hardware accelerator to simulate the operations of the DUT. In one embodiment, operations of the DUT are mapped to the FPGA hardware accelerator, and the accelerator clock signals are generated at multiple frequencies and at the defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA hardware accelerator. In an embodiment, the FPGA hardware accelerator may be used to control the frequencies of the multiple device clocks.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sameh W. Asaad, Mohit Kapur
  • Patent number: 10162922
    Abstract: A computer-implemented method for generating a circuit design is provided according to certain aspects. The method includes determining a gating efficiency of first gate-enable logic, determining a gating efficiency of second gate-enable logic, and determining one of the first gate-enable logic and the second gate-enable logic having a greater one of the determined gating efficiencies. The method also includes placing the determined one of the first gate-enable logic and the second gate-enable logic in clock gating logic of the circuit design, and placing another one of the first gate-enable logic and the second gate-enable in data gating logic of the circuit design.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: December 25, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Kalyan Kumar Oruganti, Kailash Digari, Sandeep Nellikatte Srivatsa
  • Patent number: 10158346
    Abstract: A pulse triggered flip flop circuit includes an exclusive OR clock generating stage that receives an input clock, data and produces an output clock pulse. The stage produces a output clock pulse that only goes away when the data is fully captured. The stage disables the output clock pulse only when the data is fully captured. Moreover, the circuit only toggles when the input data changes, reducing power consumption in some embodiments.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventors: Bhushan M. Borole, Anupama A. Thaploo, Altug Koker, Abhishek R. Appu, Kamal Sinha, Wenyin Fu
  • Patent number: 10152253
    Abstract: An asynchronous circuit including an asynchronous pipeline including two or more stages, each stage having: a buffering circuit for temporarily storing data to be transferred from one stage to the next based on a handshake protocol, the buffering circuit including a non-volatile memory; and a data presence detection circuit adapted to generate a data presence detection value indicating whether or not data is stored by the buffering circuit; and a control circuit adapted to perform a data back-up operation by independently controlling each buffering circuit to back-up the data it stores to its non-volatile memory based on the corresponding data presence detection value.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: December 11, 2018
    Assignees: Commissariat à l'Énergie Atomique et aux Énergies Alternatives, Centre National de la Recherche Scientifique
    Inventors: Eldar Zianbetov, Edith Beigne, Gregory Di Pendina
  • Patent number: 10134099
    Abstract: Intelligent cold storage system for storing pharmaceutical product containers, such as vials, ampules, syringes, bottles, medication tubes, blister packs and cartons, at the point of dispensing. Embodiments of the invention use product identification technology, such as radio-frequency identification (RFID) tags and barcode readers, to uniquely identify containers as they are added to or removed from the cold storage compartment, and automatically retrieve from a local or remote database a variety of details associated with the containers and their contents, such as manufacturing data, expiration dates, time out of refrigeration, inventory levels, safety information, usage statistics, known contraindications and warnings, etc. If the details indicate that there is a problem with a particular pharmaceutical (e.g.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: November 20, 2018
    Assignee: MERCK SHARP & DOHME CORP.
    Inventor: Alan J. Lowenstein
  • Patent number: 10133578
    Abstract: Embodiments are provided for an asynchronous processor with heterogeneous processors. In an embodiment, the apparatus for an asynchronous processor comprises a memory configured to cache instructions, and a first unit (XU) configured to processing a first instruction of the instructions. The apparatus also comprises a second XU having less restricted access than the first XU to a resource of the asynchronous processor and configured to process a second instruction of the instructions. The second instruction requires access to the resource. The apparatus further comprises a feedback engine configured to decode the first instruction and the second instruction, and issue the first instruction to the first XU, and a scheduler configured to send the second instruction to the second XU.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: November 20, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yiqun Ge, Wuxian Shi, Qifan Zhang, Tao Huang, Wen Tong
  • Patent number: 10115477
    Abstract: A test methodologies for detecting both known and potentially unknown FinFET-specific faults by way of implementing an efficient and reliable base set of March elements in which multiple sequential March-type read operations are performed immediately after logic values (i.e., logic-0 or logic-1) are written into each FinFET cell of a memory array. For example, a March-type write-1 operation is performed, followed immediately by multiple sequentially-executed March-type read-1 operations, then a March-type write-0 operation is performed followed immediately by multiple sequentially-executed March-type read-0 operations. An optional additional March-type read-0 operation is performed before the March-type write-1 operation, and an optional additional March-type read-1 operation is performed before the March-type write-0 operation. The write-1-multiple-read-1 and write-0-multiple-read-0 sequences are performed using one or both of an increasing address order and a decreasing address order.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: October 30, 2018
    Assignee: Synopsys, Inc.
    Inventors: Grigor Tshagharyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
  • Patent number: 10104004
    Abstract: An embodiment of the invention includes a packet processing pipeline. The packet processing pipeline includes match and action stages. Each match and action stage in incurs a match delay when match processing occurs and each match and action stage incurs an action delay when action processing occurs. A transport delay occurs between successive match and action stages when data is transferred from a first match and action stage to a second match and action stage.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: October 16, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Patrick W. Bosshart, Hun-Seok Kim
  • Patent number: 10090837
    Abstract: This disclosure relates to leakage current reduction in integrated circuits (ICs). In one aspect, an IC can include a digital logic circuit and a polarization circuit. The digital logic circuit can have a plurality of inputs and can include a plurality of logic gates. The polarization circuit can receive a standby signal and a digital input signal comprising a plurality of bits. When the standby signal is deactivated, the polarization circuit can control the plurality of inputs of the digital logic circuit based on the digital input signal. However, when the standby signal is activated the polarization circuit can control the plurality of inputs of the digital logic circuit to a low power state associated with a smaller leakage current of the plurality of logic gates relative to at least one other state of the digital logic circuit.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: October 2, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Christophe Vincent Antoine Laurent
  • Patent number: 10073937
    Abstract: A technique for implementing a clock tree distribution network having a clock buffer and a plurality of LC tanks that each take into \consideration local capacitance distributions and conductor resistances. An AC-based sizing formulation is applied to the buffer and to the LC tanks so as to reduce the total buffer area. The technique is iterative and can be fully automated while also reducing clock distribution power consumption.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: September 11, 2018
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventor: Matthew Guthaus
  • Patent number: 10069486
    Abstract: A register circuit includes a first pulse-latch circuit configured to store data from a first input node. A multiplexer circuit is configured to select between an output of the first pulse-latch circuit and a second input node. A second pulse-latch circuit is configured to store data provided by the multiplexer circuit. A control circuit is configured to switch, in response to a configuration signal, the register circuit between a flip-flop mode and a dual-latch mode.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: September 4, 2018
    Assignee: XILINX, INC.
    Inventors: Benjamin S. Devlin, Ilya K. Ganusov
  • Patent number: 10026457
    Abstract: An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. The second channel includes a second command control circuit independent of the first command control circuit. The calibration circuit is shared by the first channel and the second channel to generate a calibration code responsive to a calibration command generated responsive to a first calibration command from the first command control circuit and a second calibration command from the second command control circuit.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: July 17, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Tetsuya Arai, Junki Taniguchi
  • Patent number: 10025342
    Abstract: A control circuit of power gating of the present disclosure includes a control section that controls whether to perform power gating depending on a level of a clock signal for a logic circuit supplied with a power supply voltage through a power switch transistor, on the basis of a clock frequency of the clock signal.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: July 17, 2018
    Assignee: Sony Corporation
    Inventor: Ichiro Kumata
  • Patent number: 10007746
    Abstract: A system and method for generalized next-state-directed constrained random simulation may include obtaining an initial state for a finite state machine (FSM) constrained by a first Boolean random circuit; and unrolling the FSM, wherein each step of steps of the unrolling, except for a final step, is constrained by the first Boolean random circuit that defines a set of generalized cycles, and wherein the final step is constrained by a second Boolean random circuit.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: June 26, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventor: Guy Wolfovitz
  • Patent number: 9996645
    Abstract: A hardware verification system according to one embodiment includes, in part, a plurality of programmable devices. The plurality of programmable devices include a master scheduler, a plurality of schedulers and a plurality of programmable delay elements. A first one of the plurality of schedulers is configured to receive one or more delay values associated with one or more of the plurality of delay elements. Each of the plurality of programmable delay elements corresponds to a delay. The first scheduler is further configured to send a parameter corresponding to the one or more delay values to the master scheduler, and generate one or more signals corresponding to the one or more delay elements in response to a control signal the first scheduler receives from the master scheduler.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: June 12, 2018
    Assignee: SYNOPSYS, INC.
    Inventors: Alexander Rabinovitch, Cedric Alquier, Sebastien Delerse
  • Patent number: 9952619
    Abstract: The present disclosure provides devices and techniques to dynamically change the operating frequency of an interface where components on the interface have non-common clocks. An interface component may be provided with a frequency negotiation component to negotiate a shift in an operating frequency with other component on an interface where the different components have non-common clocks.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 24, 2018
    Assignee: INTEL CORPORATION
    Inventors: Anoop Mukker, Eng Hun Ooi, Robert J. Royer, Jr., Brian R. McFarlane