Abstract: An electronic assembly has a host wafer having a first circuit including wafer transistors and passive, non-transistor devices. Chiplets have a second circuit including at least one radio frequency (RF) transistor device. Electrical interconnects are between the chiplets and wafer. The electrical interconnects electrically connect the first circuit to the second circuits. Oscillators that have the wafer transistor, the RF transistor and the electrical interconnects produce a signal for built-in self-test circuits for testing an assembly design of the electronic assembly and speeds of the RF chiplet transistors.

Abstract: A semiconductor circuit includes a first pad, a second pad, swapping circuit, and an internal circuit. The internal circuit receives a first external signal and a second external signal, and generates a first internal signal and a second internal signal. Based on master information and swapping information, the swapping circuit couples the internal circuit to one of first and second pads to provide a path through which the first internal signal is output and a path through which the first external signal is received, and couples the internal circuit to the other of the first and second pads to provide a path through which the second internal signal is output and a path through which the second external signal is received.

Abstract: An electronic assembly has a host wafer having a first circuit including wafer transistors and passive, non-transistor devices. Chiplets have a second circuit including at least one radio frequency (RF) transistor device. Electrical interconnects are between the chiplets and wafer. The electrical interconnects electrically connect the first circuit to the second circuits. Oscillators that have the wafer transistor, the RF transistor and the electrical interconnects produce a signal for built-in self-test circuits for testing an assembly design of the electronic assembly and speeds of the RF chiplet transistors.

Abstract: An integrated clock gate (ICG) includes an OR-AND-INVERT gate to receive a first enable and a second enable; a first inverter coupled to the output of the OR-AND-INVERT; a first NAND gate coupled to the output of the first inverter; a second NAND gate coupled to the output of the OR-AND-INVERT; and a second inverter to provide a clock which is gated based on logic values of the first enable and/or the second enable, wherein an output of the second inverter is received as input by the OR-AND-INVERT-gate. The ICG circuit reduces capacitance of input clk pin, which translates to lower switching power when clock is gated and reduction in dynamic power of clock network, since buffers in clock tree driving the ICG cells can be downsized. The ICG cell has the smallest transistor count (and area) when compared to existing ICG cell topologies.

Abstract: A system includes a first park circuit having a signal input, an output, and a control input. The system also includes a first signal path having an input and an output, wherein the input of the first signal path is coupled to the output of the first park circuit. The system also includes a second park circuit having a signal input, an output, and a control input, wherein the signal input of the second park circuit is coupled to the output of the first signal path. The system further includes a second signal path having an input and an output, wherein the input of the second signal path is coupled to the output of the second park circuit.

Abstract: An electronic assembly has a host wafer having a first circuit including wafer transistors and passive, non-transistor devices. Chiplets have a second circuit including at least one radio frequency (RF) transistor device. Electrical interconnects are between the chiplets and wafer. The electrical interconnects electrically connect the first circuit to the second circuits. Oscillators that have the wafer transistor, the RF transistor and the electrical interconnects produce a signal for built-in self-test circuits for testing an assembly design of the electronic assembly and speeds of the RF chiplet transistors.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory device are configured to add variable delays to a command. The variable delays may be provided by a host device (e.g., a test equipment) using a test mode of the memory devices. Alternatively, the variable delays may be stored in nonvolatile memory (NVM) components of the memory devices. Further, mode registers of the memory devices may be set to indicate that the command is associated with the variable delays stored in the NVM components. Further, the memory devices may include delay components configured to add the variable delays to the command. Such variable delays facilitate staggered execution of the command across multiple memory devices so as to avoid (or mitigate) issues related to an instantaneous, large amount of current drawn from a power supply connected to the memory devices.

Abstract: An apparatus and method to protect unauthorized change to a reference clock for a processor. The apparatus comprises: a first oscillator to generate a first clock; a second oscillator to generate a second clock; a third oscillator to generate a third clock; a first counter to count frequency of the first clock with respect to a fourth clock; a second counter to count frequency of the second clock with respect to the fourth clock; a third counter to count frequency of the third clock with respect to the fourth clock; and a circuitry to compare frequencies of the first, second, and third clocks with one another. The oscillators can be embedded in an interposer or package. These oscillators include one or more of: LC oscillator, micro electro-mechanical system (MEMs) based resonator, or ring oscillator.

Abstract: A circuit includes a first delay filter, a first comparator, an inverter, a second delay filter, a second comparator, an OR gate, and a latch. A first delay filter input is coupled to an inverter input. The first comparator has a first comparator input coupled to a first delay filter output and a second comparator input. The second delay filter has an input coupled to an inverter output. The second comparator has a third comparator input coupled to a second delay filter output, and a fourth comparator input coupled to the second comparator input. The OR gate has an input coupled to a first comparator output and another input coupled to a second comparator output. The latch has a clock input coupled to an OR gate output and a latch input coupled to the inverter input. A latch output provides a deglitched signal.

Abstract: Embodiments of a method and device are disclosed. In an embodiment, a controller includes a plurality of memories each having registers that are accessible using an address, a plurality of memory controllers each coupled to a memory and configured to control read and write operations to the respective coupled memory, a bus coupled to each of the memory controllers configured to communicate data and commands to each of the memory controllers, a plurality of processing cores coupled to the bus and configured to read and write data to the memories through the memory controllers, and a plurality of isolation stages, each isolation stage being coupled between a memory controller and a memory and configured to isolate the respective memory from receiving a memory clock signal when the memory is not addressed by the memory controller.

Abstract: A logic circuit includes a data signal input, a computational module, a direct timing modulator and an amplitude and non-direct timing modulator. The data signal input inputs data signals. The computational module includes multiple logic elements interconnected to perform a logic function. The direct timing modulator modulates a propagation time of the input data signals from the data signal input to the computational unit, in accordance with a first set of control signals. The amplitude and non-direct timing modulator modulates the processing time of data signals by the computational module and the amplitude of data signals propagating through the computational module, in accordance with a second set of control signals.

Abstract: A low power operation method provides an apparatus with a data transmission rate. A power management unit (PMU), which is not influenced by voltage, process, and temperature, biases a high frequency oscillator (HOSC) and makes the HOSC generate a steady and high precision clock. The clock of the HOSC is used to modify a timing length of a timer which is referenced by a low frequency oscillator (LOSC) without PMU. At last, through the modified timing length, the apparatus achieves high precision periods and data transmissions with compensation for voltage, process, and temperature. Thus, the data transmission cycles of the apparatus maintain stable and robust even if the apparatus applies duty cycle usage of the HOSC and the PMU for reducing power consumption with actions of turning on and turning off. Consequently, the periodic apparatus maintains data transmission rate with the low power consumption advantage of non-periodic apparatus.

Abstract: In a power supplying system, a selection unit that selects one of a first power feed unit and a second power feed unit, a first voltage determination unit that compares a voltage of an output of the first power feed unit with a first threshold value, a second voltage determination unit that compares a voltage of an output of the second power feed unit with a second threshold value, and a management unit that sets the first threshold value and the second threshold value are provided.

Abstract: Systems, apparatuses, and methods for implementing a high-performance clock-gating circuit are described. A first pull-down stack receives enable and pulse signals on gates of N-type transistors which pull down an output node when the enable and pulse signals are both high. A pull-up transistor coupled to the output node receives a clock signal which turns off the pull-up transistor when the clock signal is high. A first pull-up stack receives the inverted pulse signal and the enable signal on gates of P-type transistors to cause the output node to be high when the enable signal and inverted pulse signal are low. A second pull-up stack maintains a high voltage on the output node after the pulse event has ended but while the clock signal is still high. A second pull-down stack maintains a low voltage on the output node after the pulse event but while the clock remains high.

Abstract: A device includes a master latch, a slave latch and a retention latch coupled to each other. The retention latch includes first and second active areas, first and second gate structures. The first and second active areas extend in a first direction. The first gate structure extends in a second direction, the first gate structure including first and second portions that are separated from each other. The first portion is arranged over the first active area, and the second portion is arranged over the second active area. The second gate structure extends in the second direction, and is arranged over the first active area. The second gate structure is separated from the second active area and the first gate structure in a layout view. An end portion of the second active area is between the first gate structure and the second gate structure.

Abstract: A method is disclosed including setting, at a plurality of devices, a plurality of VSYNC signals to a plurality of VSYNC frequencies, wherein a corresponding device VSYNC signal of a corresponding device is set to a corresponding device VSYNC frequency. The method including sending a plurality of signals between the plurality of devices, which are analyzed and used to adjust the relative timing between corresponding device VSYNC signals of at least two devices.

Abstract: A switch with clock-gating control and a method for clock gating a switch are described herein. In one example, the method generally includes detecting a state of one or more input ports and a state of one or more output ports of the switch, determining whether the state of the one or more input ports and the state of the one or more output ports has been stable for a preset number of clock cycles, and gating the switch from a clock signal until the state of the one or more input ports or the state of the one or more output ports change upon determining the states have been stable for the preset number of the cycles.

Abstract: A method and system for reducing power supply noise comprising receiving a primary data stream at a data rate. The primary data stream comprises a stream of bits having logical values of either zero or one. Then, splitting the primary data stream to create a first group of lower rate data streams and a second group of lower rate data streams. Processing the second group of lower rate data streams to invert the logic values of the bits of the lower rate data streams to create processed lower rate data streams. The first group of lower rate data streams are combined with the processed lower rate data streams to create a complementary data stream. Then, processing the primary data stream and the complementary data stream concurrently with a data processing system, the concurrent processing reducing noise on the power supply.

Abstract: This disclosure relates to a circuit comprising a first, second, and third data latch, and an input for a data signal. The first data latch may be configured to sample a delayed version of the data signal in response to a first control signal. The second data latch may be configured to sample the delayed version of the data signal in response to a run clock signal. The run clock signal may be configured to run for a predefined number of clock cycles subsequent to the first control signal. The third data latch may be configured to sample either an output signal of the first data latch or an output signal of the second data latch in response to a second control signal received after the predefined number of clock cycles of the run clock signal.

Abstract: Described is an apparatus to widen or improve a common mode range of a strong arm latch (SAL). In some embodiments, the SAL comprises a master-slave architecture with a common latch. The apparatus includes: a sampler to sample an input with a first clock, and to provide a sampled output on a node. The SAL is to receive the sampled output on the node, and to sample the sampled output according to a second clock. The apparatus comprises a digital-to-analog converter (DAC) coupled to the node, wherein the DAC is to adjust a common mode of the sampled output according to a digital control to the DAC.

Abstract: An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and deliberate routing of the clock signals from the clock sources to respective types of clock distribution networks on the integrated circuit.

Abstract: The present embodiments are generally directed to analyzing clock jitter. Jitter affects the clock delay of the circuit and the time the clock is available at sync points, so it is important to calculate its impact correctly to take appropriate margin during timing analysis. Jitter could be due to various reasons—one of them is due to IR Impact on the Clock Tree. IR drop variations between the two consecutive cycles can effectively reduce the available clock period for data to be correctly captured.

Abstract: An apparatus (e.g., a content addressable memory system) can have a controller; a first content addressable memory coupled to the controller and a second content addressable memory coupled to the controller. The controller can be configured to cause the first content addressable memory to compare input data to first data stored in the first content addressable memory and cause the second content addressable memory to compare the input data to second data stored in the second content addressable memory such the input data is compared to the first and second data concurrently and replace a result of the comparison of the input data to the first data with a result of the comparison of the input data to the second data in response to determining that the first data is invalid and that the second data corresponds to the first data.

Abstract: This disclosure describes techniques for compensating for amplifier drift. An amplifier is configured to generate an output that triggers a charge counter to generate a charge count value based on a charge count signal. A current digital-to-analog converter (IDAC) is coupled to the amplifier and configured to provide an offset current to a first input of the amplifier. An offset correction circuit is configured to: determine whether a duty cycle associated with the amplifier exceeds a specified threshold and generate a signal to cause the MAC to adjust the value of the offset current to compensate for amplifier drift based on determining whether the duty cycle exceeds the specified threshold.

Abstract: A synchronizer circuit includes a first synchronizer having a first input for receiving a signal associated with a first clock signal, a second input for receiving a second clock signal, and an output for providing a synchronizer circuit output signal; a second synchronizer having a first input for receiving the signal associated with the first clock signal, a second input for receiving the second clock signal, and an output; a detection stage having a first input coupled to the output of the first synchronizer and to the output of the second synchronizer, a second input for receiving the second clock signal, and an output; and a fault output stage having a first input coupled to the detection stage, a second input for receiving the second clock signal, and an output for providing a fault output signal.

Abstract: Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each other through a plurality of conductors. The logic die serves, for example, as a memory interface device to a memory access device, such as a processor. The logic die can include a command register that allows selective operation in either of two modes. In a direct mode, conventional command signals as well as row and column address signals are applied to the logic die, and the logic die can essentially couple these signals directly to the memory device dice. In an indirect mode, a packet containing a command and a composite address are applied to the logic die, and the logic die can decode the command and composite address to apply conventional command signals as well as row and column address signals to the memory device dice.

Abstract: One embodiment includes a clock distribution system. The system includes at least one resonator spine that propagates a clock signal and at least one resonator rib conductively coupled to the at least one resonator spine and being arranged as a standing wave resonator. At least one of the at least one resonator rib has a thickness that varies along a length of the respective one of the at least one resonator rib. The system also includes at least one transformer-coupling line. Each of the at least one transformer-coupling line can be conductively coupled to an associated circuit and being inductively coupled to the at least one resonator rib to inductively generate a clock current corresponding to the clock signal to provide functions for the associated circuit.

Abstract: System and method for detecting clock failure are disclosed. The system includes a pulse train generator, a delay circuit, and a failure detection circuit. The pulse train generator receives an input clock and generates a pulse train including a plurality of pulses aligned with a set of rising edges and a set of falling edges of the input clock. The delay circuit delays the input clock by a first time-interval to generate a first delayed clock. The failure detection circuit receives the pulse train and the first delayed clock from the pulse train generator and the delay circuit, respectively, and generates a clock detection signal that transitions from a first logic state to a second logic state based on a failure in the input clock.

Abstract: A low-power low-setup integrated clock gating (ICG) cell is disclosed. The disclosed ICG cell includes a NOR gate configured to receive an enable (E) signal and a test enable (SE) signal, and to output an EN signal. The ICG cell may include a complex gate configured to receive the EN signal and a clock (CK) signal, and to output a latched enable (ELAT) signal. The ICG cell may further include a NAND gate configured to receive the ELAT signal and the CK signal, and to output an inverted enabled clock (ECKN) signal. The ICG cell may further include an inverter configured to receive the ECKN signal from the NAND gate, and to output an enable clock (ECK) signal.

Abstract: The preset invention provides a clock buffer including a first circuit, a second circuit and an edge collector, wherein the first circuit is arranged to receive an input clock signal to generate a first clock signal, the second circuit is arranged to receive the input clock signal to generate a second clock signal, and the edge collector is arranged to generate an output clock signal by using a falling edge of the first clock signal and a rising edge of the second clock signal.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for testing the resistance of through silicon vias (TSVs) which may be used, for example, to couple multiple memory dies of a semiconductor memory device. A force amplifier may selectively provide a known current along a mesh wiring structure and through the TSV to be tested. The force amplifier may be positioned on a vacant area of the memory device, while the mesh wiring structure may be positioned in an area beneath the TSVs of the layers of the device. A chopper instrumentation amplifier may be selectively coupled to the TSV to be tested to amplify a voltage across the TSV generated by the current passing through the TSV. The chopper instrumentation amplifier may be capable of determining small resistance values of the TSV.

Abstract: An electronic device according to the present disclosure is an electronic device having a function of removing glitches contained in a signal, and includes a glitch removal circuit which removes glitches from an inputted signal, and a count unit which counts a number of times removing glitches.

Abstract: Provided is a semiconductor controller that includes: an input buffer for comparing a data signal received from the outside with a reference voltage and storing the data signal; and a reference voltage control unit for generating the reference voltage corresponding to a protocol condition of the received data signal set between a first protocol condition and a second protocol condition and providing the reference voltage to the input buffer.

Abstract: An integrated circuit device is disclosed including core circuitry and interface circuitry. The core circuitry outputs in parallel a set of data bits, while the interface circuitry couples to the core circuitry. The interface circuitry receives in parallel a first number of data bits among the set of data bits from the core circuitry and outputs in parallel a second number of data bits. The ratio of the first number to the second number is a non-power-of-2 value.

Abstract: A charge and discharge control circuit operates between a first and a second power supply voltage of the secondary battery, and is used in a cascade-connection to the second charge and discharge control circuit having the same configuration, and includes an output circuit and an output terminal for discharge control, an input circuit and an input terminal for discharge control, and a control circuit. The input circuit includes a first MOS transistor having a source terminal connected to the input terminal and a gate terminal for receiving the first power supply voltage, a second MOS transistor having a drain terminal and a gate terminal connected to a drain terminal of the first MOS transistor and a source terminal for receiving the second power supply voltage, and a third MOS transistor current-mirror-connected to the second MOS transistor and having a drain terminal for supplying a discharge control input signal.

Abstract: The present disclosure provides devices and techniques to dynamically change the operating frequency of an interface where components on the interface have non-common clocks. An interface component may be provided with a frequency negotiation component to negotiate a shift in an operating frequency with other component on an interface where the different components have non-common clocks.

Abstract: Digital systems formed on integrated circuits may include sequential logic circuitry. The sequential logic circuitry may form at least part of a finite state machine that records different logical states. The sequential logic circuitry may include a first latching circuit and a second latching circuit that each latch bits onto their respective outputs when clocked at different levels. The first latching circuit may output a first bit. Combinational logic circuitry may be distributed on both sides of the first latching circuit such that a combinational logic circuit interposed between the first and second latching circuits generates a second bit based on at least the first bit. The first and second bits may record one of two possible finite logical states of the sequential logic circuitry. By distributing combinational logic circuity on two sides of a given latching circuit, dynamic power consumption by the sequential logic circuitry may be optimized.

Abstract: A delay-locked loop (DLL) is provided that includes both a first delay line and a second delay line. The delay-locked loop functions to synchronize a DLL output clock signal relative to a received clock signal using the first delay line while a phase difference between the received clock signal and a received data signal corresponds to a delay within an operating range for the first delay line. As the phase difference increases to force the first delay line out of its operating range, the delay-locked loop transitions to using the second delay line to synchronize the DLL output clock signal relative to the received clock signal.

Abstract: A PFD outputs a detection signal based on a phase difference or a frequency difference between a reference signal and a feedback signal, a charge pump circuit outputs a pulse signal based on the detection signal, and a loop filter outputs a control voltage based on the pulse signal. A VCO includes a ring oscillator where a plurality of delay element units, which include a plurality of delay elements (for example, inverter circuits) connected in parallel, are connected in series in a ring, controls the frequency of the output signal of the ring oscillator based on the control voltage, and controls the phase of the output signal of the ring oscillator by controlling the active number of delay elements, out of the plurality of delay elements, based on the detection signal. A frequency divider circuit generates and outputs a feedback signal by dividing the frequency of the output signal.

Abstract: This disclosure relates to leakage current reduction in integrated circuits (ICs). In one aspect, an IC can include a digital logic circuit and a polarization circuit. The digital logic circuit can have a plurality of inputs and can include a plurality of logic gates. The polarization circuit can receive a standby signal and a digital input signal comprising a plurality of bits. When the standby signal is deactivated, the polarization circuit can control the plurality of inputs of the digital logic circuit based on the digital input signal. However, when the standby signal is activated the polarization circuit can control the plurality of inputs of the digital logic circuit to a low power state associated with a smaller leakage current of the plurality of logic gates relative to at least one other state of the digital logic circuit.

Abstract: Embodiments of the present disclosure pertain to reducing power consumption in a processor circuit. In one embodiment, a processor circuit comprises a plurality of data storage modules. The plurality of data storage modules each include one or more first multibit flip flop circuits having a first power consumption per bit and one or more second flip flop circuits having a second power consumption per bit. The first multibit flip flop circuits may have more bits than the second flip flop circuits. Additionally, the first power consumption per bit may be less than the second power consumption per bit such that power consumption is reduced when the first multibit flip flop circuits are used to store bits that change with a higher frequency than bits stored in the second flip flop circuits.

Abstract: A hardware verification system according to one embodiment includes, in part, a plurality of programmable devices. The plurality of programmable devices include a master scheduler, a plurality of schedulers and a plurality of programmable delay elements. A first one of the plurality of schedulers is configured to receive one or more delay values associated with one or more of the plurality of delay elements. Each of the plurality of programmable delay elements corresponds to a delay. The first scheduler is further configured to send a parameter corresponding to the one or more delay values to the master scheduler, and generate one or more signals corresponding to the one or more delay elements in response to a control signal the first scheduler receives from the master scheduler.

Abstract: A semiconductor device includes a clock selection block selecting a first or a second input clock as a reference clock based on a phase detection signal; a clock generation circuit outputting first to Nth sampling clocks by distributing the reference clock to first to Nth clock paths, and outputting a first training signal by delaying a test pulse through one clock path during a training operation; a data input circuit sampling input data based on the first and second input clocks and one sampling clock outputted through the same clock path as the first training signal among the first to Nth sampling clocks; and a training circuit delaying the test pulse by a reference delay value to output a second training signal, and comparing a phase of the first training signal with a phase of the second training signal to generate the phase detection signal, during the training operation.

Abstract: An ADC and an analog-to-digital conversion method are provided. The ADC includes: a clock generator, including M transmission gates, where the M transmission gates are configured to receive a first clock signal that is periodically sent and separately perform gating control on the first clock signal, so as to generate M second clock signals, M is an integer that is greater than or equal to 2; M ADC channels that are configured in a time interleaving manner, configured to receive one analog signal and separately perform, under the control of the M second clock signals, sampling and analog-to-digital conversion on the analog signal, so as to obtain M digital signals, where each ADC channel is corresponding to one clock signal of the M second clock signals; and an adder, configured to add the M digital signals together in a digital field, so as to obtain a digital output signal.

Abstract: A semiconductor device according to an embodiment includes a plurality of scan chains each including a retention flip-flop, and a control section configured to perform restoration of data saved in a retention section of each retention flip-flop by reading the data from the retention section and after the data restoration, perform diagnosis of the retention flip-flops by performing comparison to determine whether or not an expected value of an output data string obtained as a result of a scan shift in the plurality of scan chains before the save and a value of an output data string obtained as a result of a scan shift of data in the plurality of scan chains after the restoration.

Abstract: An apparatus comprising: a flip-flip comprising a master stage and a slave stage, wherein the slave stage is coupled to the master stage, wherein the master and slave stages are coupled to a first power supply rail; and a scan circuitry coupled to the slave stage of the flip-flip, wherein at least a portion of the scan circuitry is coupled to a second power supply rail.

Abstract: A stacked-type solid-state image sensor including a first semiconductor layer in which an imaging pixel portion is implemented, and a second semiconductor layer in which a digital signal processing unit is implemented, comprises a first timing control unit configured to generate a drive timing signal of the imaging pixel portion, an A/D converter configured to convert an analog signal output from each pixel of the imaging pixel portion into a digital signal, a second timing control unit configured to generate a drive timing signal of the A/D converter; and a status generation unit configured to receive an event signal generated by at least one of the first timing control unit and the second timing control unit and generate a status signal to restrict an operation of the digital signal processing unit.

Abstract: An apparatus, system and method are disclosed to block and replace intermediate combinatorial transitions that are correlated with secret data, also referred to as glitches, with random intermediate combinatorial transitions that are uncorrelated with the data being processed.

Abstract: Disclosed herein is a semiconductor structure including: a host substrate and one or more bonding layers on top of the host substrate. The structure further includes an entity on the one or more bonding layers, where the entity includes two transistors on opposite sides of a common layer of channel material, where each transistor includes a gate, where both gates overlap each other, where both transistors share the same source and drain regions, and where each transistor have a channel defined within a same portion of the common layer of channel material overlapped by both transistor gates.

Abstract: Embodiments are provided for an asynchronous processor with pipelined arithmetic and logic unit. The asynchronous processor includes a non-transitory memory for storing instructions and a plurality of instruction execution units (XUs) arranged in a ring architecture for passing tokens. Each one of the XUs comprises a logic circuit configured to fetch a first instruction from the non-transitory memory, and execute the first instruction. The logic circuit is also configured to fetch a second instruction from the non-transitory memory, and execute the second instruction, regardless whether the one of the XUs holds a token for writing the first instruction. The logic circuit is further configured to write the first instruction to the non-transitory memory after fetching the second instruction.