Clocking Or Synchronizing Of Logic Stages Or Gates Patents (Class 326/93)
  • Patent number: 10419016
    Abstract: An ADC and an analog-to-digital conversion method are provided. The ADC includes: a clock generator, including M transmission gates, where the M transmission gates are configured to receive a first clock signal that is periodically sent and separately perform gating control on the first clock signal, so as to generate M second clock signals, M is an integer that is greater than or equal to 2; M ADC channels that are configured in a time interleaving manner, configured to receive one analog signal and separately perform, under the control of the M second clock signals, sampling and analog-to-digital conversion on the analog signal, so as to obtain M digital signals, where each ADC channel is corresponding to one clock signal of the M second clock signals; and an adder, configured to add the M digital signals together in a digital field, so as to obtain a digital output signal.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: September 17, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jinda Yang, Liren Zhou
  • Patent number: 10401430
    Abstract: A semiconductor device according to an embodiment includes a plurality of scan chains each including a retention flip-flop, and a control section configured to perform restoration of data saved in a retention section of each retention flip-flop by reading the data from the retention section and after the data restoration, perform diagnosis of the retention flip-flops by performing comparison to determine whether or not an expected value of an output data string obtained as a result of a scan shift in the plurality of scan chains before the save and a value of an output data string obtained as a result of a scan shift of data in the plurality of scan chains after the restoration.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: September 3, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomoyuki Maekawa
  • Patent number: 10374584
    Abstract: An apparatus comprising: a flip-flip comprising a master stage and a slave stage, wherein the slave stage is coupled to the master stage, wherein the master and slave stages are coupled to a first power supply rail; and a scan circuitry coupled to the slave stage of the flip-flip, wherein at least a portion of the scan circuitry is coupled to a second power supply rail.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Charles Augustine, Muhammad Khellah, Arvind Raman, Feroze Merchant, Ashish Choubal
  • Patent number: 10368024
    Abstract: A stacked-type solid-state image sensor including a first semiconductor layer in which an imaging pixel portion is implemented, and a second semiconductor layer in which a digital signal processing unit is implemented, comprises a first timing control unit configured to generate a drive timing signal of the imaging pixel portion, an A/D converter configured to convert an analog signal output from each pixel of the imaging pixel portion into a digital signal, a second timing control unit configured to generate a drive timing signal of the A/D converter; and a status generation unit configured to receive an event signal generated by at least one of the first timing control unit and the second timing control unit and generate a status signal to restrict an operation of the digital signal processing unit.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: July 30, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yuichi Hirai
  • Patent number: 10355691
    Abstract: An apparatus, system and method are disclosed to block and replace intermediate combinatorial transitions that are correlated with secret data, also referred to as glitches, with random intermediate combinatorial transitions that are uncorrelated with the data being processed.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: July 16, 2019
    Assignee: THE ATHENA GROUP, INC.
    Inventor: Stuart Audley
  • Patent number: 10347536
    Abstract: Disclosed herein is a semiconductor structure including: a host substrate and one or more bonding layers on top of the host substrate. The structure further includes an entity on the one or more bonding layers, where the entity includes two transistors on opposite sides of a common layer of channel material, where each transistor includes a gate, where both gates overlap each other, where both transistors share the same source and drain regions, and where each transistor have a channel defined within a same portion of the common layer of channel material overlapped by both transistor gates.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: July 9, 2019
    Assignee: IMEC VZW
    Inventors: Amey Mahadev Walke, Nadine Collaert
  • Patent number: 10320386
    Abstract: The disclosed circuit arrangements include a logic circuit, multiple bi-stable circuits, and control circuitry coupled to the bi-stable circuits. Each bi-stable circuit has a data input, a clock input, and an output coupled to the logic circuit. The control circuitry is programmable to selectively connect outputs of the bi-stable circuits or signals at the data inputs of the plurality of bi-stable circuits to inputs of the logic circuit. The control circuitry generates one or more delayed clock signals from the clock signal, and selectively provides one of the one or more delayed clock signals or the clock signal without delay to the clock input of each of the first plurality of bi-stable circuits.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: June 11, 2019
    Assignee: XILINX, INC.
    Inventors: Ilya K. Ganusov, Brian C. Gaide, Henri Fraisse
  • Patent number: 10318305
    Abstract: Embodiments are provided for an asynchronous processor with pipelined arithmetic and logic unit. The asynchronous processor includes a non-transitory memory for storing instructions and a plurality of instruction execution units (XUs) arranged in a ring architecture for passing tokens. Each one of the XUs comprises a logic circuit configured to fetch a first instruction from the non-transitory memory, and execute the first instruction. The logic circuit is also configured to fetch a second instruction from the non-transitory memory, and execute the second instruction, regardless whether the one of the XUs holds a token for writing the first instruction. The logic circuit is further configured to write the first instruction to the non-transitory memory after fetching the second instruction.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: June 11, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Wuxian Shi, Yiqun Ge, Qifan Zhang, Tao Huang, Wen Tong
  • Patent number: 10305477
    Abstract: This disclosure relates to leakage current reduction in integrated circuits (ICs). In one aspect, an IC can include a digital logic circuit and a polarization circuit. The digital logic circuit can have a plurality of inputs and can include a plurality of logic gates. The polarization circuit can receive a standby signal and a digital input signal comprising a plurality of bits. When the standby signal is deactivated, the polarization circuit can control the plurality of inputs of the digital logic circuit based on the digital input signal. However, when the standby signal is activated the polarization circuit can control the plurality of inputs of the digital logic circuit to a low power state associated with a smaller leakage current of the plurality of logic gates relative to at least one other state of the digital logic circuit.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: May 28, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Christophe Vincent Antoine Laurent
  • Patent number: 10289775
    Abstract: Various embodiments described herein assign, within a circuit design, a clock tap to a clock device (e.g., flip-flop) to improve timing of a path between the clock tap and the clock device. In particular, some embodiments identify which clock devices should be assigned to a clock tap so as to improve final timing as seen under an on-chip variation timing analysis, such an AOCV/CPPR (advanced on-chip variation/common clock path pessimism removal) timing analysis. Some such embodiments may achieve this by identifying, after post-route-optimization, critical clock-tap-to-clock-device assignments based on timing analysis results (e.g., from AOCV/CPPR timing analysis) and feeding back those critical clock-tap-to-clock-device assignments to a process performing new clock tap assignments.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Brian Wilson, Charles Jay Alpert, Zhuo Li
  • Patent number: 10249241
    Abstract: The present disclosure provides a method and a device of driving a display and a display device. The method includes: conducting first image data combined with image data relevant to the first image data in time/space by a micro disturbance operation processing, to obtain second image data; and outputting the second image data. By changing the conventional driving mechanism, conducting the first image data combined with relevant image data with respect to a time axis by an operation processing, for example, adding a time axis correction parameter which may be dynamically adjusted and conducting a micro disturbance operation, so as to determine color gray scales of respective sub-pixels on the display according to an adjusted driving circuit, which may make colors of image data on the display more plentiful and optimize display effect.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: April 2, 2019
    Assignee: EverDisplay Optronics (Shanghai) Limited
    Inventor: Ren-Hung Lin
  • Patent number: 10248155
    Abstract: A semiconductor device includes a first clock generating circuit including a first control circuit and a first clock gating circuit, a first channel management circuit which communicates with the first clock generating circuit according to a full handshake method, a second clock generating circuit including a second control circuit and a second clock gating circuit, and a second channel management circuit which communicates with the second clock generating circuit according to the full handshake method. The first clock gating circuit outputs a first clock, and the second clock gating circuit outputs a second clock different from the first clock.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: April 2, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se Hun Kim, Ah Chan Kim, Youn Sik Choi, Jae Gon Lee
  • Patent number: 10216885
    Abstract: A method includes receiving a circuit design comprising an input scan chain comprising a plurality of latches connected by one or more scan connections, dividing the plurality of latches into one or more clusters, determining a number of scan controls for each cluster, placing the determined scan controls in selected locations; and adjusting the scan connections based on the scan control location. A corresponding computer system and computer program product are also disclosed.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Raghu G. GopalaKrishnaSetty, Ankit N. Kagliwal, Sridhar H. Rangarajan, James D. Warnock
  • Patent number: 10211820
    Abstract: Embodiments of a multi-stage clock generator architecture that generates multiple non-overlapping clock phase signals includes: a first stage clock generator configured to: divide an input clock signal into a number of clock signals, synchronize each clock signal to a transition edge of a synchronization signal to produce synchronized clock signals, wherein the synchronization signal is a delayed version of the input clock signal by at least an amount sufficient to ensure that each of the clock signals become stable in response to a transition edge of the input clock signal, and generate a number of clock phase signals based on the synchronized clock signals. The architecture also includes a later stage clock generator configured to: generate a set of mutually non-overlapping clock phase signals based on the input clock signal.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: February 19, 2019
    Assignee: NXP USA, Inc.
    Inventors: Mohammad Nizam Kabir, Mariam Hoseini, Rakesh Shiwale, Doug Garrity
  • Patent number: 10192635
    Abstract: A test methodologies for detecting both known and potentially unknown FinFET-specific faults by way of implementing an efficient and reliable base set of March elements in which multiple sequential March-type read operations are performed immediately after logic values (i.e., logic-0 or logic-1) are written into each FinFET cell of a memory array. For example, a March-type write-1 operation is performed, followed immediately by multiple sequentially-executed March-type read-1 operations, then a March-type write-0 operation is performed followed immediately by multiple sequentially-executed March-type read-0 operations. An optional additional March-type read-0 operation is performed before the March-type write-1 operation, and an optional additional March-type read-1 operation is performed before the March-type write-0 operation. The write-1-multiple-read-1 and write-0-multiple-read-0 sequences are performed using one or both of an increasing address order and a decreasing address order.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: January 29, 2019
    Assignee: Synopsys, Inc.
    Inventors: Grigor Tshagharyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
  • Patent number: 10176281
    Abstract: A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test (DUT). In one embodiment, the DUT includes multiple device clocks generating multiple device clock signals at multiple frequencies and at a defined frequency ratio; and the FPG hardware accelerator includes multiple accelerator clocks generating multiple accelerator clock signals to operate the FPGA hardware accelerator to simulate the operations of the DUT. In one embodiment, operations of the DUT are mapped to the FPGA hardware accelerator, and the accelerator clock signals are generated at multiple frequencies and at the defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA hardware accelerator. In an embodiment, the FPGA hardware accelerator may be used to control the frequencies of the multiple device clocks.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sameh W. Asaad, Mohit Kapur
  • Patent number: 10162922
    Abstract: A computer-implemented method for generating a circuit design is provided according to certain aspects. The method includes determining a gating efficiency of first gate-enable logic, determining a gating efficiency of second gate-enable logic, and determining one of the first gate-enable logic and the second gate-enable logic having a greater one of the determined gating efficiencies. The method also includes placing the determined one of the first gate-enable logic and the second gate-enable logic in clock gating logic of the circuit design, and placing another one of the first gate-enable logic and the second gate-enable in data gating logic of the circuit design.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: December 25, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Kalyan Kumar Oruganti, Kailash Digari, Sandeep Nellikatte Srivatsa
  • Patent number: 10158346
    Abstract: A pulse triggered flip flop circuit includes an exclusive OR clock generating stage that receives an input clock, data and produces an output clock pulse. The stage produces a output clock pulse that only goes away when the data is fully captured. The stage disables the output clock pulse only when the data is fully captured. Moreover, the circuit only toggles when the input data changes, reducing power consumption in some embodiments.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventors: Bhushan M. Borole, Anupama A. Thaploo, Altug Koker, Abhishek R. Appu, Kamal Sinha, Wenyin Fu
  • Patent number: 10152253
    Abstract: An asynchronous circuit including an asynchronous pipeline including two or more stages, each stage having: a buffering circuit for temporarily storing data to be transferred from one stage to the next based on a handshake protocol, the buffering circuit including a non-volatile memory; and a data presence detection circuit adapted to generate a data presence detection value indicating whether or not data is stored by the buffering circuit; and a control circuit adapted to perform a data back-up operation by independently controlling each buffering circuit to back-up the data it stores to its non-volatile memory based on the corresponding data presence detection value.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: December 11, 2018
    Assignees: Commissariat √† l'√Čnergie Atomique et aux √Čnergies Alternatives, Centre National de la Recherche Scientifique
    Inventors: Eldar Zianbetov, Edith Beigne, Gregory Di Pendina
  • Patent number: 10134099
    Abstract: Intelligent cold storage system for storing pharmaceutical product containers, such as vials, ampules, syringes, bottles, medication tubes, blister packs and cartons, at the point of dispensing. Embodiments of the invention use product identification technology, such as radio-frequency identification (RFID) tags and barcode readers, to uniquely identify containers as they are added to or removed from the cold storage compartment, and automatically retrieve from a local or remote database a variety of details associated with the containers and their contents, such as manufacturing data, expiration dates, time out of refrigeration, inventory levels, safety information, usage statistics, known contraindications and warnings, etc. If the details indicate that there is a problem with a particular pharmaceutical (e.g.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: November 20, 2018
    Assignee: MERCK SHARP & DOHME CORP.
    Inventor: Alan J. Lowenstein
  • Patent number: 10133578
    Abstract: Embodiments are provided for an asynchronous processor with heterogeneous processors. In an embodiment, the apparatus for an asynchronous processor comprises a memory configured to cache instructions, and a first unit (XU) configured to processing a first instruction of the instructions. The apparatus also comprises a second XU having less restricted access than the first XU to a resource of the asynchronous processor and configured to process a second instruction of the instructions. The second instruction requires access to the resource. The apparatus further comprises a feedback engine configured to decode the first instruction and the second instruction, and issue the first instruction to the first XU, and a scheduler configured to send the second instruction to the second XU.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: November 20, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yiqun Ge, Wuxian Shi, Qifan Zhang, Tao Huang, Wen Tong
  • Patent number: 10115477
    Abstract: A test methodologies for detecting both known and potentially unknown FinFET-specific faults by way of implementing an efficient and reliable base set of March elements in which multiple sequential March-type read operations are performed immediately after logic values (i.e., logic-0 or logic-1) are written into each FinFET cell of a memory array. For example, a March-type write-1 operation is performed, followed immediately by multiple sequentially-executed March-type read-1 operations, then a March-type write-0 operation is performed followed immediately by multiple sequentially-executed March-type read-0 operations. An optional additional March-type read-0 operation is performed before the March-type write-1 operation, and an optional additional March-type read-1 operation is performed before the March-type write-0 operation. The write-1-multiple-read-1 and write-0-multiple-read-0 sequences are performed using one or both of an increasing address order and a decreasing address order.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: October 30, 2018
    Assignee: Synopsys, Inc.
    Inventors: Grigor Tshagharyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
  • Patent number: 10104004
    Abstract: An embodiment of the invention includes a packet processing pipeline. The packet processing pipeline includes match and action stages. Each match and action stage in incurs a match delay when match processing occurs and each match and action stage incurs an action delay when action processing occurs. A transport delay occurs between successive match and action stages when data is transferred from a first match and action stage to a second match and action stage.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: October 16, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Patrick W. Bosshart, Hun-Seok Kim
  • Patent number: 10090837
    Abstract: This disclosure relates to leakage current reduction in integrated circuits (ICs). In one aspect, an IC can include a digital logic circuit and a polarization circuit. The digital logic circuit can have a plurality of inputs and can include a plurality of logic gates. The polarization circuit can receive a standby signal and a digital input signal comprising a plurality of bits. When the standby signal is deactivated, the polarization circuit can control the plurality of inputs of the digital logic circuit based on the digital input signal. However, when the standby signal is activated the polarization circuit can control the plurality of inputs of the digital logic circuit to a low power state associated with a smaller leakage current of the plurality of logic gates relative to at least one other state of the digital logic circuit.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: October 2, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Christophe Vincent Antoine Laurent
  • Patent number: 10073937
    Abstract: A technique for implementing a clock tree distribution network having a clock buffer and a plurality of LC tanks that each take into \consideration local capacitance distributions and conductor resistances. An AC-based sizing formulation is applied to the buffer and to the LC tanks so as to reduce the total buffer area. The technique is iterative and can be fully automated while also reducing clock distribution power consumption.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: September 11, 2018
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventor: Matthew Guthaus
  • Patent number: 10069486
    Abstract: A register circuit includes a first pulse-latch circuit configured to store data from a first input node. A multiplexer circuit is configured to select between an output of the first pulse-latch circuit and a second input node. A second pulse-latch circuit is configured to store data provided by the multiplexer circuit. A control circuit is configured to switch, in response to a configuration signal, the register circuit between a flip-flop mode and a dual-latch mode.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: September 4, 2018
    Assignee: XILINX, INC.
    Inventors: Benjamin S. Devlin, Ilya K. Ganusov
  • Patent number: 10026457
    Abstract: An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. The second channel includes a second command control circuit independent of the first command control circuit. The calibration circuit is shared by the first channel and the second channel to generate a calibration code responsive to a calibration command generated responsive to a first calibration command from the first command control circuit and a second calibration command from the second command control circuit.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: July 17, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Tetsuya Arai, Junki Taniguchi
  • Patent number: 10025342
    Abstract: A control circuit of power gating of the present disclosure includes a control section that controls whether to perform power gating depending on a level of a clock signal for a logic circuit supplied with a power supply voltage through a power switch transistor, on the basis of a clock frequency of the clock signal.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: July 17, 2018
    Assignee: Sony Corporation
    Inventor: Ichiro Kumata
  • Patent number: 10007746
    Abstract: A system and method for generalized next-state-directed constrained random simulation may include obtaining an initial state for a finite state machine (FSM) constrained by a first Boolean random circuit; and unrolling the FSM, wherein each step of steps of the unrolling, except for a final step, is constrained by the first Boolean random circuit that defines a set of generalized cycles, and wherein the final step is constrained by a second Boolean random circuit.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: June 26, 2018
    Assignee: Cadence Design Systems, Inc.
    Inventor: Guy Wolfovitz
  • Patent number: 9996645
    Abstract: A hardware verification system according to one embodiment includes, in part, a plurality of programmable devices. The plurality of programmable devices include a master scheduler, a plurality of schedulers and a plurality of programmable delay elements. A first one of the plurality of schedulers is configured to receive one or more delay values associated with one or more of the plurality of delay elements. Each of the plurality of programmable delay elements corresponds to a delay. The first scheduler is further configured to send a parameter corresponding to the one or more delay values to the master scheduler, and generate one or more signals corresponding to the one or more delay elements in response to a control signal the first scheduler receives from the master scheduler.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: June 12, 2018
    Assignee: SYNOPSYS, INC.
    Inventors: Alexander Rabinovitch, Cedric Alquier, Sebastien Delerse
  • Patent number: 9952619
    Abstract: The present disclosure provides devices and techniques to dynamically change the operating frequency of an interface where components on the interface have non-common clocks. An interface component may be provided with a frequency negotiation component to negotiate a shift in an operating frequency with other component on an interface where the different components have non-common clocks.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 24, 2018
    Assignee: INTEL CORPORATION
    Inventors: Anoop Mukker, Eng Hun Ooi, Robert J. Royer, Jr., Brian R. McFarlane
  • Patent number: 9887698
    Abstract: A circuit is disclosed that includes a latch and a logic circuit. The latch includes is configured to generate a gating control signal in response to a latch enable signal and an input clock signal. The latch includes a pair of logic gates each configured to perform multi-level compound logic function. The logic circuit is configured to receive the gating control signal and the input clock signal, and generate an output clock signal in response to the gating control signal and the input clock signal.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: February 6, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Lin Liu, Lee-Chung Lu, Shang-Chih Hsieh
  • Patent number: 9876499
    Abstract: A semiconductor device suitable for low-voltage driving. The semiconductor device includes a first transistor, a second transistor, a power supply line, a circuit, and a memory circuit. The first transistor controls electrical continuity between the circuit and the power supply line. The memory circuit stores data for setting a gate potential of the first transistor. The second transistor controls electrical continuity between an output node of the memory circuit and a gate of the first transistor. The second transistor is a transistor with an ultralow off-state current, for example, an oxide semiconductor transistor. In a period for operating the circuit, a first potential is input to the power supply line and the second transistor is turned off. In a period for updating the gate potential of the first transistor, a second potential is input to the power supply line. The second potential is higher than the first potential.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: January 23, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Munehiro Kozuma, Takayuki Ikeda, Yoshiyuki Kurokawa, Takeshi Aoki, Yuki Okamoto
  • Patent number: 9875786
    Abstract: A device includes a cutting circuit that is coupled between power supply lines in series with first and second output circuits which drive an output terminal in a push-pull manner. Each of the first and second output circuits includes a plurality of output transistors. The cutting circuit is rendered non-conductive when each of the transistors in the first and second output circuits is rendered non-conductive.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: January 23, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Tetsuya Arai, Yoshinori Matsui
  • Patent number: 9830418
    Abstract: A method includes providing a first clock tree including a root clock and a plurality of levels of integrated clock gates (ICGs) under the root clock. The plurality of levels of ICGs in the first clock tree is flattened to generate a second clock tree including a plurality of ICGs in a same level under the root clock. A fake module is formed to reserve a region between the root clock and the plurality of ICGs. The fake module includes the root clock as a first input, and a first plurality of outputs coupled to clock-inputs of the plurality of ICGs. A skew balancing is performed on the second clock tree using a clock tree synthesis (CTS) tool to generate a third clock tree, wherein no buffers are inserted into the fake module, and wherein buffers are inserted by the CTS tool under the plurality of ICGs.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: November 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ray Chih-Jui Peng
  • Patent number: 9823688
    Abstract: A method for designing a clock tree is disclosed. In one embodiment, a preliminary clock tree design for an integrated circuit (IC) is processed. The clock tree includes a root node, a number of intermediate levels, and a leaf level that is coupled to a number of clocked circuits. Clock gating circuits are placed at the leaf level of the clock tree, and at least some of the intermediate levels. Processing the preliminary clock tree design includes ensuring that an equal number of clock gating circuits are coupled between each leaf level clock gating circuit and the root node. After processing the preliminary clock tree design, clock tree synthesis is performed by executing a clock tree synthesis tool on a computer system to generate a synthesized clock tree design.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: November 21, 2017
    Assignee: Apple Inc.
    Inventors: Karthik Rajagopal, Narayanan V. Thondugulam, Rahul Sharma
  • Patent number: 9768756
    Abstract: According to one general aspect, an apparatus may include a latch, and a control circuit. The latch may receive an input enable signal and generate a latched enable signal. The latch may also pass the input enable signal to the latched enable signal when the latch is transparent. The control circuit may be electrically coupled to the latch. The control circuit may receive as input an ungated clock signal, and generate a gated clock signal and a latch control signal. The latch control signal may be configured to make the latch transparent when the ungated clock signal is in a predefined state and when one of the input enable signal and the latched enable signal are in an enabled state. The control circuit may be configured to pass the ungated clock signal to the gated clock signal when the latched enable signal is in the enabled state.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: September 19, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: James Jung Lim, Matthew Berzins
  • Patent number: 9762248
    Abstract: The arrival time of an asynchronous signal from an asynchronous domain at a synchronizer circuit of a synchronous domain is modified by injecting synchronous domain timing into an additional last stage of the asynchronous logic function generating the asynchronous signal. That reduces the probability of metastability by increasing the probability that the asynchronous signal will arrive at the synchronizer at a time that can guarantee the setup time for the flip-flop(s) of the synchronizer.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: September 12, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Greg Sadowski
  • Patent number: 9754063
    Abstract: Reducing dynamic clock skew and/or slew in an electronic circuit is provided by: referencing a layout database and/or netlist of a design for the electronic circuit; identifying a set of neighboring buffer pairs with active buffers and adjacent sub-meshes, which are connected by a shorting bar; for each neighboring buffer pair of the set: placing a dummy buffer for each of their active buffers in the adjacent sub-meshes close to the active buffers; routing an input of a first dummy buffer located in a first sub-mesh to an output of an active buffer in a second sub-mesh; routing an input of a second dummy buffer located in the second sub-mesh to an output of an active buffer in the first sub-mesh; and connecting inputs of the first and second dummy buffers to the shorting bar.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: September 5, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andreas Arp, Fatih Cilek, Guenther Hutzl, Michael Koch, Matthias Ringe
  • Patent number: 9740270
    Abstract: An electronic device includes: an operation section, a reception section, a human body detection sensor, and a mode switching section. The mode switching section switches the electronic device between a normal operation mode permitting a normal operation and a sleep mode in a power saving state based on presence or absence of a detection signal from the human body detection sensor. Then the mode switching section stops in a case where a state in which the reception section receives an operation made by use of the operation section continues for a predefined period of time the switching between the normal operation mode and the sleep mode based on the presence or absence of the detection signal.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: August 22, 2017
    Assignee: KYOCERA Document Solutions Inc.
    Inventor: Taro Kurahashi
  • Patent number: 9740234
    Abstract: An on-chip clock controller includes a primary clock gating cell and a secondary clock gating cell. The primary clock gating cell includes a first clock input terminal coupled to receive an input clock signal and a first enable input terminal coupled to receive an enable signal. The primary clock gating cell also include a first clock output terminal configured to generate a first output clock signal based at least in part on the input clock signal and the enable signal. The secondary clock gating includes a second clock input terminal coupled to receive the input clock signal and a second clock output terminal configured to generate a second output clock signal based at least in part on the input clock signal. The enable signal is based at least in part on the second output clock signal.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: August 22, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Hong Kim, Paul Policke, Anirudh Kadiyala
  • Patent number: 9720438
    Abstract: A clock switch device includes a controller and a switching circuit. The controller sets a clock switch period using a control signal when a logic level of a mode signal is changed. The switching circuit receives a first clock signal, a second clock signal and an auxiliary clock signal. The switching circuit, based on the control signal, outputs one clock signal between the first clock signal and the second clock signal as a glitch free clock signal before the clock switch period, stops outputting the one clock signal and outputs the auxiliary clock signal as the glitch free clock signal during the clock switch period, and stops outputting the auxiliary clock signal and outputs another clock signal between the first clock signal and the second clock signal as the glitch free clock signal after the clock switch period.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: August 1, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: June-Hee Lee, Bong-Kyu Kim, Dong-Chul Choi, Gun-Il Kang
  • Patent number: 9716664
    Abstract: A network device that performs information centric networking (ICN) in an ICN network receives an Interest from a consumer as the Interest traverses an Interest path to a data responder. The Interest requests data by name and indicates an accumulated Interest queuing delay experienced by the Interest on the Interest path. The network device enqueues the Interest to an Interest queue and dequeues the Interest from the Interest queue, and determines a local Interest queuing delay between the enqueing and dequeuing. The network device increases the indicated accumulated Interest queuing delay by the local Interest queueing delay, and forwards the Interest along the Interest path. The network device receives a Data packet satisfying the Interest as the Data packet traverses the Interest path in reverse. The network device increases an accumulated Data queueing delay indicated in the Data packet, and then forwards the Data packet to the consumer.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: July 25, 2017
    Assignee: Cisco Technology, Inc.
    Inventor: Dave Oran
  • Patent number: 9698780
    Abstract: This disclosure relates to leakage current reduction in integrated circuits (ICs). In one aspect, an IC can include a digital logic circuit and a polarization circuit. The digital logic circuit can have a plurality of inputs and can include a plurality of logic gates. The polarization circuit can receive a standby signal and a digital input signal comprising a plurality of bits. When the standby signal is deactivated, the polarization circuit can control the plurality of inputs of the digital logic circuit based on the digital input signal. However, when the standby signal is activated the polarization circuit can control the plurality of inputs of the digital logic circuit to a low power state associated with a smaller leakage current of the plurality of logic gates relative to at least one other state of the digital logic circuit.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: July 4, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Christophe Vincent Antoine Laurent
  • Patent number: 9686578
    Abstract: The present invention is intended to permit both real-time display of a picture represented by a non-compressed video signal on a television and display of a picture represented by a compressed video signal at any desired time by simultaneously transmitting the compressed video signal and non-compressed video signal via one interface. An STB packetizes a compressed video signal, and multiplexes the compressed video signal and a blanking signal combined with a non-compressed video signal. Thus, both the video signals are transmitted simultaneously. A picture represented by the non-compressed video signal is displayed on a television in real time. The compressed video signal is stored in a storage medium incorporated in the television, read at any user's desired time, and decoded so that a picture represented by the compressed video signal can be viewed at the user's desired time.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: June 20, 2017
    Assignee: Hitachi Maxell, Ltd.
    Inventors: Nobuaki Kabuto, Akira Shibata, Yoshiaki Mizuhashi
  • Patent number: 9680480
    Abstract: A reconfigurable digital phase-locked loop integrated circuit is disclosed which is coupleable to a reference frequency generator to generate an input signal having a reference frequency. A representative embodiment of the reconfigurable digital phase-locked loop integrated circuit may include a first digital phase-locked loop circuit configured to generate a first signal having a first frequency which is an integer multiple of the reference frequency; and a second digital phase-locked loop circuit coupled to the first digital phase-locked loop, the second digital phase-locked loop configured to generate a second, output signal having a second output frequency in response to a plurality of configuration parameters, the second frequency having a configurable fractional offset from the integer multiple of the reference frequency, and to match a phase of the second output signal with a first signal phase.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: June 13, 2017
    Assignee: Movellus Circuits, Inc.
    Inventors: Jeffrey Alan Fredenburg, Muhammad Faisal, David Michael Moore
  • Patent number: 9634668
    Abstract: This application discloses the technique to pipeline the Clock Guided Logic. Latch based storage elements are used in CGL based design such that when first stage CGL elements are in precharge phase the second stage CGL elements are in evaluate phase and vice-versa resulting into higher design throughput.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: April 25, 2017
    Assignee: Picogem Corporation
    Inventor: Ashutosh Kumar Das
  • Patent number: 9595474
    Abstract: A die stack comprises a first integrated circuit (IC) die having at least a first device comprising a first source, a first drain and a first gate electrode above a first channel region between the first source and the first drain. A second IC die has at least a second device comprising a second source, a second drain and a second gate electrode above a second channel region between the second source and the second drain. The second gate electrode is connected to the first gate electrode by a path including a first through substrate via (TSV), the second drain connected to the first source by a path including a second TSV.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: March 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao Chieh Li, Ruey-Bin Sheen, Chih-Hsien Chang
  • Patent number: 9590596
    Abstract: A receiving circuit may include a wide range receiving circuit and a parallelizing circuit. The wide range receiving circuit may amplify an input signal which swings within a first range and generate an intermediate output signal which swings within a second range wider than the first range. The parallelizing circuit may compare the intermediate output signal with a second reference voltage and amplify the intermediate output signal accordingly and generate output signals which swing within a third range wider than the second range.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: March 7, 2017
    Assignee: SK HYNIX INC.
    Inventor: Dong Uk Lee
  • Patent number: 9577635
    Abstract: A CGC includes an enable module and a latch module. The enable module has an enable module input and an enable module output. The latch module has latch module inputs and a latch module output. The latch module inputs include a latch module clock input for receiving a clock and a latch module enable input for receiving the enable module output. The latch module enable input is coupled to the enable module output. The latch module is configured to enable and to disable the clock via the latch module output based on the enable module input. The latch module includes an internal enable node that is the latch module output. The latch module is configured to cause the internal enable node to transition from low to high as a function of the enable module output and ?C, where E is the internal enable node and C is the clock.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: February 21, 2017
    Assignee: QUALCOMM INCORPORATED
    Inventors: Seid Hadi Rasouli, Steven James Dillen, Animesh Datta