Flash EEPROM device and method for fabricating the same
In a flash EEPROM device, and method for fabricating the same, no bit line contact is made, thereby minimizing a design rule between a contact and a gate. Thus, cell size may be reduced. The flash EEPROM device includes a semiconductor substrate having an active area defined in a bit line direction and a word line direction, a plurality of floating gates formed in the word line direction, an interlayer polysilicon oxide film formed on a floating gate, a control gate formed on the interlayer polysilicon oxide film, source and drain electrodes disposed between adjacent floating gates in the word line direction, a buried N+ region formed in the semiconductor substrate under the source and drain electrodes, and a metal silicide film formed on an upper surface of the control gate.
This application is a Divisional of U.S. patent application Ser. No. 11/319,484, filed Dec. 29, 2005 and claims the benefit of Korean Patent Application No. 10-2004-0116742, filed on Dec. 30, 2004, both of which are hereby incorporated by reference for all purposes as if fully set forth herein.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to a flash EEPROM device enabling a reduced cell size and to a method for fabricating the same.
2. Discussion of the Related Art
Read-only memory (ROM) devices are generally non-volatile memory devices and include programmable ROM (PROM) devices that are electrically programmed after fabrication, mounting, and packaging. In an erasable/programmable ROM (EPROM) device, the programmed data can be erased using ultraviolet light, and in an electrically erasable PROM (EEPROM) device, the programmed data can be erased electrically. A flash memory device, which may be constructed as a NAND or NOR device, is a volatile memory device enabling multiple data rewrite operations electrically.
The programming and erasing of a flash memory device is performed by charging and discharging a floating gate using, for example, channel hot electron injection and Fowler-Nordheim tunneling. In the programming of a memory cell of a flash memory device, such as, a memory cell transistor, a high voltage is applied to the control gate to inject, into the floating gate, electrons from a substrate region near a drain of a memory cell. The transistor's threshold voltage is thereby raised as the injected electrons accumulate in the floating gate. Programming occurs when a predetermined amount of accumulation is reached, such that a logic “1” or a logic “0” is stored in the cell, which can be read by detecting a source-drain current.
After repeated write/erase cycles, the reliability of a flash memory cell becomes degraded over time, and generally deteriorates more quickly in NOR flash devices, according to a deterioration of a tunneling oxide, i.e., a silicon oxide film formed on a source/drain diffusion layer. The deterioration is specifically due to the flow of tunnel current during charging and discharging. In generating tunnel current, a high-voltage electric field (e.g., greater than 8 MV/cm) is applied across the silicon oxide film, creating electron-hole traps in the film and thus facilitating leakage current through the film. This is particularly problematic for a silicon oxide film of 10 nm or thinner.
Due to a limitation in a design rule, however, there is a limitation in reducing the size of the cell or layout area. The design rule is limited by the bit line contact with the source/drain regions 18. Cell-to-cell isolation requires a device isolation film, which may be formed by shallow-trench isolation or local oxidation of silicon. The device isolation film requires a finite dimension to prevent punch-through, which represents another impediment to cell size reduction. Here, the size of the device isolation film is in general greater than the gate-to-gate design rule.
SUMMARY OF THE INVENTIONAccordingly, the present invention is directed to a flash EEPROM device and a method for fabricating the same that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An advantage of the present invention is to provide a flash EEPROM device and a method for fabricating the same, by which a reduced cell size is enabled.
Another advantage of the present invention is to provide a flash EEPROM device and a method for fabricating the same, which minimizes a design rule between a contact and a gate by eliminating a bit line contact area.
Additional features and advantages of the invention will be set forth in the description which follows, and will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure and method particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a flash EEPROM device comprises a semiconductor substrate having an active area defined in a bit line direction and a word line direction, a plurality of floating gates formed on the active area of the semiconductor substrate in the word line direction, an interlayer polysilicon oxide film formed on at least one of the plurality of floating gates, a control gate formed on the interlayer polysilicon oxide film, source and drain electrodes disposed between adjacent floating gates in the word line direction, a buried N+ region formed in the semiconductor substrate under the source and drain electrodes, and a metal silicide film formed on an upper surface of the control gate.
According to another aspect of the present invention, a method for fabricating a flash EEPROM device includes forming a tunneling oxide film on an active region of a semiconductor substrate defined in a bit line direction and a word line direction, forming a first conductive layer and a first insulating film on the tunneling oxide film, selectively patterning the first insulating film and the first conductive layer formed in the word line direction, forming sidewall spacers at opposite sides of the first insulating film and the patterned first conductive layer, forming a buried N+ region in an exposed surface of the semiconductor substrate, forming a second conductive layer on an entire surface of the semiconductor substrate by a planarizing process, to form source and drain electrodes on the buried N+ region, removing the first insulating film and forming a second insulating film on a surface of the source and drain electrodes, sequentially forming an interlayer polysilicon oxide film and a third conductive layer on an entire surface of the semiconductor substrate, forming a control gate and a floating gate by selectively patterning the third conductive layer, the interlayer polysilicon oxide film, and the first conductive layer formed in the bit line direction of the semiconductor substrate, forming a third insulating film on an entire surface of the semiconductor substrate by planarizing an entire surface of the semiconductor surface until the control gate is reached; and forming a metal silicide film on a surface of the floating gate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, like reference designations will be used throughout the drawings to refer to the same or similar parts.
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According to the flash EEPROM and method for fabricating the same, the electrodes at the drain/source regions enable a lower active resistance. Thus, a high-density NOR flash device may be enabled without bit line contacts by commonly forming drain contacts in the NOR cells. The formation of common drain lines and source lines enables the cell formation in a word line direction and in the bit line contact direction of the device shown in
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
Claims
1. A flash EEPROM device, comprising:
- a semiconductor substrate having an active area defined in a bit line direction and a word line direction;
- a plurality of floating gates formed on the active area of said semiconductor substrate in the word line direction;
- an interlayer polysilicon oxide film formed on said at least one of the plurality of floating gates;
- a control gate formed on said interlayer polysilicon oxide film;
- source and drain electrodes disposed between adjacent floating gates in the word line direction;
- a buried N+ region formed in said semiconductor substrate under said source and drain electrodes; and
- a metal silicide film formed on an upper surface of said control gate.
2. The flash EEPROM device of claim 1, further comprising:
- a gate insulating film formed on an upper surface of said source and drain electrodes.
3. The flash EEPROM device of claim 2, wherein said control gate is formed on said at least one of the plurality of floating gates and on said source and drain electrodes in the word line direction of said semiconductor substrate.
4. The flash EEPROM device of claim 3, wherein said gate insulating film is disposed between said control gate and said source and drain electrodes.
5. The flash EEPROM device of claim 1, further comprising:
- a tunneling oxide film formed on said semiconductor substrate to be disposed under said at least one of the plurality of floating gates.
6. The flash EEPROM device of claim 1, further comprising:
- sidewall spacers disposed at opposite sides of said at least one of the plurality of floating gates.
7-12. (canceled)
13. The device of claim 6, wherein the control gate is formed between the sidewall spacers.
14. The device of claim 6, wherein the interlayer polysilicon oxide film is formed between the sidewall spacers.
15. The device of claim 6, wherein the interlayer polysilicon oxide film is formed between the sidewall spacers and the control gate is formed on the interlayer polysilicon oxide film between the sidewall spacers.
Type: Application
Filed: Jul 31, 2008
Publication Date: Mar 19, 2009
Inventor: Heung Jin Kim (Eumseong-gun)
Application Number: 12/222,060
International Classification: H01L 29/788 (20060101);