With Thin Insulator Region For Charging Or Discharging Floating Electrode By Quantum Mechanical Tunneling Patents (Class 257/321)
  • Patent number: 11393917
    Abstract: An object is to provide a high reliability thin film transistor using an oxide semiconductor layer which has stable electric characteristics. In the thin film transistor in which an oxide semiconductor layer is used, the amount of change in threshold voltage of the thin film transistor before and after a BT test is made to be 2 V or less, preferably 1.5 V or less, more preferably 1 V or less, whereby the semiconductor device which has high reliability and stable electric characteristics can be manufactured. In particular, in a display device which is one embodiment of the semiconductor device, a malfunction such as display unevenness due to change in threshold voltage can be reduced.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: July 19, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takahiro Tsuji, Kunihiko Suzuki
  • Patent number: 11355185
    Abstract: A semiconductor device that has a silicon-oxide-nitride-oxide-silicon (SONOS) based non-volatile memory (NVM) array including charge-trapping memory cells arranged in rows and columns and configured to store one of N×analog values. Each charge-trapping memory cells may include a memory transistor including an angled lightly doped drain (LDD) implant extends at least partly under an oxide-nitride-oxide (ONO) layer of the memory transistor. The ONO layer disposed within the memory transistor and over an adjacent isolation structure has the same elevation substantially.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: June 7, 2022
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Venkatraman Prabhakar, Vineet Agrawal, Long Hinh, Santanu Kumar Samanta, Ravindra Kapre
  • Patent number: 11322516
    Abstract: Microelectronic devices include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of pillars extends through the stack structure. At least one isolation structure extends through an upper stack portion of the stack structure. The at least one isolation structure protrudes into pillars of neighboring columns of pillars of the series of pillars. Conductive contacts are in electrical communication with the pillars into which the at least one isolation structure protrudes. Related methods and electronic systems are also disclosed.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: May 3, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Matthew J. King, David A. Daycock, Yoshiaki Fukuzumi, Albert Fayrushin, Richard J. Hill, Chandra S. Tiwari, Jun Fujiki
  • Patent number: 11296102
    Abstract: Disclosed is a three-dimensional semiconductor memory device including a substrate including a cell array region and a connection region, a stack including first and second stacks sequentially stacked on the substrate, the stack having a staircase structure on the connection region, each of the first and second stacks including conductive patterns vertically stacked on the substrate, and contact plugs disposed on the connection region and respectively coupled to the conductive patterns. A bottom surface of each contact plug is located between top and bottom surfaces of a corresponding conductive pattern. In each stack, a recess depth of each contact plug varies monotonically in a stacking direction of the conductive patterns, when measured from a top surface of a corresponding conductive pattern. The contact plugs coupled to an uppermost conductive pattern of the first stack and a lowermost conductive pattern of the second stack have discrete recess depths.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: April 5, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Hwang, Woosung Yang, Joon-Sung Lim, Jiyoung Kim, Jiwon Kim
  • Patent number: 11282844
    Abstract: An erasable programmable non-volatile memory includes a first select transistor, a first floating gate transistor, a second select transistor and a second floating gate transistor. A select gate and a first source/drain terminal of the first select transistor receive a first select gate voltage and a first source line voltage, respectively. A first source/drain terminal and a second source/drain terminal of the first floating gate transistor are connected with a second source/drain terminal of the first select transistor and a first bit line voltage, respectively. A select gate and a first source/drain terminal of the second select transistor receive a second select gate voltage and a second source line voltage, respectively. A first source/drain terminal and a second source/drain terminal of the second floating gate transistor are connected with the second source/drain terminal of the second select transistor and a second bit line voltage, respectively.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: March 22, 2022
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chia-Jung Hsu, Wein-Town Sun
  • Patent number: 11257916
    Abstract: Systems and methods of the disclosed embodiments include an electronic device that has a gate electrode for supplying a gate voltage, a source, a drain, and a channel doped to enable a current to flow from the drain to the source when a voltage is applied to the gate electrode. The electronic device may also include a gate insulator between the channel and the gate electrode. The gate insulator may include a first gate insulator section including a first thickness, and a second gate insulator section including a second thickness that is less than the first thickness. The gate insulator sections thereby improve the safe operating area by enabling the current to flow through the second gate insulator section at a lower voltage than the first gate insulator section.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: February 22, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Balaji Padmanabhan, Prasad Venkatraman, Zia Hossain, Donald Zaremba, Gordon M. Grivna, Alexander Young
  • Patent number: 11239253
    Abstract: A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a first single crystalline semiconductor layer, and memory stack structures extending through the alternating stack and containing respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die includes a peripheral circuitry.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: February 1, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Adarsh Rajashekhar, Raghuveer S. Makala, Fei Zhou
  • Patent number: 11222901
    Abstract: A semiconductor device includes a semiconductor layer, a charge storage layer provided on a surface of the semiconductor layer via a tunnel insulating film, and an electrode layer provided on a surface of the charge storage layer via a block insulating film. The tunnel insulating film includes a plurality of first silicon oxynitride films which are provided between the semiconductor layer and the charge storage layer. The tunnel insulating film further includes a silicon oxide film provided between the first silicon oxynitride films and/or a second silicon oxynitride film which is provided between the first silicon oxynitride films and has an oxygen concentration higher than an oxygen concentration in the first silicon oxynitride film.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: January 11, 2022
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Masaki Noguchi
  • Patent number: 11211297
    Abstract: Bridging testing method between adjacent semiconductor devices includes forming patterned diffusion region on semiconductor substrate, and forming first conductive layer over diffusion region. First conductive layer is patterned in same pattern as patterned diffusion region. Second conductive layer formed extending in first direction over first conductive layer. Second conductive layer is patterned to form opening extending in first direction in central region of second conductive layer exposing portion of first conductive layer. First conductive layer exposed portion is removed exposing portion of diffusion region. Source/drain region is formed over exposed portion of diffusion region, and dielectric layer is formed over source/drain region. Third conductive layer is formed over dielectric layer. End portions along first direction of second conductive layer removed to expose first and second end portions of first conductive layer.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: December 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Chia-Lin Liang, Chih-Ren Hsieh
  • Patent number: 11177269
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. First charge-blocking material is formed to extend elevationally along the vertically-alternating tiers. The first charge-blocking material has k of at least 7.0 and comprises a metal oxide. A second charge-blocking material is formed laterally inward of the first charge-blocking material. The second charge-blocking material has k less than 7.0. Storage material is formed laterally inward of the second charge-blocking material. Insulative charge-passage material is formed laterally inward of the storage material. Channel material is formed to extend elevationally along the insulative tiers and the wordline tiers laterally inward of the insulative charge-passage material. Structure embodiments are disclosed.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: November 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Bharat Bhushan, Chris M. Carlson, Collin Howder
  • Patent number: 11172576
    Abstract: A method for producing a printed circuit board structure comprising at least one insulation layer, at least one conductor layer, and at least one embedded component having a contact pad that has an outer barrier layer, in which structure at least two conductor paths/conductor layer are connected to at least two connections using vias, and each via runs from a conductor path/conductor layer directly to the barrier contact layer of the corresponding connection of the component.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: November 9, 2021
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Johannes Stahr, Mike Morianz
  • Patent number: 11127751
    Abstract: Back gates and related apparatuses, systems, and methods are disclosed. An apparatus includes a channel material including a first side and a second side opposite the first side. The apparatus also includes word lines comprising electrically conductive material spaced along the first side of the channel material. The apparatus further includes a back gate comprising electrically conductive material proximate to the second side of the channel material. A method includes biasing a bit line and a word line associated with a memory cell according to a memory operation, and biasing the back gate while biasing the bit line and the word line.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: September 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Andrew Bicksler, Marc Aoulaiche, Albert Fayrushin
  • Patent number: 11127655
    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. At least one dielectric material portion is formed over the substrate adjacent to the alternating stack. Memory stack structures are formed through the alternating stack. A trench extending through the alternating stack and a via cavity extending through the at least one dielectric material portion are formed using a same anisotropic etch process. The via cavity is deeper than the trench and the via cavity extends into an upper portion of the substrate. The sacrificial material layers are replaced with electrically conductive layers using the trench as a conduit for an etchant and a reactant. A trench fill structure is formed in the trench, and a via structure assembly is formed in the via cavity using simultaneous deposition of material portions. A bonding pad may be formed on the bottom surface of the via structure assembly.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: September 21, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Takumi Moriyama, Hiroshi Sasaki, Yohei Masamori, Satoshi Shimizu
  • Patent number: 11127830
    Abstract: Apparatus (e.g., semiconductor devices) include stack structures with at least one conductive region and at least one nonconductive material. A multidielectric spacer is adjacent the at least one conductive region and comprises first and second dielectric materials. The first dielectric material, adjacent the at least one conductive region, includes silicon and nitrogen. The second dielectric material, adjacent the first dielectric material, comprises silicon-carbon bonds and defines a substantially straight, vertical, outer sidewall. In methods to form such apparatus, the first dielectric material may be formed with selectivity on the at least one conductive region, and the second dielectric material may be formulated and formed to exhibit etch resistance.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: September 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: John A. Smythe, Silvia Borsari, Francois H. Fabreguette, Sutharsan Ketharanathan
  • Patent number: 11121223
    Abstract: Field-effect transistors, and apparatus including such field-effect transistors, including a gate dielectric overlying a semiconductor and a control gate overlying the gate dielectric. The control gate might include an instance of a first polycrystalline silicon-containing material containing polycrystalline silicon, and an instance of a second polycrystalline silicon-containing material containing polycrystalline silicon-germanium or polycrystalline silicon-germanium-carbon.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Haitao Liu, Chandra Mouli
  • Patent number: 11107825
    Abstract: The present disclosure relates to a flash memory structure. The flash memory structure includes a first doped region and a second doped region disposed within a substrate. A select gate is disposed over the substrate between the first doped region and the second doped region. A floating gate is disposed over the substrate between the select gate and the first doped region, and a control gate is over the floating gate. The floating gate extends along multiple surfaces of the substrate.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Shu Huang, Ming Chyi Liu
  • Patent number: 11107833
    Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: August 31, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changhyun Lee, Chanjin Park, Byoungkeun Son, Sung-Il Chang
  • Patent number: 11094705
    Abstract: A method of forming polysilicon comprises forming a first polysilicon-comprising material over a substrate, with the first polysilicon-comprising material comprising at least one of elemental carbon and elemental nitrogen at a total of 0.1 to 20 atomic percent. A second polysilicon-comprising material is formed over the first polysilicon-comprising material. The second polysilicon-comprising material comprises less, if any, total elemental carbon and elemental nitrogen than the first polysilicon-comprising material. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: August 17, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Dimitrios Pavlopoulos, Kunal Shrotri, Anish A. Khandekar
  • Patent number: 11056495
    Abstract: A structure of memory device includes trench isolation lines in a substrate, extending along a first direction. An active region in the substrate is between adjacent two of the trench isolation lines. A dielectric layer is disposed on the active region of the substrate. A floating gate corresponding to a memory cell is disposed on the dielectric layer between adjacent two of the trench isolation lines. The floating gate has a first protruding structure at a sidewall extending along the first direction. A first insulating layer crosses over the floating gate and the trench isolation lines. A control gate line is disposed on the first insulating layer over the floating gate, extending along a second direction intersecting with the first direction. The control gate line has a second protruding structure correspondingly stacked over the first protruding structure of the floating gate.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: July 6, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Liang Yi, Zhiguo Li, Chi Ren, Qiuji Zhao, Boon Keat Toh
  • Patent number: 11049866
    Abstract: Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of dielectric/sacrificial layer pairs is formed on a substrate. A channel structure extending vertically through the dielectric stack is formed. A first opening extending vertically through the dielectric stack is formed. A spacer is formed on a sidewall of the first opening. A TAC extending vertically through the dielectric stack is formed by depositing a conductor layer in contact with the spacer in the first opening. A slit extending vertically through the dielectric stack is formed after forming the TAC. A memory stack including a plurality of conductor/dielectric layer pairs is formed on the substrate by replacing, through the slit, the sacrificial layers in the dielectric/sacrificial layer pairs with a plurality of conductor layers.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: June 29, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Mei Lan Guo, Yushi Hu, Ji Xia, Hongbin Zhu
  • Patent number: 11031413
    Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming multiple hybrid shallow trench isolation structures in a substrate; forming an alternating dielectric stack on the substrate, the alternating dielectric stack including multiple dielectric layer pairs each comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming multiple channel structures in the alternating dielectric stack; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction to divide the multiple channel structures and to expose a row of hybrid shallow trench isolation structures; replacing the second dielectric layers in the alternating dielectric stack with multiple gate structures through the slit; forming a spacer wall to fill the slit; and forming multiple array common source contacts each in electric contact with a corresponding hybrid shallow trench isolation structure.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: June 8, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Li Hong Xiao, Zongliang Huo
  • Patent number: 11011539
    Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a 3D memory device includes a substrate, a first single-crystal silicon layer above the substrate, a first memory stack above the first single-crystal silicon layer, a first channel structure extending vertically through the first memory stack, and a first interconnect layer above the first memory stack. The first memory stack includes a first plurality of interleaved conductor layers and dielectric layers. The first channel structure includes a first lower plug extending into the first single-crystal silicon layer and including single-crystal silicon. The first interconnect layer includes a first bit line electrically connected to the first channel structure.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: May 18, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Li Hong Xiao
  • Patent number: 10985251
    Abstract: Various embodiments include apparatuses and methods of forming the same. One such apparatus can include a first dielectric material and a second dielectric material, and a conductive material between the first dielectric material and the second dielectric material. A charge storage element, such as a floating gate or charge trap, is between the first dielectric material and the second dielectric material and adjacent to the conductive material. The charge storage element has a first surface and a second surface. The first and second surfaces are substantially separated from the first dielectric material and the second dielectric material, respectively, by a first air gap and a second air gap. Additional apparatuses and methods are disclosed.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: April 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Minsoo Lee, Akira Goda
  • Patent number: 10950498
    Abstract: Methods of dep-etch in semiconductor devices (e.g. V-NAND) are described. A metal layer is deposited in a feature. The metal layer is removed by low temperature atomic layer etching by oxidizing the surface of the metal layer and etching the oxide in a layer-by-layer fashion. After removal of the metal layer, the features are filled with a metal.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: March 16, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Susmit Singha Roy, Srinivas Gandikota, Pramit Manna, Abhijit Basu Mallick
  • Patent number: 10930767
    Abstract: FinFET patterning methods are disclosed for achieving fin width uniformity. An exemplary method includes forming a mandrel layer over a substrate. A first cut removes a portion of the mandrel layer, leaving a mandrel feature disposed directly adjacent to a dummy mandrel feature. The substrate is etched using the mandrel feature and the dummy mandrel feature as an etch mask, forming a dummy fin feature and an active fin feature separated by a first spacing along a first direction. A second cut removes a portion of the dummy fin feature and a portion of the active fin feature, forming dummy fins separated by a second spacing and active fins separated by the second spacing. The second spacing is along a second direction substantially perpendicular to the first direction. A third cut removes the dummy fins, forming fin openings, which are filled with a dielectric material to form dielectric fins.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 10930749
    Abstract: Semiconductor devices are provided. A semiconductor device includes a channel region that protrudes from a substrate. The semiconductor device includes a gate line on the channel region. Moreover, the semiconductor device includes a gate isolation layer that is between a first portion of the gate line and a second portion of the gate line. The gate isolation layer is in contact with the gate line and includes a gap that is in the gate isolation layer. Related methods of manufacturing a semiconductor device are also provided.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: February 23, 2021
    Inventors: Yong Ho Jeon, Jung Hyun Kim, Sung Woo Myung, Young Mook Oh, Dong Seok Lee
  • Patent number: 10930760
    Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with a strained channel, including forming one or more vertical fins on a substrate, forming a sacrificial stressor layer adjacent to the one or more vertical fins, wherein the sacrificial stressor layer imparts a strain in the adjacent vertical fins, forming a fin trench through one or more vertical fins and the sacrificial stressor layer to form a plurality of fin segments and a plurality of sacrificial stressor layer blocks, forming an anchor wall adjacent to and in contact with one or more fin segment endwalls, and removing at least one of the plurality of the sacrificial stressor layer blocks, wherein the anchor wall maintains the strain of the adjacent fin segments after removal of the sacrificial stressor layer blocks adjacent to the fin segment with the adjacent anchor wall.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: February 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li
  • Patent number: 10916564
    Abstract: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: David Ross Economy, John Mark Meldrim, Haoyu Li, Yongjun Jeff Hu, Christopher W. Petz, Daniel Billingsley, Everett A. McTeer
  • Patent number: 10903232
    Abstract: Laterally alternating sequences of memory opening fill structures and isolation dielectric pillars are formed between alternating stacks of insulating layers and sacrificial material layers. Each of the memory opening fill structures includes, from inside to outside, a vertical semiconductor channel, a tunneling dielectric layer, and an aluminum oxide liner. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers. Discrete silicon nitride portions are formed on physically exposed surfaces of the aluminum oxide liners employing a selective silicon nitride deposition process, and are employed as charge storage elements. Electrically conductive layers are formed in remaining volumes of the backside recesses. The silicon nitride portions are formed as a pair of discrete silicon nitride portions at each level of the electrically conductive layers within each memory opening fill structure.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: January 26, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Masanori Tsutsumi
  • Patent number: 10861570
    Abstract: A memory device and an operating method of the memory device is disclosed. The memory device includes a memory cell array including a plurality of memory blocks. The memory device further includes a peripheral circuit for performing an erase voltage application operation, a first erase verify operation, and a second erase verify operation on a selected memory block among the plurality of memory blocks. The memory device also includes a control logic for setting a start erase voltage of an erase operation, based on a result of the first erase verify operation, and controlling the peripheral circuit to perform the second erase verify operation when it is determined that the first erase verify operation on the selected memory block has been passed.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: December 8, 2020
    Assignee: SK hynix Inc.
    Inventors: Yong Han, Jun Hyuk Lee
  • Patent number: 10854623
    Abstract: A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: December 1, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jang Hyun You, Jin Taek Park, Taek Soo Shin, Sung Yun Lee
  • Patent number: 10833191
    Abstract: Embodiments of the invention are directed to methods of fabricating devices on a substrate. A non-limiting example of the method includes performing memory fabrication operations to form a non-volatile memory device in a first region of the substrate, wherein the memory fabrication operations include forming a first region of a nanosheet stack over the first region of the substrate. The first region of the nanosheet stack includes nanosheet layers of a first type of semiconductor material alternating with nanosheet layers of a second type of semiconductor material. A first portion of the first region of the nanosheet stack is replaced with a control gate of the non-volatile memory device, and a charge trapping region of the non-volatile memory device is provided under the control gate.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Julien Frougier, Ruilong Xie, Kangguo Cheng, Juntao Li
  • Patent number: 10790300
    Abstract: A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate including a single crystalline substrate semiconductor material, and memory stack structures extending through the alternating stack and containing a respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die contains a peripheral circuitry.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: September 29, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Adarsh Rajashekhar, Raghuveer S. Makala, Fei Zhou, Rahul Sharangpani
  • Patent number: 10790303
    Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels include conductive wordline material having terminal ends. Charge blocking material is along the terminal ends of the conductive wordline material and has first vertical faces. The insulative levels have terminal ends with second vertical faces. The second vertical faces are laterally offset relative to the first vertical faces. Charge-trapping material is along the first vertical faces, and extends partially along the second vertical faces. The charge-trapping material is configured as segments which are vertically spaced from one another by gaps. Charge-tunneling material extends along the segments of the charge-trapping material. Channel material extends vertically along the stack, and is spaced from the charge-trapping material by the charge-tunneling material. The channel material extends into the gaps. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: September 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Woohee Kim, John D. Hopkins, Changhan Kim
  • Patent number: 10790396
    Abstract: A semiconductor device of an embodiment includes a first electrode; a second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode and extending in a first direction; a gate electrode surrounding the oxide semiconductor layer; and a first gate insulating layer provided between the gate electrode and the oxide semiconductor layer, the first gate insulating layer surrounding the oxide semiconductor layer, and the first gate insulating layer having a length in the first direction shorter than a length of the oxide semiconductor layer in the first direction.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: September 29, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoaki Sawabe, Tomomasa Ueda, Keiji Ikeda, Tsutomu Tezuka, Nobuyoshi Saito
  • Patent number: 10784356
    Abstract: A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third gate oxide of a third thickness, in which the first thickness is greater than the second thickness and the second thickness is greater than the third thickness.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: September 22, 2020
    Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.
    Inventors: Krishnaswamy Ramkumar, Igor Kouznetsov, Venkatraman Prabhakar, Ali Keshavarzi
  • Patent number: 10770472
    Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends along the stack. Conductive segments are along the wordline levels. Each of the conductive segments has, along a cross-section, first and second ends in opposing relation to one another. The conductive segments include gates and wordlines adjacent the gates. The wordlines encompass the second ends, and the gates have rounded (e.g., substantially parabolic) noses which encompass the first ends. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: September 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Changhan Kim, Gianpietro Carnevale
  • Patent number: 10756106
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing word lines and drain select gate electrodes located over a substrate, and memory stack structures containing a respective vertical semiconductor channel and a memory film including a tunneling dielectric and a charge storage layer. A first portion of a first charge storage layer located in a first memory stack structure at level of a first drain select gate electrode is thicker than a first portion of a second charge storage layer located in a second memory stack structure at the level of the first drain select electrode.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: August 25, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masatoshi Nishikawa, Michiaki Sano, Ken Oowada, Zhixin Cui
  • Patent number: 10734292
    Abstract: Bridging testing method between adjacent semiconductor devices includes forming patterned diffusion region on semiconductor substrate, and forming first conductive layer over diffusion region. First conductive layer is patterned in same pattern as patterned diffusion region. Second conductive layer formed extending in first direction over first conductive layer. Second conductive layer is patterned to form opening extending in first direction in central region of second conductive layer exposing portion of first conductive layer. First conductive layer exposed portion is removed exposing portion of diffusion region. Source/drain region is formed over exposed portion of diffusion region, and dielectric layer is formed over source/drain region. Third conductive layer is formed over dielectric layer. End portions along first direction of second conductive layer removed to expose first and second end portions of first conductive layer.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Han Lin, Chia-Lin Liang, Chih-Ren Hsieh
  • Patent number: 10727241
    Abstract: Techniques are disclosed for forming three-dimensional (3D) NAND structures including group III-nitride (III-N) material channels. Typically, polycrystalline silicon (poly-Si) channels are used for 3D NAND structures, such as 3D NAND flash memory devices. However, using III-N channel material for 3D NAND structures offers numerous benefits over poly-Si channel material, such as relatively lower resistance in the channel, relatively higher current densities, and relatively lower leakage. Therefore, using III-N channel material enables an increased number of floating gates or storage cells to be stacked in 3D NAND structures, thereby leading to increased capacity for a given integrated circuit footprint (e.g., increased GB/cm2). For instance, use of III-N channel material can enable greater than 100 floating gates for a 3D NAND structure. Other embodiments may be described and/or disclosed.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Prashant Majhi, Han Wui Then, Marko Radosavljevic
  • Patent number: 10727239
    Abstract: An EEPROM memory integrated circuit includes memory cells arranged in a memory plane. Each memory cell includes an access transistor in series with a state transistor. Each access transistor is coupled, via its source region, to the corresponding source line and each state transistor is coupled, via its drain region, to the corresponding bit line. The floating gate of each state transistor rests on a dielectric layer having a first part with a first thickness, and a second part with a second thickness that is less than the first thickness. The second part is located on the source side of the state transistor.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: July 28, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: François Tailliet
  • Patent number: 10707225
    Abstract: A method for fabricating a semiconductor memory device is disclosed. A substrate having a main surface is provided. A memory gate is formed on the main surface of the substrate. The memory has a first sidewall and a second sidewall opposite to the first sidewall. A control gate is formed in proximity to the memory gate. The control gate has a third sidewall directly facing the second sidewall, and a fourth sidewall opposite to the third sidewall. A gap is formed between the second sidewall of the memory gate and the third sidewall of the control gate. A first single spacer structure is formed on the first sidewall of the memory gate and a second single spacer structure on the fourth sidewall of the control gate. A gap-filling layer is formed to fill up the gap.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: July 7, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Patent number: 10700091
    Abstract: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: June 30, 2020
    Assignee: Micron Technology, Inc.
    Inventors: David Ross Economy, John Mark Meldrim, Haoyu Li, Yongjun Jeff Hu, Christopher W. Petz, Daniel Billingsley, Everett A. McTeer
  • Patent number: 10700128
    Abstract: An example three-dimensional (3-D) memory array includes a substrate material including a plurality of conductive contacts arranged in a staggered pattern and a plurality of planes of a conductive material separated from one another by a first insulation material formed on the substrate material. Each of the plurality of planes of the conductive material includes a plurality of recesses formed therein. A second insulation material is formed in a serpentine shape through the insulation material and the conductive material. A plurality of conductive pillars are arranged to extend substantially perpendicular to the plurality of planes of the conductive material and the substrate and each respective conductive pillar is coupled to a different respective one of the conductive contacts. A chalcogenide material is formed in the plurality of recesses such that the chalcogenide material in each respective recess is formed partially around one of the plurality of conductive pillars.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: June 30, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Fantini, Lorenzo Fratin
  • Patent number: 10651282
    Abstract: Various embodiments include apparatuses and methods of forming the same. One such apparatus can include a first dielectric material and a second dielectric material, and a conductive material between the first dielectric material and the second dielectric material. A charge storage element, such as a floating gate or charge trap, is between the first dielectric material and the second dielectric material and adjacent to the conductive material. The charge storage element has a first surface and a second surface. The first and second surfaces are substantially separated from the first dielectric material and the second dielectric material, respectively, by a first air gap and a second air gap. Additional apparatuses and methods are disclosed.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: May 12, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Minsoo Lee, Akira Goda
  • Patent number: 10629752
    Abstract: Gate all-around devices are disclosed in which an angled channel including a semiconducting nanostructure is located between a source and a drain. The angled channel has an axis that is oriented at an angle to the top surface of the substrate at an angle in a range of about 1° to less than about 90°. The gate all-around device is intended to meet design and performance criteria for the 7 nm technology generation.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: April 21, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Russell Chin Yee Teo, Benjamin Colombeau
  • Patent number: 10600802
    Abstract: A first alternating stack of first insulating layers and first spacer layers, an inter-tier dielectric layer, a sacrificial memory opening fill structure, and a second alternating stack of second insulating layers and second spacer layers are formed over a substrate. The spacer layers are formed as, or are subsequently replaced with, electrically conductive layers. A concave downward-facing surface of the inter-tier dielectric layer is formed on a convex upper surface of the sacrificial memory opening fill structure. An inter-tier memory opening is provided by forming second-tier memory opening and removing the sacrificial memory opening fill structure. A memory stack structure including a memory film is formed in the inter-tier memory opening. The memory film includes a rounded top surface at the joint between tiers to enhance its reliability.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: March 24, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Tadashi Nakamura, Kota Funayama
  • Patent number: 10593695
    Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels include conductive wordline material having terminal ends. Charge blocking material is along the terminal ends of the conductive wordline material and has first vertical faces. The insulative levels have terminal ends with second vertical faces. The second vertical faces are laterally offset relative to the first vertical faces. Charge-trapping material is along the first vertical faces, and extends partially along the second vertical faces. The charge-trapping material is configured as segments which are vertically spaced from one another by gaps. Charge-tunneling material extends along the segments of the charge-trapping material. Channel material extends vertically along the stack, and is spaced from the charge-trapping material by the charge-tunneling material. The channel material extends into the gaps. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: March 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Woohee Kim, John D. Hopkins, Changhan Kim
  • Patent number: 10586802
    Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so that the portion is doped differently than the remaining semiconductor material in the tier. At least substantially all of the remaining semiconductor material of the tier is removed, leaving the differently doped portion of the tier of semiconductor material as a charge storage structure. A tunneling dielectric is formed on a first surface of the charge storage structure and an intergate dielectric is formed on a second surface of the charge storage structure. Additional embodiments are also described.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: March 10, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, John K. Zahurak
  • Patent number: 10566053
    Abstract: Memory cells programmed via multi-mechanism charge transports are described herein. An example apparatus includes a semiconductor material, a tunneling material formed on the semiconductor material, a charge trapping material formed on the tunneling material, a charge blocking material formed on the charge trapping material, and a metal gate formed on the charge blocking material. The charge trapping material comprises gallium nitride (GaN), and the memory cell is programmed to the target state via the multi-mechanism charge transport such that charges are simultaneously transported to the charge trapping material through a plurality of different channels.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: February 18, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya