Electrically Programmable (eprom), I.e., Floating Gate Memory Structures (epo) Patents (Class 257/E21.68)
  • Patent number: 11394296
    Abstract: A voltage driver can be operated to power an electrowetting lens of an eye-implantable or eye-mountable device. The voltage driver includes a first charge pump that outputs a first voltage having a first polarity and a second charge pump that outputs a second voltage having a second polarity, where the second polarity is an opposite polarity of the first polarity. The voltage driver can be operated to charge the electrowetting lens by coupling the first charge pump to the electrowetting lens and, after charging the electrowetting lens, discharge the electrowetting lens by coupling the second charge pump to the electrowetting lens. In operation, charging and discharging the electrowetting lens adjusts an optical power of the electrowetting lens and can thus adjust an optical power available for vision when the electrowetting lens is implanted in or mounted on an eye.
    Type: Grant
    Filed: September 29, 2018
    Date of Patent: July 19, 2022
    Assignee: Verily Life Sciences LLC
    Inventor: Shungneng Lee
  • Patent number: 11056175
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate, word lines and bit lines. The semiconductor substrate has active regions separated from one another and extending along a first direction. The word lines are formed in the semiconductor substrate. The active regions are respectively intersected with one or more of the word lines. The word lines respectively have thick portions and a narrow portion continuously extending on the thick portions along a second direction. The thick portions are located at where the word lines are intersected with the active regions. The bit lines are formed over the semiconductor substrate, and extending along a third direction intersected with the first and second directions.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: July 6, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Noriaki Ikeda
  • Patent number: 10872650
    Abstract: Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two capacitors. Another example ferroelectric memory cell includes four transistors and two capacitors.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: December 22, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Christopher J. Kawamura
  • Patent number: 10783948
    Abstract: Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two capacitors. Another example ferroelectric memory cell includes four transistors and two capacitors.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: September 22, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Christopher J. Kawamura
  • Patent number: 10297452
    Abstract: One illustrative method disclosed includes selectively forming sacrificial conductive source/drain cap structures on and in contact with first and second source/drain contact structures positioned on opposite sides of a gate of a transistor and removing and replacing the spaced-apart sacrificial conductive source/drain cap structures with first and second separate, laterally spaced-apart insulating source/drain cap structures that are positioned on the first and second source/drain contact structures. The method also includes forming a gate contact opening that extends through a space between the insulating source/drain cap structures and through the gate cap so as to expose a portion of the gate structure and forming a conductive gate contact structure (CB) that is conductively coupled to the gate structure.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: May 21, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Hui Zang, Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10211303
    Abstract: An integrated circuit contains a flash cell in which the top gate of the sense transistor is a metal sense gate over the floating gate. The source/drain regions of the sense transistor extend under the floating gate so that the source region is separated from the drain region by a sense channel length less than 200 nanometers. The floating gate is at least 400 nanometers wide, so the source/drain regions of the sense transistor extend under the floating gate at least 100 nanometers on each side. The integrated circuit is formed by forming the sense transistor source and drain regions before forming the floating gate.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: February 19, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ning Tan, Weidong Tian
  • Patent number: 10115789
    Abstract: A method for forming a non-volatile memory cell is provided. The method comprises: forming a field region with a first impurity type in a semiconductor substrate, the field region having a first impurity concentration; forming a plurality of spaced apart higher concentration regions with the first impurity type within the field region, the higher concentration regions each having a higher concentration than the first impurity concentration; and forming a plurality of floating gate transistors in the field region between the higher concentration regions.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: October 30, 2018
    Assignee: WAFERTECH, LLC
    Inventor: Swen Wang
  • Patent number: 10014308
    Abstract: Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: July 3, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Stephane Zoll, Philippe Garnier
  • Patent number: 9825048
    Abstract: A 3D memory has multiple memory layers stacked on top of a substrate. Word lines in different memory layers are connected respectively to different columns of contact pads in the substrate directly under the multiple memory layers. The connection is accomplished by creating vertical shifts above each contact pad and creating a vertical word line VIA connecting to the contact pad. For a given memory layer and its column of vertical word line VIAs, an auxiliary vertical shaft down to the memory layer is formed between each vertical word line VIA and an adjacent word line. The auxiliary vertical shaft is contiguous with the vertical shift allowing access to the vertical word line VIA. The auxiliary vertical shaft also enables excavating a lateral space between the word line and the vertical word line VIA. Filling the space with a conductive material completes a conductive path from the word line to the contact pad.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: November 21, 2017
    Assignee: SanDisk Technologies LLC
    Inventor: Raul Adrian Cernea
  • Patent number: 9748256
    Abstract: Provided is a semiconductor device including a memory gate structure and a select gate structure. The memory gate structure is closely adjacent to the select gate structure. Besides, an air gap encapsulated by an insulating layer is disposed between the memory gate structure and the select gate structure.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: August 29, 2017
    Assignee: United Microelectronics Corp.
    Inventors: Wei-Chang Liu, Zhen Chen, Shen-De Wang, Wang Xiang, Yi-Shan Chiu, Wei Ta
  • Patent number: 9564449
    Abstract: A semiconductor device is provided, which may include: a well of a first conductivity type located within a substrate of a second conductivity type; a well terminal electrically coupled to the well; a floating gate disposed over the well; a floating gate terminal electrically coupled to the floating gate; a control gate disposed over the floating gate and electrically coupled to the well; and a control gate terminal electrically coupled to the control gate; wherein the floating gate terminal is configured to receive a first voltage; wherein the control gate terminal and the well terminal are configured to receive a second voltage.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: February 7, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Bernd Landgraf
  • Patent number: 9559108
    Abstract: A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: January 31, 2017
    Assignee: INFINEON TECHNOLOGIES DRESDEN GMBH
    Inventors: Robert Strenz, Mayk Roehrich, Wolfram Langheinrich, John Power, Danny Shum, Martin Stiftinger
  • Patent number: 9543516
    Abstract: Methods for producing RRAM resistive switching elements having reduced forming voltage include doping to create oxygen deficiencies in the dielectric film. Oxygen deficiencies in a dielectric film promote formation of conductive pathways.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: January 10, 2017
    Assignees: Intermolecular, Inc., SanDisk 3D LLC, Kabushiki Kaisha Toshiba
    Inventors: Jinhong Tong, Randall Higuchi, Imran Hashim, Vidyut Gopal
  • Patent number: 9401367
    Abstract: An array of floating gate transistors of a non-volatile memory, NVM, cell includes floating gate transistors separated from one another by high-concentration dopant impurity regions and without using shallow trench isolation (STI) or field oxide (FOX) isolation structures. The array is formed over a substrate portion that includes a continuous and planar upper surface. The high-concentration dopant impurity regions are formed in a P-field region and are formed of the same dopant impurity species as the P-field region but of a higher concentration. The floating gate transistors are split-gate floating gate transistors in some embodiments.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: July 26, 2016
    Assignee: WAFERTECH, LLC
    Inventor: Swen Wang
  • Patent number: 9391206
    Abstract: Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with liner material and have segments of semiconductor material exposed along lower regions. Semiconductor material is isotropically etched through the exposed segments which transforms the recesses into openings having wide lower regions beneath narrow upper regions. Gate dielectric material is formed along sidewalls of the openings. Gate material is formed within the openings and over regions of the semiconductor material between the openings. Insulative material is formed down the center of each opening and entirely through the gate material. A segment of gate material extends from one of the openings to the other, and wraps around a pillar of the semiconductor material between the openings. The segment is a gate of a transistor. Source/drain regions are formed on opposing sides of the gate.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: July 12, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Deepak Chandra Pandey, Haitao Liu, Fawad Ahmed, Kamal M. Karda
  • Patent number: 9373391
    Abstract: A resistive memory apparatus is provided. The resistive memory apparatus includes a plurality of memory cell pairs, and each of the memory cell pairs includes an active area, first and second word lines, a source line, first and second resistors and first and second bit lines. The active area is formed on a substrate, and the first and second word lines are formed on the substrate, and intersected with the active area. The source line is formed on the substrate and coupled to the active area. The first and second resistors are disposed on the substrate, and respectively coupled to the active area. The first and second bit lines are formed on the first and second resistors and coupled to the first and second resistors. The first and second bit lines are extended along a first direction which is substantially parallel to the first and second word lines.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: June 21, 2016
    Assignee: Winbond Electronics Corp.
    Inventors: Frederick Chen, Wen-Hsiung Chang, Chien-Min Wu
  • Patent number: 9299854
    Abstract: To enhance the performance of a semiconductor device. In a method for manufacturing a semiconductor device, a metal film is formed over a semiconductor substrate having an insulating film formed on a surface thereof, and then the metal film is removed in a memory cell region, whereas, in a part of a peripheral circuit region, the metal film is left. Next, a silicon film is formed over the semiconductor substrate, then the silicon film is patterned in the memory cell region, and, in the peripheral circuit region, the silicon film is left so that an outer peripheral portion of the remaining metal film is covered with the silicon film. Subsequently, in the peripheral circuit region, the silicon film, the metal film, and the insulating film are patterned for forming an insulating film portion formed of the insulating film, a metal film portion formed of the metal film, and a conductive film portion formed of the silicon film.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: March 29, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yukio Nishida, Tomohiro Yamashita
  • Patent number: 9276008
    Abstract: A process integration is disclosed for fabricating complete, planar non-volatile memory (NVM) cells (110) prior to the formation of high-k metal gate electrodes for CMOS transistors (212, 213) using a planarized dielectric layer (26) and protective mask (28) to enable use of a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: March 1, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jon D. Cheek, Frank K. Baker, Jr.
  • Patent number: 9209244
    Abstract: Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: December 8, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Joo Shim, Han-Soo Kim, Woon-Kyung Lee, Ju-Young Lim, Sung-Min Hwang
  • Patent number: 9035431
    Abstract: A method for fabricating the device includes patterning a first structure and a second structure on a semiconductor device. A first angled ion implantation is applied to the second structure such that the first structure is protected and a second angled ion implantation is applied to the first structure such that the second structure is protected, wherein exposed portions of the first and second structures have an altered rate of oxidation. Oxidation is performed to form thicker or thinner oxide portions on the exposed portions of the first and second structures relative to unexposed portions of the first and second structures. Oxide portions are removed to an underlying layer of the first and second structures. The first and second structures are removed. Spacers are formed about a periphery of remaining oxide portions. The remaining oxide portions are removed. A layer below the spacers is patterned to form integrated circuit features.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Ghavam G. Shahidi
  • Patent number: 8980766
    Abstract: Provided are methods of forming nonvolatile memory elements using atomic layer deposition techniques, in which at least two different layers of a memory element are deposited sequentially and without breaking vacuum in a deposition chamber. This approach may be used to prevent oxidation of various materials used for electrodes without a need for separate oxygen barrier layers. A combination of signal lines and resistive switching layers may be used to cap the electrodes and to minimize their oxidation. As such, fewer layers are needed in a memory element. Furthermore, atomic layer deposition allows more precise control of electrode thicknesses. In some embodiments, a thickness of an electrode may be less than 50 Angstroms. Overall, atomic layer deposition of electrodes and resistive switching layers lead to smaller thicknesses of entire memory elements making them more suitable for low aspect ratio features of advanced nodes.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: March 17, 2015
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Yun Wang, Tony P. Chiang, Tim Minvielle, Takeshi Yamaguchi
  • Patent number: 8969947
    Abstract: A memory device includes a substrate, a semiconductor column extending perpendicularly from the substrate and a plurality of spaced-apart charge storage cells disposed along a sidewall of the semiconductor column. Each of the storage cells includes a tunneling insulating layer disposed on the sidewall of the semiconductor column, a polymer layer disposed on the tunneling insulating layer, a plurality of quantum dots disposed on or in the polymer layer and a blocking insulating layer disposed on the polymer layer.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-goo Lee, Jung-dal Choi, Young-woo Park
  • Patent number: 8962416
    Abstract: A method of making a semiconductor structure uses a substrate having a background doping of a first type. A gate structure has a gate dielectric on the substrate and a select gate layer on the gate dielectric. Implanting is performed into a first portion of the substrate adjacent to a first end with dopants of a second type. The implanting is prior to any dopants being implanted into the background doping of the first portion which becomes a first doped region of the second type. An NVM gate structure has a select gate, a storage layer having a first portion over the first doped region, and a control gate over the storage layer. Implanting at a non-vertical angle with dopants of the first type forms a deep doped region under the select gate. Implanting with dopants of the second type forms a source/drain extension.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: February 24, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Brian A. Winstead, Cheong Min Hong, Sung-Taeg Kang, Konstantin V. Loiko, Jane A. Yater
  • Patent number: 8921175
    Abstract: An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: December 30, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Thierry Coffi Herve Yao, Gregory James Scott
  • Patent number: 8912575
    Abstract: The semiconductor device includes a semiconductor substrate having a first active area defined by a first isolation layer; a gate insulating layer formed on the semiconductor substrate; a first conductive layer formed on the gate insulating layer; a dielectric layer formed on the first conductive layer; at least one first contact hole passing through the dielectric layer; a second conductive layer, formed on the dielectric layer, the second conductive layer filling the at least one first contact hole to contact the first conductive layer; and at least one first contact plug connected to the second conductive layer in the first active area, wherein the at least one first contact plug is offset from the at least one first contact hole to overlap the dielectric layer.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: December 16, 2014
    Assignee: SK Hynix Inc.
    Inventor: Min Gyu Koo
  • Patent number: 8895390
    Abstract: Embodiments of the invention generally relate to memory devices and methods for manufacturing such memory devices. In one embodiment, a method for forming a memory device with a textured electrode is provided and includes forming a silicon oxide layer on a lower electrode disposed on a substrate, forming metallic particles on the silicon oxide layer, wherein the metallic particles are separately disposed from each other on the silicon oxide layer. The method further includes etching between the metallic particles while removing a portion of the silicon oxide layer and forming troughs within the lower electrode, removing the metallic particles and remaining silicon oxide layer by a wet etch process while revealing peaks separated by the troughs disposed on the lower electrode, forming a metal oxide film stack within the troughs and over the peaks of the lower electrode, and forming an upper electrode over the metal oxide film stack.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 25, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Dipankar Pramanik
  • Patent number: 8896049
    Abstract: A manufacturing method of a semiconductor device of the present invention includes the steps of forming a stacked body in which a semiconductor film, a gate insulating film, and a first conductive film are sequentially stacked over a substrate; selectively removing the stacked body to form a plurality of island-shaped stacked bodies; forming an insulating film to cover the plurality of island-shaped stacked bodies; removing a part of the insulating film to expose a surface of the first conductive film, such that a surface of the first conductive film almost coextensive with a height of the insulating film; forming a second conductive film over the first conductive film and a left part of the insulating film; forming a resist over the second conductive film; selectively removing the first conductive film and the second conductive film using the resist as a mask.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: November 25, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Tamae Takano, Yasuyuki Arai, Fumiko Terasawa
  • Patent number: 8883655
    Abstract: Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: November 11, 2014
    Assignees: Intermoecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Yun Wang, Tony P. Chiang, Vidyut Gopal, Imran Hashim, Dipankar Pramanik
  • Patent number: 8872252
    Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatuses that include them. In one such method, a silicide is formed in a tier of silicon, the silicide is removed, and a device is formed at least partially in a void that was occupied by the silicide. One such apparatus includes a tier of silicon with a void between tiers of dielectric material. Residual silicide is on the tier of silicon and/or on the tiers of dielectric material and a device is formed at least partially in the void. Additional embodiments are also described.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Anurag Jindal, Gowri Damarla, Roger W. Lindsay, Eric Blomiley
  • Patent number: 8809205
    Abstract: Provided are methods of forming nonvolatile memory elements using atomic layer deposition techniques, in which at least two different layers of a memory element are deposited sequentially and without breaking vacuum in a deposition chamber. This approach may be used to prevent oxidation of various materials used for electrodes without a need for separate oxygen barrier layers. A combination of signal lines and resistive switching layers may be used to cap the electrodes and to minimize their oxidation. As such, fewer layers are needed in a memory element. Furthermore, atomic layer deposition allows more precise control of electrode thicknesses. In some embodiments, a thickness of an electrode may be less than 50 Angstroms. Overall, atomic layer deposition of electrodes and resistive switching layers lead to smaller thicknesses of entire memory elements making them more suitable for low aspect ratio features of advanced nodes.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 19, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Yun Wang, Tony P. Chiang, Tim Minvielle, Takeshi Yamaguchi
  • Patent number: 8802492
    Abstract: Methods for producing RRAM resistive switching elements having reduced forming voltage include doping to create oxygen deficiencies in the dielectric film. Oxygen deficiencies in a dielectric film promote formation of conductive pathways.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: August 12, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Jinhong Tong, Randall Higuchi, Imran Hashim, Vidyut Gopal
  • Patent number: 8796752
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of strings spaced a first distance from each other, each string including first preliminary gate structures spaced a second distance, smaller than the first distance, between second preliminary gate structures, forming a first insulation layer to cover the first and second preliminary gate structures, forming an insulation layer structure to fill a space between the strings, forming a sacrificial layer pattern to partially fill spaces between first and second preliminary gate structures, removing a portion of the first insulation layer not covered by the sacrificial layer pattern to form a first insulation layer pattern, reacting portions of the first and second preliminary gate structures not covered by the first insulation layer pattern with a conductive layer to form gate structures, and forming a capping layer on the gate structures to form air gaps between the gate structures.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: August 5, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae-Hwang Sim
  • Patent number: 8778761
    Abstract: A semiconductor device fabrication method particularly suitable for the fabrication of a 90 nm embedded flash memory is disclosed. The method includes: forming a dielectric layer having a first thickness over a first device region and forming a dielectric layer having a second thickness different from the first thickness over a second device region, the dielectric layer having a first thickness serving as a tunnel oxide layer of a split-gate structure, the dielectric layer having a second thickness serving as a gate oxide layer of a MOS transistor. The method enables the fabrication of a MOS transistor including a gate oxide layer with a desired thickness.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: July 15, 2014
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Jing Gu, Binghan Li
  • Patent number: 8748249
    Abstract: A vertical structure non-volatile memory device in which a gate dielectric layer is prevented from protruding toward a substrate; a resistance of a ground selection line (GSL) electrode is reduced so that the non-volatile memory device is highly integrated and has improved reliability, and a method of manufacturing the same are provided. The method includes: sequentially forming a polysilicon layer and an insulating layer on a silicon substrate; forming a gate dielectric layer and a channel layer through the polysilicon layer and the insulating layer, the gate dielectric layer and the channel layer extending in a direction perpendicular to the silicon substrate; forming an opening for exposing the silicon substrate, through the insulating layer and the polysilicon layer; removing the polysilicon layer exposed through the opening, by using a halogen-containing reaction gas at a predetermined temperature; and filling a metallic layer in the space formed by removing the polysilicon layer.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: June 10, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-kyu Yang, Ki-hyun Hwang, Phil-ouk Nam, Jae-young Ahn, Han-mei Choi, Dong-chul Yoo
  • Patent number: 8748964
    Abstract: Memory cells including a charge storage structure having a gettering agent therein can be useful for non-volatile memory devices. Providing for gettering of oxygen from a charge-storage material of the charge storage structure can facilitate a mitigation of detrimental oxidation of the charge-storage material.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: June 10, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Rhett T. Brewer, Durai V. Ramaswamy
  • Patent number: 8716809
    Abstract: Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may implement a different custom logic circuit. Custom fabrication masks may be used to hardwire the programmable circuitry to implement a specific custom logic circuit. The programmable circuitry may be hardwired in such a way that signal timing characteristics of a hardened programmable logic device that implements a custom logic circuit may match the signal timing characteristics of a programmable logic device that implements the same custom logic circuit using configuration data.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: May 6, 2014
    Assignee: Altera Corporation
    Inventors: Andy L. Lee, Jeffrey T. Watt
  • Patent number: 8703566
    Abstract: A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: April 22, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Patent number: 8674414
    Abstract: Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: March 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoungkeun Son, Hansoo Kim, Jinho Kim, Kihyun Kim
  • Patent number: 8664059
    Abstract: A method includes forming a shallow trench isolation (STI) region in a substrate; depositing a first material such that the first material overlaps the STI region and a portion of a top surface of the STI region is exposed; etching a recess in the STI region by a first etch, the recess having a bottom and sides; depositing a second material over the first material and on the sides and bottom of the recess in the STI region; and etching the first and second material by a second etch to form a floating gate of the device, wherein the floating gate extends into the recess.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: March 4, 2014
    Assignee: International Business Machines Corporation
    Inventor: Erwan Dornel
  • Patent number: 8633548
    Abstract: A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: January 21, 2014
    Assignee: Microsemi SoC Corporation
    Inventors: Fethi Dhaoui, John McCollum, Frank Hawley, Leslie Richard Wilkinson
  • Patent number: 8629018
    Abstract: Some embodiments include NAND memory constructions. The constructions may contain semiconductor material pillars extending upwardly between dielectric regions, with individual pillars having a pair of opposing vertically-extending sides along a cross-section. First conductivity type regions may be along first sides of the pillars, and second conductivity type regions may be along second sides of the individual pillars; with the second conductivity type regions contacting interconnect lines. Vertical NAND strings may be over the pillars, and select devices may selectively couple the NAND strings with the interconnect lines. The select devices may have vertical channels directly against the semiconductor material pillars and directly against upper regions of the first and second conductivity type regions. Some embodiments include methods of forming NAND memory constructions.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: January 14, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Sanh D. Tang
  • Patent number: 8623671
    Abstract: ALD processing techniques for forming non-volatile resistive-switching memories are described. In one embodiment, a method includes forming a first electrode on a substrate, maintaining a pedestal temperature for an atomic layer deposition (ALD) process of less than 100° Celsius, forming at least one metal oxide layer over the first electrode, wherein the forming the at least one metal oxide layer is performed using the ALD process using a purge duration of less than 20 seconds, and forming a second electrode over the at least one metal oxide layer.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: January 7, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Nobumichi Fuchigami, Pragati Kumar, Prashant Phatak
  • Patent number: 8610193
    Abstract: Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: December 17, 2013
    Assignee: Micron Technology Inc.
    Inventor: D. V. Nirmal Ramaswamy
  • Patent number: 8592889
    Abstract: A memory structure includes a substrate, a source region, a drain region, a gate insulating layer, a floating gate and a control gate. The substrate has a surface and a well extended from the surface to the interior of the substrate. The source region and the drain region are formed in the well and a channel region is formed between the source region and the drain region. The gate insulating layer is formed on the surface of the substrate between the source region and the drain region and covers the channel region. The floating gate disposed on the gate insulating layer to store a bit data. The control gate is disposed near lateral sides of the floating gate.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: November 26, 2013
    Assignee: United Microelectronics Corp.
    Inventor: Chin-Fu Chen
  • Patent number: 8592885
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a tunneling insulating film, a floating gate, a leak suppression unit, an inter-gate insulating film, and a control gate. The substrate includes silicon. The tunneling insulating film is provided on the substrate. The floating gate is provided on the tunneling insulating film. The leak suppression unit is provided on the floating gate. The inter-gate insulating film is provided on the leak suppression unit. The control gate is provided on the inter-gate insulating film. The dielectric constant of the leak suppression unit is higher than a dielectric constant of the inter-gate insulating film.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: November 26, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeru Kinoshita, Hisataka Meguro, Minori Kajimoto
  • Patent number: 8592275
    Abstract: An object of the present invention is to provide a semiconductor device having a nonvolatile memory cell of a high operation speed and a high rewrite cycle and a nonvolatile memory cell of high reliability. In a split gate type nonvolatile memory in which memory gate electrodes are formed in the shape of sidewalls of control gate electrodes, it is possible to produce a memory chip having a memory of a high operation speed and a high rewrite cycle and a memory of high reliability at a low cost by jointly loading memory cells having different memory gate lengths in an identical chip.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: November 26, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshiyuki Kawashima
  • Patent number: 8587036
    Abstract: A non-volatile memory is formed on a substrate. The non-volatile memory includes an isolation structure, a floating gate, and a gate dielectric layer. The isolation structure is disposed in the substrate to define an active area. The floating gate is disposed on the substrate and crosses over the active area. The gate dielectric layer is disposed between the floating gate and the substrate. The floating gate includes a first region and a second region. An energy band of the second region is lower than an energy band of the first region, so that charges stored in the floating gate are away from an overlap region of the floating gate and the gate dielectric layer.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: November 19, 2013
    Assignee: eMemory Technology Inc.
    Inventors: Shih-Chen Wang, Wen-Hao Ching
  • Patent number: 8574992
    Abstract: A vertical interconnect architecture for a three-dimensional (3D) memory device suitable for low cost, high yield manufacturing is described. Conductive lines (e.g. word lines) for the 3D memory array, and contact pads for vertical connectors used for couple the array to decoding circuitry and the like, are formed as parts of the same patterned level of material. The same material layer can be used to form the contact pads and the conductive access lines by an etch process using a single mask. By forming the contact pads concurrently with the conductive lines, the patterned material of the contact pads can protect underlying circuit elements which could otherwise be damaged during patterning of the conductive lines.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: November 5, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Shih-Hung Chen, Yen-Hao Shih, Hang-Ting Lue
  • Patent number: 8546275
    Abstract: Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack having a metal oxide buffer layer disposed on or over a metal oxide bulk layer. The metal oxide bulk layer contains a metal-rich oxide material and the metal oxide buffer layer contains a metal-poor oxide material. The metal oxide bulk layer is less electrically resistive than the metal oxide buffer layer since the metal oxide bulk layer is less oxidized or more metallic than the metal oxide buffer layer. In one example, the metal oxide bulk layer contains a metal-rich hafnium oxide material and the metal oxide buffer layer contains a metal-poor zirconium oxide material.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: October 1, 2013
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Yun Wang, Vidyut Gopal, Imran Hashim, Dipankar Pramanik, Tony Chiang
  • Patent number: 8541829
    Abstract: A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, first and second control gate electrode layers, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on a high voltage gate insulating film, a second inter-gate insulating film having an aperture, third and fourth control gate electrode layers, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on a second tunneling insulating film, a third inter-gate insulating film having an aperture, fifth and sixth control gate electrode layers, and a third metallic silicide film; and a liner insulating film directly disposed on source and drain regions of each of the memory cell transistor, the low voltage transistor, and the high voltage transistor.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: September 24, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kikuko Sugimae, Masayuki Ichige, Fumitaka Arai, Yasuhiko Matsunaga, Atsuhiro Sato