BIPOLAR TRANSISTORS WITH RESISTORS

Abstract

Bipolar transistors in complimentary MOS (CMOS) integrated circuits (ICs) are often fabricated as parasitic components, in which emitters of bipolar transistors are implanted in the same processes as CMOS sources/drains, to avoid manufacturing costs associated with dedicated implants for bipolar emitters. Energies and doses of CMOS source/drain implants are typically selected to optimize CMOS transistor performance, resulting in less than optimum values of bipolar parameters such as gain. CMOS ICs often include implanted resistors of a same type as the emitters of the bipolar transistors in the same ICs. This invention discloses bipolar transistors with emitters implanted by CMOS source/drain implants and resistor implants to improve bipolar transistor parameters, and a method for fabricating same.

Description

FIELD OF THE INVENTION

This invention relates to the field of integrated circuits. More particularly, this invention relates to bipolar transistors in integrated circuits.

BACKGROUND OF THE INVENTION

Integrated circuits commonly include n-channel MOS (NMOS) transistors, p-channel MOS (PMOS) transistors, bipolar pnp transistors, bipolar npn transistors, diodes and resistors, in and on a semiconductor substrate. Doped regions in and on the semiconductor substrate that are parts of the transistors, diodes and resistors are typically formed by ion implantation or diffusion of dopant species into the substrate. In order to achieve more economical manufacturing, photolithographic, ion implantation and diffusion processes that are used to form MOS transistors are typically applied to regions containing bipolar transistors and diodes, thus eliminating the costs associated with separate, dedicated photolithographic, ion implantation and diffusion process operations for bipolar transistors and diodes. Dedicated process operations for a component are process operations that only affect regions containing that component. Components such as bipolar transistors and diodes that are formed without dedicated process operations are commonly known as parasitic components. For example, emitter regions of vertical bipolar PNP transistors are commonly implanted in the same operation as p-channel MOS transistor source and drain regions. Using ion implantation and diffusion operations from MOS transistors for forming bipolar transistors and diodes has a disadvantage of not optimizing performance parameters of the affected bipolar transistors and diodes, because process parameters for the ion implantation and diffusion operations are chosen to maximize selected parameters of the relevant MOS transistors. For example, parasitic vertical bipolar PNP transistors commonly have gains below 2, while vertical bipolar PNP transistors formed using dedicated processes commonly have gains above 10.

Resistors are typically formed using dedicated ion implantation and diffusion operations in order to achieve desired ranges of sheet resistivities.

SUMMARY OF THE INVENTION

This Summary is provided to comply with 37 C.F.R. §1.73, requiring a summary of the invention briefly indicating the nature and substance of the invention. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Complementary MOS integrated circuits (CMOS ICs) often include implanted resistor and parasitic bipolar transistors. The instant invention is a bipolar transistor in which an emitter region is implanted in a same process as the source/drain of an MOS transistor and implanted in a same process as the resistor, and a method of fabricating such a bipolar transistor.

DESCRIPTION OF THE VIEWS OF THE DRAWING

FIG. 1A, FIG. 1B and FIG. 1C are cross-sections of an integrated circuit including an NMOS and a PMOS transistor, a p-type polysilicon resistor, and a vertical pnp bipolar transistor.

FIG. 2A, FIG. 2B and FIG. 2C are cross-sections of an integrated circuit including an NMOS and a PMOS transistor, an n-type polysilicon resistor, and a buried collector npn bipolar transistor.

FIG. 3A, FIG. 3B and FIG. 3C are cross-sections of an integrated circuit including an NMOS and a PMOS transistor, an n-type polysilicon resistor, and a lateral npn bipolar transistor.

DETAILED DESCRIPTION

The present invention is described with reference to the attached figures, wherein like reference numerals are used throughout the figures to designate similar or equivalent elements. The figures are not drawn to scale and they are provided merely to illustrate the invention. Several aspects of the invention are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide a full understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the invention. The present invention is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present invention.

For the purposes of this disclosure, the term “type polarity” of a dopant refers to the polarity of carrier, n-type or p-type, generated by the dopant in a semiconductor. For example, phosphorus and arsenic both generate n-type carriers in silicon, so both are considered be of the same type polarity.

FIG. 1A, FIG. 1B and FIG. 1C are cross-sections of an integrated circuit including an NMOS and a PMOS transistor, a p-type polysilicon resistor, and a vertical pnp bipolar transistor. FIG. 1A depicts the integrated circuit during ion implantation of PMOS source and drain regions. FIG. 1B depicts the integrated circuit during ion implantation of the p-type polysilicon resistor. FIG. 1C depicts the integrated circuit after transistor and resistor fabrication are completed.

Referring to FIG. 1A, integrated circuit (100) includes a p-type substrate (102), n-type regions known as n-wells (104), p-type regions known as p-wells (106), and field oxide regions (108), typically formed of silicon dioxide by local oxidation of silicon (LOCOS) or shallow trench isolation (STI), separating components. An NMOS transistor (110) is formed in a p-well (106). A PMOS transistor (112) is depicted as partially formed in an n-well (104). Elements of the partially formed PMOS transistor include PMOS gate structure (114) and p-type source/drain extensions (116). A p-type polysilicon resistor (118) is depicted as partially formed on field oxide (108), and includes polysilicon resistor body (120) and gate sidewall spacer material (122), typically formed of silicon nitride, abutting the resistor body (120). A vertical bipolar pnp transistor (124) is depicted as partially formed. Emitter region (126) and base diffused regions (128) are located in an n-well (104). Collector regions (130) are located in p-wells (106). A first photoresist layer (132) has been deposited and patterned on a top surface of the integrated circuit (100) to allow a first p-type dopant (134), typically boron or gallium, or a combination of both, to be ion implanted, in doses ranging from 10¹⁴ to 10¹⁶ cm⁻², at energies ranging from 1 keV to 300 keV, into the PMOS transistor (112) and the emitter region (126) and the collector regions (130) of vertical bipolar pnp transistor (124). A primary purpose of implanting the first p-type dopant (134) is to form source and drain regions for the PMOS transistor.

Referring to FIG. 1B, a second photoresist layer (136) has been deposited and patterned on a top surface of the integrated circuit (100) to allow a second p-type dopant (138), also typically boron or gallium, or a combination of both, to be ion implanted, in doses ranging from 10¹⁴ to 10¹⁶ cm⁻², at energies ranging from 1 keV to 300 keV, into the p-type polysilicon resistor (118) and emitter region (126) and collector regions (130) of vertical bipolar pnp transistor (124). A primary purpose of implanting the second p-type dopant (138) is to attain a desired sheet resistance in the polysilicon resistor body (120). The implant energy of the second p-type dopant (138) may be adjusted to improve the vertical bipolar pnp transistor (124) without adversely affecting the polysilicon resistor (118).

Implanting the emitter region (126) with both PMOS source/drain implant and polysilicon resistor body implant, according to an embodiment of the instant invention, is advantageous because the emitter-base junction is formed closer to the base-collector junction than it would be in the case of a single emitter implant, which increases gain of the vertical bipolar pnp transistor. It will be recognized by workers in integrated circuit fabrication that the benefits of the embodiments discussed above will be realized if the relative order of the PMOS source/drain implant and polysilicon resistor body implant are reversed.

Referring to FIG. 1C, fabrication of the components in the IC (100) is continued with deposition of a pre-metal dielectric (PMD) layer stack (140), typically including a liner layer, usually silicon nitride, and a PMD layer, usually silicon dioxide. Contacts (142), typically tungsten, are formed in the PMD layer stack (140) to connect NMOS transistor (110), PMOS transistor (112), polysilicon resistor (118) and vertical bipolar pnp transistor (124) to form electrical circuits.

In an alternate embodiment of the instant invention, an emitter region of a vertical bipolar pnp transistor may be implanted with only the p-type polysilicon resistor implant, thus providing a second version of vertical bipolar pnp transistor that may be used in circuits.

It will be recognized by workers in integrated circuit fabrication that the embodiments discussed above will be beneficial if the vertical bipolar pnp transistor is utilized as a diode in a circuit, by providing a lower leakage current in reverse bias.

FIG. 2A, FIG. 2B and FIG. 2C are cross-sections of an integrated circuit including an NMOS and a PMOS transistor, an n-type polysilicon resistor, and a buried collector npn bipolar transistor. FIG. 2A depicts the integrated circuit during ion implantation of NMOS source and drain regions. FIG. 2B depicts the integrated circuit during ion implantation of the n-type polysilicon resistor. FIG. 2C depicts the integrated circuit after transistor and resistor fabrication are completed.

Referring to FIG. 2A, integrated circuit (200) includes a p-type substrate (202), n-well (204), p-well (206), and field oxide regions (208), typically formed of silicon dioxide by local oxidation of silicon (LOCOS) or shallow trench isolation (STI), separating components. A PMOS transistor (210) is formed in an n-well (204). An NMOS transistor (212) is depicted as partially formed in a p-well (206). Elements of the partially formed NMOS transistor include NMOS gate structure (214) and n-type source/drain extensions (216). An n-type polysilicon resistor (218) is depicted as partially formed on field oxide (208), and includes polysilicon resistor body (220) and gate sidewall spacer material (222), typically formed of silicon nitride, abutting the resistor body (220). A buried collector bipolar npn transistor (224) is depicted as partially formed. Emitter region (226) and base diffused region (228) are located in a p-well (206). Collector diffused region (230) connects to n-type buried collector layer (232). A first photoresist layer (234) has been deposited and patterned on a top surface of the integrated circuit (200) to allow a first n-type dopant (236), typically phosphorus, arsenic or antimony, or a combination of these three, to be ion implanted, in doses ranging from 10¹⁴ to 10¹⁶ cm⁻², at energies ranging from 1 keV to 500 keV, into the NMOS transistor (210) and the emitter region (226) of buried collector bipolar npn transistor (224). A primary purpose of implanting the first n-type dopant (236) is to form source and drain regions for the NMOS transistor.

Referring to FIG. 2B, a second photoresist layer (238) has been deposited and patterned on a top surface of the integrated circuit (200) to allow a second n-type dopant (240), also typically phosphorus, arsenic or antimony, or a combination of these three, to be ion implanted, in doses ranging from 10¹⁴ to 10¹⁶ cm⁻², at energies ranging from 1 keV to 500 keV, into the n-type polysilicon resistor (218) and emitter region (226) of buried collector bipolar npn transistor (224). A primary purpose of implanting the second n-type dopant (240) is to attain a desired sheet resistance in the polysilicon resistor body (220). The implant energy of the second n-type dopant (240) may be adjusted to improve the buried collector bipolar npn transistor (224) without adversely affecting the polysilicon resistor (218).

Implanting the emitter region (226) with both NMOS source/drain implant and polysilicon resistor body implant, according to an embodiment of the instant invention, is advantageous because the emitter-base junction is formed closer to the base-collector junction than it would be in the case of a single emitter implant, which increases gain of the buried collector bipolar npn transistor. It will be recognized by workers in integrated circuit fabrication that the benefits of the embodiments discussed above will be realized if the relative order of the NMOS source/drain implant and polysilicon resistor body implant are reversed.

Referring to FIG. 2C, fabrication of the components in the IC (200) is continued with deposition of a pre-metal dielectric (PMD) layer stack (242), typically including a liner layer, usually silicon nitride, and a PMD layer, usually silicon dioxide. Contacts (244), typically tungsten, are formed in the PMD layer stack (242) to connect NMOS transistor (210), PMOS transistor (212), polysilicon resistor (218) and buried collector bipolar npn transistor (224) to form electrical circuits.

In an alternate embodiment of the instant invention, an emitter region of buried collector bipolar npn may be implanted with only the n-type polysilicon resistor implant, thus providing a second version of buried collector bipolar npn transistor that may be used in circuits.

FIG. 3A, FIG. 3B and FIG. 3C are cross-sections of an integrated circuit including an NMOS and a PMOS transistor, an n-type polysilicon resistor, and a lateral npn bipolar transistor. FIG. 3A depicts the integrated circuit during ion implantation of NMOS source and drain regions. FIG. 3B depicts the integrated circuit during ion implantation of the n-type polysilicon resistor. FIG. 3C depicts the integrated circuit after transistor and resistor fabrication are completed.

Referring to FIG. 3A, integrated circuit (300) includes a p-type substrate (302), n-well (304), p-well (306), and field oxide regions (308), typically formed of silicon dioxide by local oxidation of silicon (LOCOS) or shallow trench isolation (STI), separating components. A PMOS transistor (310) is formed in an n-well (304). An NMOS transistor (312) is depicted as partially formed in a p-well (306). Elements of the partially formed NMOS transistor include NMOS gate structure (314) and n-type source/drain extensions (316). An n-type polysilicon resistor (318) is depicted as partially formed on field oxide (308), and includes polysilicon resistor body (320) and gate sidewall spacer material (322), typically formed of silicon nitride, abutting the resistor body (320). A lateral bipolar npn transistor (324) is depicted as partially formed. Emitter region (326), base diffused region (328) and collector diffused region (330) are located in a p-well (306). A first photoresist layer (332) has been deposited and patterned on a top surface of the integrated circuit (300) to allow a first n-type dopant (334), typically phosphorus, arsenic or antimony, or a combination of these three, to be ion implanted, in doses ranging from 10¹⁴ to 10¹⁶ cm⁻², at energies ranging from 1 keV to 500 keV, into NMOS transistor (310) and emitter region (326) of lateral bipolar npn transistor (324). A primary purpose of implanting the first n-type dopant (334) is to form source and drain regions for the NMOS transistor.

Referring to FIG. 3B, a second photoresist layer (336) has been deposited and patterned on a top surface of the integrated circuit (300) to allow a second n-type dopant (338), also typically phosphorus, arsenic or antimony, or a combination of these three, to be ion implanted, in doses ranging from 10¹⁴ to 10^≠cm⁻², at energies ranging from 1 keV to 500 keV, into the n-type polysilicon resistor (318) and emitter region (326) of lateral bipolar npn transistor (324). A primary purpose of implanting the second n-type dopant (338) is to attain a desired sheet resistance in the polysilicon resistor body (320). The implant energy of the second n-type dopant (338) may be adjusted to improve the lateral bipolar npn transistor (324) without adversely affecting the polysilicon resistor (318).

Implanting the emitter region (326) with both NMOS source/drain implant and polysilicon resistor body implant, according to an embodiment of the instant invention, is advantageous because the emitter-base junction is formed closer to the base-collector junction than it would be in the case of a single emitter implant, which increases gain of the lateral bipolar npn transistor. It will be recognized by workers in integrated circuit fabrication that the benefits of the embodiments discussed above will be realized if the relative order of the NMOS source/drain implant and polysilicon resistor body implant are reversed.

Referring to FIG. 3C, fabrication of the components in the IC (300) is continued with deposition of a pre-metal dielectric (PMD) layer stack (340), typically including a liner layer, usually silicon nitride, and a PMD layer, usually silicon dioxide. Contacts (342), typically tungsten, are formed in the PMD layer stack (340) to connect NMOS transistor (310), PMOS transistor (312), polysilicon resistor (318) and lateral bipolar npn transistor (324) to form electrical circuits.

In an alternate embodiment of the instant invention, an emitter region of lateral bipolar npn may be implanted with only the n-type polysilicon resistor implant, thus providing a second version of lateral bipolar npn transistor that may be used in circuits.

In another embodiment of the instant invention, a lateral pnp bipolar transistor, a PMOS transistor and a p-type polysilicon resistor may be fabricated following the procedure discussed in reference to FIGS. 3A through 3C, with appropriate changes in device polarities and dopant types. Implanting an emitter region of a lateral pnp bipolar transistor with both PMOS source/drain implant and polysilicon resistor body implant, is advantageous because the emitter-base junction is formed closer to the base-collector junction than it would be in the case of a single emitter implant, which increases gain of the lateral bipolar pnp transistor.

It will be recognized by workers in integrated circuit fabrication that the embodiments of the instant invention discussed above may be realized when resistors formed in active areas of the integrated circuit are substituted for the polysilicon resistors described in the discussions.

Claims

1. An integrated circuit, comprising

provided a substrate;

an MOS transistor, comprising source and drain regions which are ion implanted with a first dopant at an energy from 1 to 300 keV and a dose from 1014 to 1016 cm−2;

a resistor, comprising a body region which is ion implanted with a second dopant, of the same type polarity as the first dopant, at an energy from 1 to 300 keV and a dose from 1014 to 1016 cm−2; and

a bipolar transistor, comprising an emitter which is ion implanted with said first dopant simultaneously with said source and drain regions of said MOS transistor and is ion implanted with said second dopant simultaneously with said body region of said resistor.

2. The integrated circuit of claim 1, wherein said body region of said resistor is comprised of polycrystalline silicon.

3. The integrated circuit of claim 1, wherein said body region of said resistor is comprised of an active region in said substrate.

4. The integrated circuit of claim 1, wherein:

said MOS transistor is a p-channel MOS transistor;

said first dopant is a p-type dopant;

said second dopant is a p-type dopant; and

said bipolar transistor is a vertical pnp bipolar transistor.

5. The integrated circuit of claim 1, wherein:

said MOS transistor is an n-channel MOS transistor;

said first dopant is an n-type dopant;

said second dopant is an n-type dopant; and

said bipolar transistor is a buried collector npn bipolar transistor.

6. The integrated circuit of claim 1, wherein:

said MOS transistor is an n-channel MOS transistor;

said first dopant is an n-type dopant;

said second dopant is an n-type dopant; and

said bipolar transistor is a lateral npn bipolar transistor.

7. The integrated circuit of claim 1, wherein:

said MOS transistor is a p-channel MOS transistor;

said first dopant is a p-type dopant;

said second dopant is a p-type dopant; and

said bipolar transistor is a lateral pnp bipolar transistor.

8. A method of forming an integrated circuit, comprising the steps of:

providing a substrate;

forming an MOS transistor, by a process comprising the steps of: defining source and drain regions; and ion implanting a first dopant in said source and drain regions at an energy from 1 to 300 keV and a dose from 1014 to 1016 cm−2;

forming a resistor, by a process comprising the steps of: defining a body region; and ion implanting a second dopant of the same type polarity as the first dopant in said body region at an energy from 1 to 300 keV and a dose from 1014 to 1016 cm−2;

forming a bipolar transistor, by a process comprising the steps of: defining an emitter region; ion implanting said emitter region with said first dopant simultaneously with said source and drain regions of said MOS transistor; and ion implanting said emitter region with said second dopant simultaneously with said body region of said resistor.

9. The method of claim 8, wherein said process of forming a resistor further comprises the step of forming said body region of polycrystalline silicon.

10. The method of claim 8, wherein said process of forming a resistor further comprises the step of forming said body region in an active region of said substrate.

11. The method of claim 8, wherein:

said MOS transistor is a p-channel MOS transistor;

said first dopant is a p-type dopant;

said second dopant is a p-type dopant; and

said bipolar transistor is a vertical pnp bipolar transistor.

12. The method of claim 8, wherein:

said MOS transistor is an n-channel MOS transistor;

said first dopant is an n-type dopant;

said second dopant is an n-type dopant; and

said bipolar transistor is a buried collector npn bipolar transistor.

13. The method of claim 8, wherein:

said MOS transistor is an n-channel MOS transistor;

said first dopant is an n-type dopant;

said second dopant is an n-type dopant; and

said bipolar transistor is a lateral npn bipolar transistor.

14. The method of claim 8, wherein:

said MOS transistor is a p-channel MOS transistor;

said first dopant is a p-type dopant;

said second dopant is a p-type dopant; and

said bipolar transistor is a lateral pnp bipolar transistor.

15. A method of forming an integrated circuit, comprising the steps of:

providing a substrate;

forming an MOS transistor, by a process comprising the steps of: defining source and drain regions; and ion implanting a first dopant in said source and drain regions at an energy from 1 to 300 keV and a dose from 1014 to 1016 cm−2;

forming a resistor, by a process comprising the steps of: defining a body region; and ion implanting a second dopant of the same type polarity as the first dopant in said body region at an energy from 1 to 300 keV and a dose from 1014 to 1016 cm−2;

forming a first bipolar transistor, by a process comprising the steps of: defining a first emitter region; ion implanting said first emitter region with said first dopant simultaneously with said source and drain regions of said MOS transistors; and ion implanting said first emitter region with said second dopant simultaneously with said body region of said resistor;

forming a second bipolar transistor, by a process comprising the steps of: defining a second emitter region; and ion implanting said second emitter region with said second dopant simultaneously with said body region of said resistor.

16. The method of claim 15, wherein said process of forming a resistor further comprises the step of forming said body region of polycrystalline silicon.

17. The method of claim 15, wherein said process of forming a resistor further comprises the step of forming said body region in an active region of said substrate.

18. The method of claim 15, wherein

said MOS transistor is a p-channel MOS transistor;

said first dopant is a p-type dopant;

said second dopant is a p-type dopant;

said first bipolar transistor is a vertical pnp bipolar transistor; and

said second bipolar transistor is a vertical pnp bipolar transistor.

19. The method of claim 15, wherein

said MOS transistor is an n-channel MOS transistor;

said first dopant is an n-type dopant;

said second dopant is an n-type dopant; and

said first bipolar transistor is a buried collector npn bipolar transistor;

said second bipolar transistor is a buried collector npn bipolar transistor.

20. The method of claim 15, wherein

said MOS transistor is an n-channel MOS transistor;

said first dopant is an n-type dopant;

said second dopant is an n-type dopant; and

said first bipolar transistor is a lateral npn bipolar transistor;

said second bipolar transistor is a lateral npn bipolar transistor.