Combined With Bipolar Transistor Patents (Class 257/378)
  • Patent number: 10536140
    Abstract: A half bridge circuit is disclosed. The circuit includes a GaN-based substrate, an oscillator on the substrate, and one or more components forming one or more of a low side power transistor, a low side driver, low side logic circuitry, a high side power transistor, a high side driver, and high side logic circuitry. At least one of the low side power transistor, the low side driver, the low side logic circuitry, the high side power transistor, the high side driver, and the high side logic circuitry is at least partially formed on the substrate. The oscillator is configured to generate non-overlapping pulses, and the non-overlapping pulses are separated by a dead time.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: January 14, 2020
    Assignee: NAVITAS SEMICONDUCTOR, INC.
    Inventors: Thomas Ribarich, Santosh Sharma
  • Patent number: 10439621
    Abstract: A two-step switching method of circuit switch can be used in a charge pump circuit of a phase locked loop circuit. In the method, a first type switch and a second type switch which have the same sizes and are opposite in type, are provided. The first type switch and second type switch continuously receive an input current, and the input current is kept at a low current state in a first stage before the first type switch and the second type switch are turned on. In a second stage, the first type switch and the second type switch are turned on, the input current is gradually adjusted to a target current state, and the input current of the target current state is gradually supplied to an external circuit. The present method can reduce noise generated by the external circuit, reduce power loss, and offset charge injection.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: October 8, 2019
    Assignee: National Chiao Tung University
    Inventors: Shih-Hsing Wang, Chung-Chih Hung
  • Patent number: 10438852
    Abstract: A semiconductor device includes: reverse conducting switching elements-in each of which a diode element and a switching element are arranged in parallel on a single semiconductor substrate; a driver applying a gate voltage to a plurality of gate electrodes in the reverse conducting switching elements; and a mode determination unit determining whether a forward conduction mode in which a current mainly flows through the switching element or a reverse conduction mode in which the current flows through the diode element is being operated.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: October 8, 2019
    Assignee: DENSO CORPORATION
    Inventor: Noriyuki Kakimoto
  • Patent number: 10410862
    Abstract: A first representation of an integrated circuit undergoing processing is transformed into a second representation. The second representation including additional dopants relative to the first representation. The transformation generates a three-dimensional dopant distribution from adding a first dopant under a first set of process conditions with a mask, by combining the two-dimensional lateral profile of the dopant with the one-dimensional depth profile of the dopant. The one-dimensional depth profile of the dopant is retrieved from a database storing selected results from earlier process simulation of the first addition of the first dopant under the first set of process conditions. The two-dimensional lateral dopant profile from adding the first dopant under the first set of process conditions with a first mask corresponding to the first dopant, is generated by convolving the mask with a lateral diffusion function, or from at least one solution to the 2D diffusion equation without convolution.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: September 10, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Arsen Terterian, Tommaso Cilento
  • Patent number: 10312357
    Abstract: A high-performance trench gate IGBT is provided. A trench gate IGBT according to one embodiment includes: a semiconductor substrate (11); a channel layer (15) provided on the semiconductor substrate (11); two floating P-type layer (12) provided on both sides of the channel layer 15, the floating P-type layers (12) being deeper than the channel layer (15); two emitter trenches (13) disposed between the two floating P-type layers (12), the emitter trenches (13) being respectively in contact with the floating P-type layers (12); at least two gate trenches (14) disposed between the two emitter trenches (13); and a source diffusion layer (19) disposed between the two gate trenches 14, the source diffusion layer (19) being in contact with each of the gate trenches (14).
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: June 4, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Ryo Kanda, Hitoshi Matsuura, Shuichi Kikuchi
  • Patent number: 10269430
    Abstract: Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: April 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Tessariol, Roberto Gastaldi
  • Patent number: 10217765
    Abstract: A semiconductor integrated circuit includes a semiconductor layer of a first conductivity type which is stacked on a support substrate with an insulating layer interposed between the semiconductor layer and the support substrate, a first well region of a second conductivity type buried in an upper part of the semiconductor layer so as to be separated from the insulating layer, a second well region of the first conductivity type buried in an upper part of the first well region, and an isolation region of the first conductivity type buried in the upper part of the semiconductor layer such that the isolation region surrounds the first well region and is separated from the first well region and the insulating layer.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: February 26, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroshi Kanno, Hitoshi Sumida, Masaharu Yamaji
  • Patent number: 10199371
    Abstract: The semiconductor device of the present invention includes a semiconductor substrate, a switching element which is defined on the semiconductor substrate, and a temperature sense element which is provided on the surface of the semiconductor substrate independently from the switching element and characterized by being dependent on a temperature.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: February 5, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Yuki Nakano
  • Patent number: 10177230
    Abstract: A semiconductor device includes a first semiconductor region including a first semiconductor material and a second semiconductor region adjoining the first semiconductor region, the second semiconductor region including a second semiconductor material different from the first semiconductor material. The semiconductor device further includes at least one of a drift zone and a base zone in the first semiconductor region, and at least one type of deep-level dopant in an emitter region of the second semiconductor region. The at least one type of deep-level dopant has a distance to the valence or conduction band of at least 100 meV.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: January 8, 2019
    Assignee: Infineon Technologies AG
    Inventors: Stephan Voss, Franz-Josef Niedernostheide, Hans-Joachim Schulze
  • Patent number: 10050029
    Abstract: A semiconductor device for driving a load includes: a protection circuit configured to be connected to the load, the protection circuit including a protection diode, a diode-connected unipolar protection element, and a diode-connected bipolar protection element, all of which are connected in parallel so that when connected to the load, the protection diode, the diode-connected unipolar protection element, and the diode-connected bipolar protection element are connected in parallel to the load; and a switching circuit that is connected in series to the protection circuit and that performs a switching operation so as to drive the load. The protection diode, the diode-connected unipolar protection element, and the diode-connected bipolar protection element are connected in such a polarity that each is reverse-biased when the switching circuit is turned ON, and consume a discharge current resulting from a counter-electromotive force from the load when the switching circuit is turned OFF.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: August 14, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tohru Shirakawa
  • Patent number: 10043895
    Abstract: A linear active cell region is formed from a plurality of divided active cell regions arranged apart from each other in a second direction (y direction). The linear hole collector cell region is formed from a plurality of divided hole collector cell regions arranged apart from each other in the second direction (y direction). A P-type floating region is formed in a semiconductor substrate between the linear active cell region and the linear hole collector cell region adjacent to each other in a first direction (x direction), between the divided active cell regions adjacent to each other in the second direction (y direction), and between the divided hole collector cell regions adjacent to each other in the second direction (y direction).
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: August 7, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hitoshi Matsuura
  • Patent number: 9984894
    Abstract: Methods of forming a semiconductor structure include providing an insulation layer on a semiconductor layer and diffusing cesium ions into the insulation layer from a cesium ion source outside the insulation layer. A MOSFET including an insulation layer treated with cesium ions may exhibit increased inversion layer mobility.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: May 29, 2018
    Assignees: Cree, Inc., Auburn University
    Inventors: Sarit Dhar, Sei-Hyung Ryu, Anant Agarwal, John Robert Williams
  • Patent number: 9966491
    Abstract: A bi-polar device is provided, along with methods of making the same. The bi-polar device can include a semiconductor substrate doped with a first dopant, a semiconductor layer on the first surface of the semiconductor substrate, and a Schottky barrier layer on the semiconductor layer. The method of forming a bi-polar device can include: forming a semiconductor layer on a first surface of a semiconductor substrate, where the semiconductor substrate comprises a first dopant and where the semiconductor layer comprises a second dopant that has an opposite polarity than the first dopant; and forming a Schottky barrier layer on a first portion of the semiconductor layer while leaving a second portion of the semiconductor layer exposed.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: May 8, 2018
    Assignee: University of South Carolina
    Inventors: MVS Chandrashekhar, Tangali S. Sudarshan, Sabih U. Omar, Gabriel Brown, Shamaita S. Shetu
  • Patent number: 9891113
    Abstract: The present disclosure relates to a thermal sensor and a method for producing a thermal sensor of this type having a low signal-to-noise ratio at relatively high signal strengths. To this end, a thermoelectric generator is combined with a field effect transistor and a diode. Owing to its integrated diode and the barrier effect associated therewith, the thermal sensor is suitable for the economical and efficient design of imaging sensor arrays for converting thermal radiation into electrical signals.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: February 13, 2018
    Assignee: Robert Bosch GmbH
    Inventors: Ingo Herrmann, Fabian Utermoehlen
  • Patent number: 9880573
    Abstract: A low dropout (LDO) device with improved linear mode comprising an error amplifier, a programmable attenuation factor circuit coupled to said error amplifier, a feedback network whose input is electrically connected to said programmable attenuation factor circuit and whose output is electrically coupled to the negative input of said error amplifier, a high side (HS) pre-drive circuit whose input is a high impedance (HiZ) mode signal, a low side (LS) pre-drive circuit whose input is a low pull-down input mode signal, a high side (HS) output stage element electrically coupled to said high side (HS) pre-drive circuit, a low side (LS) output stage element electrically coupled to said low side (LS) pre-drive circuit, and a high side sense (HSENSE) output stage element whose gate is electrically coupled to said high side (HS) pre-drive circuit, and whose gate and source are electrically connected to the output of said error amplifier.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: January 30, 2018
    Assignee: Dialog Semiconductor GmbH
    Inventors: Zakaria Mengad, Mykhaylo Teplechuk
  • Patent number: 9859414
    Abstract: A semiconductor device includes a drift layer 20 of a first conductivity type, a base layer 30 of a second conductivity type that is disposed on the drift layer 20 and is connected to a source electrode 90, and a column layer 50 of a second conductivity type that is connected to the source electrode 90 and penetrates the base layer 30 to extend into the drift layer 20.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: January 2, 2018
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Takeshi Asada, Mizue Kitada, Takeshi Yamaguchi, Noriaki Suzuki
  • Patent number: 9806186
    Abstract: A vertical power switching device, such as a vertical superjunction metal-oxide-semiconductor field-effect-transistor (MOSFET), in which termination structures in the corners of the integrated circuit are stretched to efficiently shape the lateral electric field. Termination structures in the device include such features as doped regions, field plates, insulator films, and high-voltage conductive regions and elements at the applied substrate voltage. Edges of these termination structures are shaped and placed according to a 2nd-order smooth, non-circular analytic function so as to extend deeper into the die corner from the core region of the device than a constant-distance path. Also disclosed are electrically floating guard rings in the termination region, to inhibit triggering of parasitic p-n-p-n structures.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: October 31, 2017
    Assignee: D3 Semiconductor LLC
    Inventors: Thomas E. Harrington, III, John V. Spohnheimer, Zhijun Qu
  • Patent number: 9793364
    Abstract: A semiconductor device with a deep trench has a dielectric liner formed on sidewalls and a bottom of the deep trench. A pre-etch deposition step of a two-step process forms a protective polymer on an existing top surface of the semiconductor device, and on the dielectric liner proximate to a top surface of the substrate. The pre-etch deposition step does not remove a significant amount of the dielectric liner from the bottom of the deep trench. A main etch step of the two-step process removes the dielectric liner at the bottom of the deep trench while maintaining the protective polymer at the top of the deep trench. The protective polymer is subsequently removed.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: October 17, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: David William Hamann, Thomas E. Lillibridge, Abbas Ali
  • Patent number: 9735061
    Abstract: Methods to form multi Vt channels, including a single type of WF material, utilizing lower annealing temperatures and the resulting devices are disclosed.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: August 15, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hoon Kim, Min-gyu Sung, Ruilong Xie, Chanro Park
  • Patent number: 9685506
    Abstract: There are disclosed herein implementations of an insulated-gate bipolar transistor (IGBT) having an inter-trench superjunction structure. Such an IGBT includes a drift region having a first conductivity type situated over a collector having a second conductivity type. The IGBT also includes first and second gate trenches extending through a base having the second conductivity type into the drift region, the first and second gate trenches each being bordered by an emitter diffusion having the first conductivity type. In addition, the IGBT includes an inter-trench superjunction structure situated in the drift region between the first and second gate trenches.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: June 20, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Florin Udrea, Alice Pei-Shan Hsieh, Gianluca Camuso, Chiu Ng, Yi Tang, Rajeev Krishna Vytla
  • Patent number: 9666505
    Abstract: A power metal oxide semiconductor (MOS) transistor die with a temperature sensing function and an integrated circuit are provided. The power MOS transistor die has a control terminal, a phase terminal, a ground terminal and a temperature signal output terminal, and that further includes a power switch part and a temperature sensing part. The power switch part has: a first electrode coupled to the control terminal; a second electrode coupled to the ground terminal; and a third electrode coupled to the phase terminal. The temperature sensing part has: a first electrode; a second electrode coupled to the temperature signal output terminal; and a third electrode coupled to the third electrode of the power switch part. The power switch part and the temperature sensing part are configured as a MOS transistor made by a same manufacturing process, and are capable of sensing temperature precisely.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: May 30, 2017
    Assignee: uPl Semiconductor Corp.
    Inventor: Sheng-An Ko
  • Patent number: 9559195
    Abstract: A semiconductor device of the present invention includes a semiconductor layer, a plurality of gate trenches formed in the semiconductor layer, a gate electrode filled via a gate insulating film in the plurality of gate trenches, an n+-type emitter region, a p-type base region, and an n?-type drift region disposed, lateral to each gate trench, in order in a depth direction of the gate trench from a front surface side of the semiconductor layer, a p+-type collector region disposed on a back surface side of the semiconductor layer with respect to the n?-type drift region, an emitter trench formed between the plurality of gate trenches adjacent to each other, and a buried electrode filled via an insulating film in the emitter trench, and electrically connected with the n+-type emitter region, and the emitter trench is disposed at an interval of 2 ?m or less via an n?-type drift region with the gate trench.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: January 31, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Akihiro Hikasa
  • Patent number: 9553011
    Abstract: An integrated circuit is formed on a substrate containing a semiconductor material having a first conductivity type. A deep well having a second, opposite, conductivity type is formed in the semiconductor material of the first conductivity type. A deep isolation trench is formed in the substrate through the deep well so as separate an unused portion of the deep well from a functional portion of the deep well. The functional portion of the deep well contains an active circuit element of the integrated circuit. The separated portion of the deep well does not contain an active circuit element. A contact region having the second conductivity type and a higher average doping density than the deep well is formed in the separated portion of the deep well. The contact region is connected to a voltage terminal of the integrated circuit.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: January 24, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yongxi Zhang, Eugen Mindricelu, Sameer Pendharkar, Seetharaman Sridhar
  • Patent number: 9461036
    Abstract: A semiconductor device which uses a fin-type semiconductor layer to form a bipolar transistor. The substrate of the device is a semiconductor substrate. A collector is a first-conductivity type impurity region which is formed in the semiconductor substrate. A base is a second-conductivity type impurity region which is formed in the surface layer of the collector. A first semiconductor layer is a fin-type semiconductor layer which lies over the base. An emitter is formed in the first semiconductor layer and its bottom is coupled to the base. A first contact is coupled to the collector, a second contact is coupled to the base, and a third contact is coupled to the emitter.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: October 4, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hisamitsu Suzuki
  • Patent number: 9391181
    Abstract: An embodiment concerns forming an EPI film on a substrate where the EPI film has a different lattice constant from the substrate. The EPI film and substrate may include different materials to collectively form a hetero-epitaxial device having, for example, a Si and/or SiGe substrate and a III-V or IV film. The EPI film may be one of multiple EPI layers or films and the films may include different materials from one another and may directly contact one another. Further, the multiple EPI layers may be doped differently from another in terms of doping concentration and/or doping polarity. One embodiment includes creating a horizontally oriented hetero-epitaxial structure. Another embodiment includes a vertically oriented hetero-epitaxial structure. The hetero-epitaxial structures may include, for example, a bipolar junction transistor, heterojunction bipolar transistor, thyristor, and tunneling field effect transistor among others. Other embodiments are described herein.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: July 12, 2016
    Assignee: Intel Corporation
    Inventors: Benjamin Chu-Kung, Van H. Le, Robert S. Chau, Sansaptak Dasgupta, Gilbert Dewey, Niti Goel, Jack T. Kavalieros, Matthew V. Metz, Niloy Mukherjee, Ravi Pillarisetty, Willy Rachmady, Marko Radosavljevic, Han Wui Then, Nancy M. Zelick
  • Patent number: 9385117
    Abstract: An integrated circuit formed on a silicon substrate includes an NMOS transistor with n-channel raised source and drain (NRSD) layers adjacent to a gate of the NMOS transistor, a PMOS transistor with SiGe stressors in the substrate adjacent to a gate of the PMOS transistor, and an NPN heterojunction bipolar transistor (NHBT) with a p-type SiGe base formed in the substrate and an n-type silicon emitter formed on the SiGe base. The SiGe stressors and the SiGe base are formed by silicon-germanium epitaxy. The NRSD layers and the silicon emitter are formed by silicon epitaxy.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: July 5, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Manoj Mehrotra, Terry J. Bordelon, Jr., Deborah J. Riley
  • Patent number: 9356137
    Abstract: Various embodiments of a power MOS device structure are disclosed. In one aspect, a power MOS device structure includes a plurality of LDMOS and a plurality of bonding pads. The basic units of LDMOS are coupled in parallel and electrically coupled to the bonding pads to couple to a gate terminal, a source terminal, a drain terminal and a substrate of each of the basic units of LDMOS. The basic units of LDMOS are disposed below the bonding pads. The bonding pads include a single layer of metal with a thickness of 3.5 um to 4.5 um and a width of 1.5 um to 2.5 um. The region below the bonding pads of the power MOS device of the present disclosure is utilized to increase the number of basic units of LDMOS, thereby effectively reducing the on-resistance.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: May 31, 2016
    Assignee: CSMC TECHNOLOGIES FAB1 CO., LTD.
    Inventors: Shu Zhang, Yanqiang He, TseHuang Lo, HsiaoChia Wu
  • Patent number: 9312338
    Abstract: A semiconductor device includes a single crystalline semiconductor body with a first surface and a second surface parallel to the first surface. The semiconductor body contains chalcogen atoms and a background doping of pnictogen and/or hydrogen atoms. A concentration of the chalcogen atoms is at least 1E12 cm?3. A ratio of the chalcogen atoms to the atoms of the background doping is in a range from 1:9 to 9:1.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: April 12, 2016
    Assignee: Infineon Technologies AG
    Inventor: Gerhard Schmidt
  • Patent number: 9293473
    Abstract: A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: March 22, 2016
    Assignee: SOITEC
    Inventors: Patrick Reynaud, Sebastien Kerdiles, Daniel Delprat
  • Patent number: 9276060
    Abstract: A triode includes a semiconductor, a deep n-well, a p-well, an n+ doping region, and a doping region. The deep n-well is disposed adjacent to the semiconductor substrate. The p-well is included in the deep n-well and serves as a collector region of the triode. The n+ doping region serves as a base region of the triode. The p+ doping region serves as an emitter region of the triode. The deep n-well is coupled to the n+ doping region via at least one conducting channel.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: March 1, 2016
    Assignee: Fitipower Integrated Technology, Inc.
    Inventor: Chih-Nan Cheng
  • Patent number: 9105682
    Abstract: Disclosed is a semiconductor component that includes a semiconductor body, a first emitter region of a first conductivity type in the semiconductor body, a second emitter region of a second conductivity type spaced apart from the first emitter region in a vertical direction of the semiconductor body, a base region of one conductivity type arranged between the first emitter region and the second emitter region, and at least two higher doped regions of the same conductivity type as the base region and arranged in the base region. The at least two higher doped regions are spaced apart from one another in a lateral direction of the semiconductor body and separated from one another only by sections of the base region.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: August 11, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Peter Felsl, Thomas Raker, Hans-Joachim Schulze, Franz-Josef Niedernostheide
  • Patent number: 9054151
    Abstract: A semiconductor device includes a semiconductor body including a first surface having a normal direction defining a vertical direction, a first n-type semiconductor region arranged below the first surface and having a first maximum doping concentration and a second n-type semiconductor region arranged below the first n-type semiconductor region and including, in a vertical cross-section, two spaced apart first n-type portions each adjoining the first n-type semiconductor region, having a maximum doping concentration which is higher than the first maximum doping concentration and having a first minimum distance to the first surface, and a second n-type portion adjoining the first n-type semiconductor region, having a maximum doping concentration which is higher than the first maximum doping concentration and a second minimum distance to the first surface which is larger than the first minimum distance. A p-type second semiconductor layer forms a pn-junction with the second n-type portion.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: June 9, 2015
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Yvonne Gawlina
  • Patent number: 9029955
    Abstract: An integrated circuit includes a semiconductor substrate, a silicon layer, a buried isolating layer arranged between the substrate and the layer, a bipolar transistor comprising a collector and emitter having a first doping, and a base and a base contact having a second doping, the base forming a junction with the collector and emitter, the collector, emitter, base contact, and the base being coplanar, a well having the second doping and plumb with the collector, emitter, base contact and base, the well separating the collector, emitter and base contact from the substrate, having the second doping and extending between the base contact and base, a isolating trench plumb with the base and extending beyond the layer but without reaching a bottom of the emitter and collector, and another isolating trench arranged between the base contact, collector, and emitter, the trench extending beyond the buried layer into the well.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: May 12, 2015
    Assignees: Commissariat á l'énergie atomique et aux énergies alternatives, STMicroelectronics SA
    Inventors: Claire Fenouillet-Beranger, Pascal Fonteneau
  • Publication number: 20150108580
    Abstract: One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures.
    Type: Application
    Filed: December 23, 2014
    Publication date: April 23, 2015
    Inventors: Jerome Ciavatti, Roderick Miller, Marc Tarabbia
  • Patent number: 9006839
    Abstract: In a semiconductor substrate of a semiconductor device, a drift layer, a body layer, an emitter layer, and a trench gate electrode are formed. When the semiconductor substrate is viewed in a plane manner, the semiconductor substrate is divided into a first region covered with a heat dissipation member, and a second region not covered with the heat dissipation member. A density of trench gate electrodes in the first region is equal to a density of trench gate electrodes in the second region. A value obtained by dividing an effective carrier amount of channel parts formed in the first region by an area of the first region is larger than a value obtained by dividing an effective carrier amount of channel parts formed in the second region by an area of the second region.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: April 14, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Tadashi Misumi
  • Patent number: 8994147
    Abstract: A semiconductor device includes a semiconductor element including a first element portion having a first gate and a second element portion having a second gate, wherein the turning on and off of the first and second element portions are controlled by a signal from the first and second gates respectively. The semiconductor device further includes signal transmission means connected to the first gate and the second gate and transmitting a signal to the first gate and the second gate so that when the semiconductor element is to be turned on, the first element portion and the second element portion are simultaneously turned on, and so that when the semiconductor element is to be turned off, the second element portion is turned off a delay time after the first element portion is turned off.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: March 31, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Khalid Hassan Hussein, Shoji Saito
  • Patent number: 8963253
    Abstract: A bi-directional electrostatic discharge (ESD) protection device may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates, one or more P+ doped plates, one or more field oxide (FOX) portions, and one or more field plates. A multi-emitter structure is also provided.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: February 24, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsin-Liang Chen, Shuo-Lun Tu
  • Patent number: 8946018
    Abstract: Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second semiconductor material is epitaxially grown over the first semiconductor material. The second semiconductor material is patterned to form circuit components, and the heavily-doped region is patterned to form spaced-apart buried lines electrically coupling pluralities of the circuit components to one another. At least some of the patterning of the heavily-doped region occurs simultaneously with at least some of the patterning of the second semiconductor material.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Jaydip Guha, Shyam Surthi
  • Publication number: 20150001634
    Abstract: One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Jerome Ciavatti, Roderick Miller, Marc Tarabbia
  • Patent number: 8921945
    Abstract: The power transistor configured to be integrated into a trench-isolated thick layer SOI-technology with an active silicon layer with a thickness of about 50 ?m. The power transistor may have a lower resistance than the DMOS transistor and a faster switch-off behavior than the IGBT.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: December 30, 2014
    Assignee: X-Fab Semiconductor Foundries AG
    Inventor: Ralf Lerner
  • Patent number: 8907450
    Abstract: Methods and apparatus for metal semiconductor wafer bonding for high-Q devices are provided. An exemplary capacitor includes a first plate formed on a glass substrate, a second plate, and a dielectric layer. No organic bonding agent is used between the first plate and the glass substrate, and the dielectric layer can be an intrinsic semiconductor. A extrinsic semiconductor layer that is heavily doped contacts the dielectric layer. The dielectric and extrinsic semiconductor layers are sandwiched between the first and second plates. An intermetallic layer is formed between the first plate and the dielectric layer. The intermetallic layer is thermo compression bonded to the first plate and the dielectric layer. The capacitor can be coupled in a circuit as a high-Q capacitor and/or a varactor, and can be integrated with a mobile device.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: December 9, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Changhan Yun, Chengjie Zuo, Chi Shun Lo, Jonghae Kim, Mario F. Velez
  • Patent number: 8901669
    Abstract: A method of manufacturing an integrated circuit comprising bipolar transistors including first and second type bipolar transistors, the method comprising providing a substrate comprising first isolation regions each separated from a second isolation region by an active region comprising a collector impurity of one of the bipolar transistors; forming a base layer stack over the substrate; forming a first emitter cap layer of a first effective thickness over the base layer stack in the areas of the first type bipolar transistor; forming a second emitter cap layer of a second effective thickness different from the first effective thickness over the base layer stack in the areas of the second type bipolar transistor; and forming an emitter over the emitter cap layer of each of the bipolar transistors. An IC in accordance with this method.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: December 2, 2014
    Assignee: NXP, B.V.
    Inventors: Hans Mertens, Johannes Theodorus Marinus Donkers, Evelyne Gridelet, Tony Vanhoucke, Petrus Hubertus Cornelis Magnee
  • Patent number: 8901611
    Abstract: Bipolar field effect transistor (BiFET) structures and methods of forming the same are provided. In one embodiment, an apparatus includes a substrate and a plurality of epitaxial layers disposed over the substrate. The plurality of epitaxial layers includes a first epitaxial layer, a second epitaxial layer disposed over the first epitaxial layer, and a third epitaxial layer disposed over the second epitaxial layer. The first epitaxial layer includes at least a portion of a channel of a first field effect transistor (FET) and the third epitaxial layer includes at least a portion of a channel of a second FET.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: December 2, 2014
    Assignee: Skyworks Solutions, Inc.
    Inventors: Peter J. Zampardi, Jr., Hsiang-Chih Sun
  • Patent number: 8872222
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a doped strip and a top doped region. The first doped region has a first type conductivity. The second doped region is formed in the first doped region and has a second type conductivity opposite to the first type conductivity. The doped strip is formed in the first doped region and has the second type conductivity. The top doped region is formed in the doped strip and has the first type conductivity. The top doped region has a first sidewall and a second sidewall opposite to the first sidewall. The doped strip is extended beyond the first sidewall or the second sidewall.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: October 28, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Ching-Lin Chan, Chen-Yuan Lin, Cheng-Chi Lin, Shih-Chin Lien
  • Patent number: 8860144
    Abstract: In general, according to one embodiment, a power semiconductor device includes a first pillar region, a second pillar region, and an epitaxial layer of a first conductivity type on a first semiconductor layer. The first pillar region is composed of a plurality of first pillar layers of a second conductivity type and a plurality of second pillar layers of the first conductivity type alternately arranged along a first direction. The second pillar region is adjacent to the first pillar region along the first direction and includes a third pillar layer of the second conductivity type, a fourth pillar layer of the first conductivity type, and a fifth pillar layer of the second conductivity type in this order along the first direction. A plurality of second base layers of the second conductivity type electrically connected, respectively, onto the third pillar layer and the fifth pillar layer and spaced from each other.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: October 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Ohta, Yasuto Sumi, Kiyoshi Kimura, Junji Suzuki, Hiroyuki Irifune, Wataru Saito, Syotaro Ono
  • Patent number: 8853775
    Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having first and second main surfaces, control electrodes disposed in trenches on the first main surface of the semiconductor substrate and extending in a first direction parallel to the first main surface, and control interconnects disposed on the first main surface of the semiconductor substrate and extending in a second direction perpendicular to the first direction. The semiconductor substrate includes a first semiconductor layer of a first conductivity type, second semiconductor layers of a second conductivity type on a surface of the first semiconductor layer on a first main surface side, third semiconductor layers of the first conductivity type disposed on surfaces of the second semiconductor layers on the first main surface side and extending in the second direction, and a fourth semiconductor layer of the second conductivity type on the second main surface of the semiconductor substrate.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: October 7, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuneo Ogura, Kazutoshi Nakamura, Hideaki Ninomiya, Tomoko Matsudai, Yuichi Oshino
  • Patent number: 8847278
    Abstract: A semiconductor device includes an active section for a main current flow and a breakdown withstanding section for breakdown voltage. An external peripheral portion surrounds the active section on one major surface of an n-type semiconductor substrate. The breakdown withstanding section has a ring-shaped semiconductor protrusion, with a rectangular planar pattern including a curved section in each of four corners thereof, as a guard ring. The ring-shaped semiconductor protrusion has a p-type region therein, is sandwiched between a plurality of concavities deeper than the p-type region, and has an electrically conductive film across an insulator film on the surface thereof. Because of this, it is possible to manufacture at low cost a breakdown withstanding structure with which a high breakdown voltage is obtained in a narrow width, wherein there is little drop in breakdown voltage, even when there are variations in a patterning process of a field oxide film.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: September 30, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Manabu Takei, Yusuke Kobayashi
  • Patent number: 8836042
    Abstract: A semiconductor device includes an IGBT, a constant voltage circuit, and protection Zener diodes. The IGBT makes/breaks a low-voltage current flowing in a primary coil. The constant voltage circuit and the protection Zener diodes are provided between an external gate terminal and an external collector terminal. The constant voltage circuit supplies a constant gate voltage to the IGBT to thereby set a saturation current value of the IGBT to a predetermined limiting current value. The IGBT has the saturation current value in a limiting current value range of the semiconductor device.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: September 16, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Katsunori Ueno
  • Patent number: 8829609
    Abstract: An insulated gate semiconductor device, comprising: a semiconductor body having a front side and a back side opposite to one another; a drift region, which extends in the semiconductor body and has a first type of conductivity and a first doping value; a body region having a second type of conductivity, which extends in the drift region facing the front side of the semiconductor body; a source region, which extends in the body region and has the first type of conductivity; and a buried region having the second type of conductivity, which extends in the drift region at a distance from the body region and at least partially aligned to the body region in a direction orthogonal to the front side and to the back side.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: September 9, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Donato Corona, Giovanni Samma Trice, Sebastiano Amara, Salvatore Pisano, Antonio Giuseppe Grimaldi
  • Patent number: 8829650
    Abstract: A zener diode in a SiGe BiCMOS process is disclosed. An N-type region of the zener diode is formed in an active region and surrounded by an N-deep well. A pseudo buried layer is formed under each of the shallow trench field oxide regions on a corresponding side of the active region, and the N-type region is connected to the pseudo buried layers via the N-deep well. The N-type region has its electrode picked up by deep hole contacts. A P-type region of the zener diode is formed of a P-type ion implanted region in the active region. The P-type region is situated above and in contact with the N-type region, and has a doping concentration greater than that of the N-type region. The P-type region has its electrode picked up by metal contact. A method of fabricating zener diode in a SiGe BiCMOS process is also disclosed.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: September 9, 2014
    Assignee: Shanghai Hua Hong Nec Electronics Co., Ltd.
    Inventors: Donghua Liu, Jun Hu, Wenting Duan, Wensheng Qian, Jing Shi