Abstract: Shielding techniques are used to provide an embedded sensor element such as a temperature sensing element on a wide bandgap power semiconductor device. A semiconductor device may include a drift layer and an embedded sensor element. The drift layer may be a wide bandgap semiconductor material. A shielding structure is provided in the drift layer below the embedded sensor element. The embedded sensor element may be provided between contacts that are in electrical contact with the shielding well. The distance between the contacts may be minimized. A noise reduction well may be provided between the contacts to further isolate the embedded sensor element from parasitic signals.

Abstract: An apparatus includes a first drain/source region and a second drain/source region over a substrate, and a first gate adjacent to the first drain/source region and a second gate adjacent to the second drain/source region, wherein the first gate and the second gate are separated from each other, wherein the first drain/source region, the second drain/source region, the first gate and the second gate form two back-to-back connected transistors.

Abstract: According to one embodiment, a power generation element includes a first conductive region including a first surface, a plurality of second conductive regions, and a plurality of insulating structure regions. The second conductive regions are arranged along the first surface. A gap is provided between the second conductive regions and the first surface. One of the structure regions is provided between one of the second conductive regions and the first surface. An other one of the structure regions is provided between an other one of the second conductive regions and the first surface.

Abstract: A bipolar transistor includes a collector. The collector is formed by: a first portion of the collector which extends under an insulating trench, and a second portion of the collector which crosses through the insulating trench. The first and second portions of the collector are in physical contact.

Abstract: A power semiconductor device includes a semiconductor layer, a ladder-shaped trench recessed a specific depth from a surface of the semiconductor layer into the semiconductor layer and including a pair of lines having a first depth and a plurality of connectors connected between the pair of lines and having a second depth shallower than the first depth, a well region defined in the semiconductor layer between the pair of lines and between the plurality of connectors of the trench, a floating region defined in the semiconductor layer outside the pair of lines of the trench, a gate insulating layer disposed on an inner wall of the trench, and a gate electrode layer disposed on the gate insulating layer to fill the trench and including a first portion in which the pair of lines is filled and a second portion in which the plurality of connectors is filled. A depth of the second portion of the gate electrode layer is shallower than a depth of the first portion of the gate electrode layer.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a first well, a second well and doped regions. The substrate has heavily doped and lightly doped regions over the heavily doped region. The first wells are disposed in the lightly doped region and arranged as an array. The first wells have a conductive type opposite to a conductive type of the heavily doped and lightly doped regions. The second well is disposed in the substrate over the lightly doped region, and has an active region defined by an isolation structure. The first wells are overlapped with the second well. Top ends of the first wells are lower than a bottom end of the second well. The doped regions are separately located in the active region, and have a conductive type opposite to a conductive type of the second well.

Abstract: A semiconductor integrated circuit device may include a semiconductor substrate, an active well, an emitter, a base, a collector, a body contact region, and a blocking well. The semiconductor substrate may have a first conductive type. The active well may be formed in the semiconductor substrate. The active well may have a second conductive type. The emitter and the base may be formed in the active well. The collector may be formed in the semiconductor substrate outside the active well. The body contact region may be formed in the semiconductor substrate to electrically connect the collector with the semiconductor substrate. The body contact region may have a conductive type substantially the same as that of the collector. The blocking well may be configured to surround an outer wall of the body contact region. The blocking well may have the second conductive type.

Abstract: A semiconductor module includes a diode bridge circuit, a sensor configured to measure a current value of the diode bridge circuit, a current limiting circuit having an IGBT connected to the diode bridge circuit, and a protection circuit configured to switch ON and OFF the IGBT in accordance with the current value of the diode bridge circuit measured by the sensor.

Abstract: A semiconductor integrated circuit includes: implanting impurity ions of a p-type at different implantation positions by multiple implantation in a part of an upper portion of a semiconductor layer of an n?-type to form first ion implantation regions; implanting the impurity ions of the p-type at different implantation positions by multiple implantation in another part of the upper portion of the semiconductor layer to form second ion implantation regions; activating the impurity ions in the first ion implantation regions to form a well region, and activating the impurity ions in the second ion implantation regions to form a body region; forming a control element including first and second terminal regions of the n+-type in an upper portion of the well region; and forming an output-stage element including an output terminal region of the n+-type in an upper portion of the body region to be controlled by the control element.

Abstract: The disclosed technology generally relates to integrated circuit devices having at least one transistor, and methods of fabricating the same. In one aspect, an integrated circuit device can be produced from a silicon substrate and can include at least one nano-ridge transistor formed from III-V semiconducting crystal portions. The III-V portions can be grown epitaxially from the silicon substrate using an intermediate portion which can be adapted to produce aspect ratio trapping. The nano-ridge transistor can have a reduced footprint on the silicon substrate, may be adapted for power RF applications, and can be combined with MOS or CMOS transistors within one and a same integrated circuit.

Abstract: A semiconductor device may include a semiconductor layer; a source electrode disposed above one main surface of the semiconductor layer; a drain electrode disposed below another main surface of the semiconductor layer; and an insulation gate section. The semiconductor layer may include a drift region of a first conductivity type; a JFET region of the first conductivity type disposed above the drift region; a body region of a second conductivity type disposed above the drift region and adjoining the JFET region; and a source region of the first conductivity type separated from the JFET region by the body region. The insulation gate section may be opposed to a portion of the body region that separates the JFET region and the source region, a space may be provided within the semiconductor layer, and the drift region, the JFET region and the body region may be exposed to the space.

Abstract: A semiconductor device includes at least a first transistor including at least a second level metal layer (second metal layer) above a first level metal layer coupled by a source contact to a source region doped with a first dopant type. The second level metal layer is coupled by a drain contact to a drain region doped with the first dopant type. A gate stack is between the source region and drain region having the second level metal layer coupled by a contact thereto. The second level metal layer is coupled by a contact to a first isolation region doped with the second dopant type. The source region and drain region are within the first isolation region. A second isolation region doped with the first dopant type encloses the first isolation region, and is not coupled to the second level metal layer so that it electrically floats.

Abstract: A semiconductor device includes: semiconductor layer having first and second surfaces; first base region of first conductivity type formed in the semiconductor layer; second base region of second conductivity type adjacent to the first base region and formed in the semiconductor layer; first surface region of the second conductivity type selectively formed in the first base region; second surface region of the first conductivity type selectively formed in the second base region separate from the first base region; gate electrode facing portion of the first base region between boundary between the first and second base regions and the first surface region and portion of the second base region between the boundary and the second surface region, the gate electrode extending across the boundary; first and second electrodes connected to the first and second surface regions respectively; and third electrode connected in common to the first and second base regions.

Abstract: In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating.

Abstract: A semiconductor device includes a semiconductor layer, having an active region, in which a functional element is formed, a first impurity region of a first conductivity type, formed at a surface layer portion of the semiconductor layer, a second impurity region of a second conductivity type, formed at a surface layer portion of the first impurity region and defining the active region, and a well region of the second conductivity type, formed along a periphery of the second impurity region at the surface layer portion of the first impurity region and having an inner side edge portion positioned at the second impurity region side, and an outer side edge portion positioned at an opposite side with respect to the second impurity region and having a second conductivity type impurity concentration lower than a second conductivity type impurity concentration of the inner side edge portion.

Abstract: A half bridge circuit is disclosed. The circuit includes a GaN-based substrate, an oscillator on the substrate, and one or more components forming one or more of a low side power transistor, a low side driver, low side logic circuitry, a high side power transistor, a high side driver, and high side logic circuitry. At least one of the low side power transistor, the low side driver, the low side logic circuitry, the high side power transistor, the high side driver, and the high side logic circuitry is at least partially formed on the substrate. The oscillator is configured to generate non-overlapping pulses, and the non-overlapping pulses are separated by a dead time.

Abstract: A semiconductor device includes: reverse conducting switching elements-in each of which a diode element and a switching element are arranged in parallel on a single semiconductor substrate; a driver applying a gate voltage to a plurality of gate electrodes in the reverse conducting switching elements; and a mode determination unit determining whether a forward conduction mode in which a current mainly flows through the switching element or a reverse conduction mode in which the current flows through the diode element is being operated.

Abstract: A two-step switching method of circuit switch can be used in a charge pump circuit of a phase locked loop circuit. In the method, a first type switch and a second type switch which have the same sizes and are opposite in type, are provided. The first type switch and second type switch continuously receive an input current, and the input current is kept at a low current state in a first stage before the first type switch and the second type switch are turned on. In a second stage, the first type switch and the second type switch are turned on, the input current is gradually adjusted to a target current state, and the input current of the target current state is gradually supplied to an external circuit. The present method can reduce noise generated by the external circuit, reduce power loss, and offset charge injection.

Abstract: A first representation of an integrated circuit undergoing processing is transformed into a second representation. The second representation including additional dopants relative to the first representation. The transformation generates a three-dimensional dopant distribution from adding a first dopant under a first set of process conditions with a mask, by combining the two-dimensional lateral profile of the dopant with the one-dimensional depth profile of the dopant. The one-dimensional depth profile of the dopant is retrieved from a database storing selected results from earlier process simulation of the first addition of the first dopant under the first set of process conditions. The two-dimensional lateral dopant profile from adding the first dopant under the first set of process conditions with a first mask corresponding to the first dopant, is generated by convolving the mask with a lateral diffusion function, or from at least one solution to the 2D diffusion equation without convolution.

Abstract: A high-performance trench gate IGBT is provided. A trench gate IGBT according to one embodiment includes: a semiconductor substrate (11); a channel layer (15) provided on the semiconductor substrate (11); two floating P-type layer (12) provided on both sides of the channel layer 15, the floating P-type layers (12) being deeper than the channel layer (15); two emitter trenches (13) disposed between the two floating P-type layers (12), the emitter trenches (13) being respectively in contact with the floating P-type layers (12); at least two gate trenches (14) disposed between the two emitter trenches (13); and a source diffusion layer (19) disposed between the two gate trenches 14, the source diffusion layer (19) being in contact with each of the gate trenches (14).

Abstract: Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described.

Abstract: A semiconductor integrated circuit includes a semiconductor layer of a first conductivity type which is stacked on a support substrate with an insulating layer interposed between the semiconductor layer and the support substrate, a first well region of a second conductivity type buried in an upper part of the semiconductor layer so as to be separated from the insulating layer, a second well region of the first conductivity type buried in an upper part of the first well region, and an isolation region of the first conductivity type buried in the upper part of the semiconductor layer such that the isolation region surrounds the first well region and is separated from the first well region and the insulating layer.

Abstract: The semiconductor device of the present invention includes a semiconductor substrate, a switching element which is defined on the semiconductor substrate, and a temperature sense element which is provided on the surface of the semiconductor substrate independently from the switching element and characterized by being dependent on a temperature.

Abstract: A semiconductor device includes a first semiconductor region including a first semiconductor material and a second semiconductor region adjoining the first semiconductor region, the second semiconductor region including a second semiconductor material different from the first semiconductor material. The semiconductor device further includes at least one of a drift zone and a base zone in the first semiconductor region, and at least one type of deep-level dopant in an emitter region of the second semiconductor region. The at least one type of deep-level dopant has a distance to the valence or conduction band of at least 100 meV.

Abstract: A semiconductor device for driving a load includes: a protection circuit configured to be connected to the load, the protection circuit including a protection diode, a diode-connected unipolar protection element, and a diode-connected bipolar protection element, all of which are connected in parallel so that when connected to the load, the protection diode, the diode-connected unipolar protection element, and the diode-connected bipolar protection element are connected in parallel to the load; and a switching circuit that is connected in series to the protection circuit and that performs a switching operation so as to drive the load. The protection diode, the diode-connected unipolar protection element, and the diode-connected bipolar protection element are connected in such a polarity that each is reverse-biased when the switching circuit is turned ON, and consume a discharge current resulting from a counter-electromotive force from the load when the switching circuit is turned OFF.

Abstract: A linear active cell region is formed from a plurality of divided active cell regions arranged apart from each other in a second direction (y direction). The linear hole collector cell region is formed from a plurality of divided hole collector cell regions arranged apart from each other in the second direction (y direction). A P-type floating region is formed in a semiconductor substrate between the linear active cell region and the linear hole collector cell region adjacent to each other in a first direction (x direction), between the divided active cell regions adjacent to each other in the second direction (y direction), and between the divided hole collector cell regions adjacent to each other in the second direction (y direction).

Abstract: Methods of forming a semiconductor structure include providing an insulation layer on a semiconductor layer and diffusing cesium ions into the insulation layer from a cesium ion source outside the insulation layer. A MOSFET including an insulation layer treated with cesium ions may exhibit increased inversion layer mobility.

Abstract: A bi-polar device is provided, along with methods of making the same. The bi-polar device can include a semiconductor substrate doped with a first dopant, a semiconductor layer on the first surface of the semiconductor substrate, and a Schottky barrier layer on the semiconductor layer. The method of forming a bi-polar device can include: forming a semiconductor layer on a first surface of a semiconductor substrate, where the semiconductor substrate comprises a first dopant and where the semiconductor layer comprises a second dopant that has an opposite polarity than the first dopant; and forming a Schottky barrier layer on a first portion of the semiconductor layer while leaving a second portion of the semiconductor layer exposed.

Abstract: The present disclosure relates to a thermal sensor and a method for producing a thermal sensor of this type having a low signal-to-noise ratio at relatively high signal strengths. To this end, a thermoelectric generator is combined with a field effect transistor and a diode. Owing to its integrated diode and the barrier effect associated therewith, the thermal sensor is suitable for the economical and efficient design of imaging sensor arrays for converting thermal radiation into electrical signals.

Abstract: A low dropout (LDO) device with improved linear mode comprising an error amplifier, a programmable attenuation factor circuit coupled to said error amplifier, a feedback network whose input is electrically connected to said programmable attenuation factor circuit and whose output is electrically coupled to the negative input of said error amplifier, a high side (HS) pre-drive circuit whose input is a high impedance (HiZ) mode signal, a low side (LS) pre-drive circuit whose input is a low pull-down input mode signal, a high side (HS) output stage element electrically coupled to said high side (HS) pre-drive circuit, a low side (LS) output stage element electrically coupled to said low side (LS) pre-drive circuit, and a high side sense (HSENSE) output stage element whose gate is electrically coupled to said high side (HS) pre-drive circuit, and whose gate and source are electrically connected to the output of said error amplifier.

Abstract: A semiconductor device includes a drift layer 20 of a first conductivity type, a base layer 30 of a second conductivity type that is disposed on the drift layer 20 and is connected to a source electrode 90, and a column layer 50 of a second conductivity type that is connected to the source electrode 90 and penetrates the base layer 30 to extend into the drift layer 20.

Abstract: A vertical power switching device, such as a vertical superjunction metal-oxide-semiconductor field-effect-transistor (MOSFET), in which termination structures in the corners of the integrated circuit are stretched to efficiently shape the lateral electric field. Termination structures in the device include such features as doped regions, field plates, insulator films, and high-voltage conductive regions and elements at the applied substrate voltage. Edges of these termination structures are shaped and placed according to a 2nd-order smooth, non-circular analytic function so as to extend deeper into the die corner from the core region of the device than a constant-distance path. Also disclosed are electrically floating guard rings in the termination region, to inhibit triggering of parasitic p-n-p-n structures.

Abstract: A semiconductor device with a deep trench has a dielectric liner formed on sidewalls and a bottom of the deep trench. A pre-etch deposition step of a two-step process forms a protective polymer on an existing top surface of the semiconductor device, and on the dielectric liner proximate to a top surface of the substrate. The pre-etch deposition step does not remove a significant amount of the dielectric liner from the bottom of the deep trench. A main etch step of the two-step process removes the dielectric liner at the bottom of the deep trench while maintaining the protective polymer at the top of the deep trench. The protective polymer is subsequently removed.

Abstract: Methods to form multi Vt channels, including a single type of WF material, utilizing lower annealing temperatures and the resulting devices are disclosed.

Abstract: There are disclosed herein implementations of an insulated-gate bipolar transistor (IGBT) having an inter-trench superjunction structure. Such an IGBT includes a drift region having a first conductivity type situated over a collector having a second conductivity type. The IGBT also includes first and second gate trenches extending through a base having the second conductivity type into the drift region, the first and second gate trenches each being bordered by an emitter diffusion having the first conductivity type. In addition, the IGBT includes an inter-trench superjunction structure situated in the drift region between the first and second gate trenches.

Abstract: A power metal oxide semiconductor (MOS) transistor die with a temperature sensing function and an integrated circuit are provided. The power MOS transistor die has a control terminal, a phase terminal, a ground terminal and a temperature signal output terminal, and that further includes a power switch part and a temperature sensing part. The power switch part has: a first electrode coupled to the control terminal; a second electrode coupled to the ground terminal; and a third electrode coupled to the phase terminal. The temperature sensing part has: a first electrode; a second electrode coupled to the temperature signal output terminal; and a third electrode coupled to the third electrode of the power switch part. The power switch part and the temperature sensing part are configured as a MOS transistor made by a same manufacturing process, and are capable of sensing temperature precisely.

Abstract: A semiconductor device of the present invention includes a semiconductor layer, a plurality of gate trenches formed in the semiconductor layer, a gate electrode filled via a gate insulating film in the plurality of gate trenches, an n+-type emitter region, a p-type base region, and an n?-type drift region disposed, lateral to each gate trench, in order in a depth direction of the gate trench from a front surface side of the semiconductor layer, a p+-type collector region disposed on a back surface side of the semiconductor layer with respect to the n?-type drift region, an emitter trench formed between the plurality of gate trenches adjacent to each other, and a buried electrode filled via an insulating film in the emitter trench, and electrically connected with the n+-type emitter region, and the emitter trench is disposed at an interval of 2 ?m or less via an n?-type drift region with the gate trench.

Abstract: An integrated circuit is formed on a substrate containing a semiconductor material having a first conductivity type. A deep well having a second, opposite, conductivity type is formed in the semiconductor material of the first conductivity type. A deep isolation trench is formed in the substrate through the deep well so as separate an unused portion of the deep well from a functional portion of the deep well. The functional portion of the deep well contains an active circuit element of the integrated circuit. The separated portion of the deep well does not contain an active circuit element. A contact region having the second conductivity type and a higher average doping density than the deep well is formed in the separated portion of the deep well. The contact region is connected to a voltage terminal of the integrated circuit.

Abstract: A semiconductor device which uses a fin-type semiconductor layer to form a bipolar transistor. The substrate of the device is a semiconductor substrate. A collector is a first-conductivity type impurity region which is formed in the semiconductor substrate. A base is a second-conductivity type impurity region which is formed in the surface layer of the collector. A first semiconductor layer is a fin-type semiconductor layer which lies over the base. An emitter is formed in the first semiconductor layer and its bottom is coupled to the base. A first contact is coupled to the collector, a second contact is coupled to the base, and a third contact is coupled to the emitter.

Abstract: An embodiment concerns forming an EPI film on a substrate where the EPI film has a different lattice constant from the substrate. The EPI film and substrate may include different materials to collectively form a hetero-epitaxial device having, for example, a Si and/or SiGe substrate and a III-V or IV film. The EPI film may be one of multiple EPI layers or films and the films may include different materials from one another and may directly contact one another. Further, the multiple EPI layers may be doped differently from another in terms of doping concentration and/or doping polarity. One embodiment includes creating a horizontally oriented hetero-epitaxial structure. Another embodiment includes a vertically oriented hetero-epitaxial structure. The hetero-epitaxial structures may include, for example, a bipolar junction transistor, heterojunction bipolar transistor, thyristor, and tunneling field effect transistor among others. Other embodiments are described herein.

Abstract: An integrated circuit formed on a silicon substrate includes an NMOS transistor with n-channel raised source and drain (NRSD) layers adjacent to a gate of the NMOS transistor, a PMOS transistor with SiGe stressors in the substrate adjacent to a gate of the PMOS transistor, and an NPN heterojunction bipolar transistor (NHBT) with a p-type SiGe base formed in the substrate and an n-type silicon emitter formed on the SiGe base. The SiGe stressors and the SiGe base are formed by silicon-germanium epitaxy. The NRSD layers and the silicon emitter are formed by silicon epitaxy.

Abstract: Various embodiments of a power MOS device structure are disclosed. In one aspect, a power MOS device structure includes a plurality of LDMOS and a plurality of bonding pads. The basic units of LDMOS are coupled in parallel and electrically coupled to the bonding pads to couple to a gate terminal, a source terminal, a drain terminal and a substrate of each of the basic units of LDMOS. The basic units of LDMOS are disposed below the bonding pads. The bonding pads include a single layer of metal with a thickness of 3.5 um to 4.5 um and a width of 1.5 um to 2.5 um. The region below the bonding pads of the power MOS device of the present disclosure is utilized to increase the number of basic units of LDMOS, thereby effectively reducing the on-resistance.

Abstract: A semiconductor device includes a single crystalline semiconductor body with a first surface and a second surface parallel to the first surface. The semiconductor body contains chalcogen atoms and a background doping of pnictogen and/or hydrogen atoms. A concentration of the chalcogen atoms is at least 1E12 cm?3. A ratio of the chalcogen atoms to the atoms of the background doping is in a range from 1:9 to 9:1.

Abstract: A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes.

Abstract: A triode includes a semiconductor, a deep n-well, a p-well, an n+ doping region, and a doping region. The deep n-well is disposed adjacent to the semiconductor substrate. The p-well is included in the deep n-well and serves as a collector region of the triode. The n+ doping region serves as a base region of the triode. The p+ doping region serves as an emitter region of the triode. The deep n-well is coupled to the n+ doping region via at least one conducting channel.

Abstract: Disclosed is a semiconductor component that includes a semiconductor body, a first emitter region of a first conductivity type in the semiconductor body, a second emitter region of a second conductivity type spaced apart from the first emitter region in a vertical direction of the semiconductor body, a base region of one conductivity type arranged between the first emitter region and the second emitter region, and at least two higher doped regions of the same conductivity type as the base region and arranged in the base region. The at least two higher doped regions are spaced apart from one another in a lateral direction of the semiconductor body and separated from one another only by sections of the base region.

Abstract: A semiconductor device includes a semiconductor body including a first surface having a normal direction defining a vertical direction, a first n-type semiconductor region arranged below the first surface and having a first maximum doping concentration and a second n-type semiconductor region arranged below the first n-type semiconductor region and including, in a vertical cross-section, two spaced apart first n-type portions each adjoining the first n-type semiconductor region, having a maximum doping concentration which is higher than the first maximum doping concentration and having a first minimum distance to the first surface, and a second n-type portion adjoining the first n-type semiconductor region, having a maximum doping concentration which is higher than the first maximum doping concentration and a second minimum distance to the first surface which is larger than the first minimum distance. A p-type second semiconductor layer forms a pn-junction with the second n-type portion.

Abstract: An integrated circuit includes a semiconductor substrate, a silicon layer, a buried isolating layer arranged between the substrate and the layer, a bipolar transistor comprising a collector and emitter having a first doping, and a base and a base contact having a second doping, the base forming a junction with the collector and emitter, the collector, emitter, base contact, and the base being coplanar, a well having the second doping and plumb with the collector, emitter, base contact and base, the well separating the collector, emitter and base contact from the substrate, having the second doping and extending between the base contact and base, a isolating trench plumb with the base and extending beyond the layer but without reaching a bottom of the emitter and collector, and another isolating trench arranged between the base contact, collector, and emitter, the trench extending beyond the buried layer into the well.

Abstract: One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures.

Abstract: In a semiconductor substrate of a semiconductor device, a drift layer, a body layer, an emitter layer, and a trench gate electrode are formed. When the semiconductor substrate is viewed in a plane manner, the semiconductor substrate is divided into a first region covered with a heat dissipation member, and a second region not covered with the heat dissipation member. A density of trench gate electrodes in the first region is equal to a density of trench gate electrodes in the second region. A value obtained by dividing an effective carrier amount of channel parts formed in the first region by an area of the first region is larger than a value obtained by dividing an effective carrier amount of channel parts formed in the second region by an area of the second region.