METHOD FOR FORMING A PLUG STRUCTURE AND RELATED PLUG STRUCTURE THEREOF
A method for forming a plug structure by utilizing a punching through process and the related plug structure are provided. An opening is defined in a substrate, and an unwanted oxide residue is disposed on a bottom of the opening. A glue layer is subsequently formed over the substrate. Portions of the glue layer are disposed on the sidewall and bottom of the opening, and cover the oxide. Thereafter, the portion of the first glue layer disposed at the bottom of the opening is punched through until the substrate is exposed so as to remove the oxide. Next, the opening is filled with a conductive structure.
1. Field of the Invention
The present invention relates to a method for forming a plug structure, and more particularly to a method of cleaning an opening by using a punching through process.
2. Description of the Prior Art
Currently, semiconductor devices are widely involved in many products and services in our daily life. These semiconductor devices are fabricated through many processes, such as photolithography, deposition, ion implantation, or etching, to form a plurality of integrated circuit (IC) devices on a wafer. In semiconductor fabrication on a wafer, an opening with a high aspect ratio, which is defined as a ratio of the depth to the width, is needed in some situations. The opening, such as a via hole or a contact hole, is formed in a dielectric layer and is filled with a metallic material, such as tungsten, to form a plug.
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Because the top corner of the plug hole 18 is over-rounded, a barrier bridge problem 30 is caused between contact plugs 28, as shown in
In order to prevent the barrier bridge problem 30 and remove the oxides 50, a F-base cleaning process is carried out instead of the argon cleaning process, as shown in
The existence of oxides reduces the device performance, and the short circuit even causes a failure of the device. Accordingly, it is desired to provide a cleaning method that does not deform the opening.
SUMMARY OF THE INVENTIONIt is therefore an objective of the present invention to provide a method for cleaning an opening and the related plug structure so that the formed product has a great performance.
It is an objective of the present invention to provide a method for forming a plug structure. First, a substrate is provided. The substrate has a dielectric layer, an opening defined in the dielectric layer. Subsequently, a first glue layer is formed over the substrate. The first glue layer is disposed at the bottom and sidewall of the opening. Next, a portion of the first glue layer disposed at the bottom of the opening is punched through until the substrate is exposed. Thereafter, the opening is filled with a conductive structure.
In accordance with another aspect of the present invention, a plug structure is provided. The plug structure includes a substrate, a material layer disposed on the substrate, an opening formed in the material layer, a glue layer covering a sidewall of the opening, a barrier layer covering a surface of the glue layer, and a plug filling the opening.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:
The method is suitable for cleaning any kind of opening in a semiconductor wafer, such as a via hole, a contact hole, a trench, or a damascene opening.
Please refer to
There are usually some unwanted oxides 50, such as native oxides, formed on the surface of the MOS device 114. For instance, the oxides 50 might be formed on the conducting regions 104 of the MOS device 114. These oxides 50 may degrade the electrical connection between the MOS device 114 and the subsequently formed contact plug in the opening 118. In addition, residues (not shown in the drawing) might also formed at the bottom of the opening 118 during an etching process of forming the opening 118, where the residues usually contains high-molecule polymers with carbon, silicon, nitrogen, fluorine, titanium, or other impurities.
The wafer 110 can also be taken as a semiconductor substrate, and can further include more devices or components (not shown in the drawing) therein. The substrate 112 can be made from semiconductor materials, such as a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator (SOI). The conducting regions 104 of the MOS device 114 can contain salicide, such as nickel silicide (NiSi), for reducing the contact resistance between the MOS device 114 and the following-formed plugs. It should be noted that the MOS device 114 could be replaced with any component or device, such as a diode, a capacitor, a resistor, or even a metallic structure, that should be electrically connected to a plug or to a trench. The dielectric layer 116 is usually sandwiched between one metal layer on the top and the substrate 112 at the bottom, or between two metal layers. The dielectric layer 116 can contain lower dielectric constant (low-k) materials, such as a silicon -containing layer including fluorinated silicate glass (FSG) or a carbon-containing layer including carbon-doped oxide (CDO). In other embodiment, the dielectric layer 116 can be replaced by other material layers.
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An opening having overhang structure may degrade the step coverage performance for the subsequent process for a formation of a plug. If the opening 118 has an overhang structure on each upper corner of the opening 118, the overhang structure can also be remove by utilizing the above-mentioned punching through process. The avoidance of the overhang structure of the glue layer on the upper corners of the opening can improve the step coverage performance.
It deserves to be mentioned that other portions of the glue layer 122 disposed on the surface of the dielectric layer 116 might also be removed in the above-mentioned punching through process. For example, the top surface of the dielectric layer 116 outside the opening 118 might be exposed in this embodiment after the punching through process. In other embodiments, portions of the glue layer 122 disposed on the sidewalls of the openings 118 might be removed, or portions of the glue layer 122 disposed on the top surface of the dielectric layer 116 might not be removed. The removed portions and the remained portions of the glue layer 122 can be modified by adjusting parameters of the punching through process or by a patterned hard mask.
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It is worthy of note that the fabrication of the barrier layer 124 can be eliminated in some embodiments. Please refer to
In other embodiments, another glue layer can be formed over the wafer 110 after the glue layer 122 is punched through. Please refer to
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The fabrication of the barrier layer 124 shown in
Portions of the barrier layer 124 shown in
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Furthermore, portions of the barrier layer 124 can be punched through immediately after the glue layer 122 is punched through in other embodiments. Please refer to
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In other embodiments, the fabrication of the barrier layer 134 shown in
In the above-mentioned embodiments, tungsten process is taken as examples to specifically illustrate the cleaning method of the present invention. In other embodiments, the utilized materials, the patterns of the openings, or the devices positioned under the plugs can be change or modified. For example, the present invention can be applied to a copper process. Please refer to
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In addition, it should be noted that a pre-cleaning process could be further performed before the deposition of the glue layer 122 in the above-mentioned embodiments. For example, an Ar pre-cleaning process or an F-base pre-cleaning process can be performed to remove portions of the oxides. In order to protect the structures of the openings, the Ar pre-cleaning process must be soft and delicate, and should not be performed for a long time, in which most of the oxides remain in the openings.
Since the present invention utilizes a punch through process to remove the unwanted oxides disposed at the bottom of the opening, there are some advantages for the present invention as following listed. First, the method can contain no Ar cleaning process nor F-base cleaning process that deforms the structure of the opening. Therefore, the contact profile of the plug structure is improved, and a short circuit between two plugs, and a short circuit between the plug and the lower device can be avoided. Subsequently, the unwanted oxides are easily and effectively removed, so the contact resistance between the plug and the lower device can be decreased. Furthermore, the step coverage for the glue layer and the step coverage for the barrier layer are also improved due to the punch through process. As a result, the device performance can be increased as desired by an IC design.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.
Claims
1. A method for forming a plug structure, the method comprising:
- providing a substrate, the substrate comprising a dielectric layer, an opening defined in the dielectric layer forming a first glue layer over the substrate, the first glue layer being disposed on a sidewall and the bottom of the opening;
- punching through a portion of the first glue layer disposed at the bottom of the opening until the substrate is exposed; and
- filling the opening with a conductive structure.
2. The method of claim 1, further comprising a step of forming a second glue layer over the substrate after the first glue layer is punched through.
3. The method of claim 2, further comprising a step of forming a barrier layer over the substrate after the second glue layer is formed.
4. The method of claim 1, further comprising a step of forming a barrier layer over the substrate after the first glue layer is punched through.
5. The method of claim 4, further comprising a step of punching through a portion of the barrier layer disposed at the bottom of the opening after the barrier layer is formed.
6. The method of claim 1, further comprising a step of forming a barrier layer over the substrate before the first glue layer is punched through.
7. The method of claim 6, wherein the step of punching through the portion of the first glue layer also punches through a portion of the barrier layer disposed at the bottom of the opening.
8. The method of claim 1, further comprising a step of performing a pre-cleaning process before the first glue layer is formed.
9. The method of claim 8, wherein the pre-cleaning process comprises an argon (Ar) or F-base pre-cleaning process.
10. The method of claim 1, wherein the step of punching through the portion of the first glue layer is performed by using an anisotropic etching process.
11. The method of claim 10, wherein the anisotropic etching process comprises a radio-frequency (RF) sputtering process.
12. The method of claim 1, wherein the first glue layer comprises titanium (Ti), tantalum (Ta), or tungsten (W).
13. The method of claim 3, wherein the barrier layer comprises titanium nitride, tantalum nitride, or tungsten nitride.
14. The method of claim 1, wherein the substrate further comprises a semiconductor device, and the semiconductor device comprises a conducting region; wherein the conducting region comprises nickel silicide (NiSi), and the conductive structure comprises tungsten.
15. A plug structure, comprising:
- a substrate;
- a dielectric layer disposed on the substrate;
- an opening defined in the dielectric layer;
- a glue layer covering a sidewall of the opening;
- a barrier layer covering a surface of the glue layer; and
- a conductive structure filling the opening.
16. The plug structure of claim 15, wherein the barrier layer covers a portion of the substrate at a bottom of the opening.
17. The plug structure of claim 15, wherein the conductive structure contacts a portion of the substrate at a bottom of the opening.
18. The plug structure of claim 15, wherein the conductive structure comprises a seed layer covering a surface of the barrier layer, and a conductive material filling the opening;
- wherein the seed layer and the conductive material comprise copper.
19. The plug structure of claim 16, wherein the substrate comprises a semiconductor device, and the semiconductor device comprises a conducting region; wherein the conducting region comprises nickel silicide, and the conductive structure comprises tungsten.
20. The plug structure of claim 15, wherein the glue layer comprises titanium, tantalum, or tungsten, and the barrier layer comprises titanium nitride, tantalum nitride, or tungsten nitride.
Type: Application
Filed: Oct 17, 2007
Publication Date: Apr 23, 2009
Inventor: Chao-Ching Hsieh (Tai-Nan City)
Application Number: 11/874,186
International Classification: H01L 21/4763 (20060101); H01L 23/48 (20060101);