Arrangements For Conducting Electric Current To Or From Solid-state Body In Operation, E.g., Leads, Terminal Arrangements (epo) Patents (Class 257/E23.01)
  • Patent number: 10712499
    Abstract: The present disclosure relates to packaging of integrated circuit chips for semiconductor devices. More particularly, the present disclosure relates to packaging of multiple chips for silicon photonics devices. The present disclosure provides a semiconductor device including a photonic integrated circuit (PIC) chip, an inductor positioned over the PIC chip, and a transimpedance amplifier (TIA) chip positioned over the PIC chip. The inductor has a first terminal end and a second terminal end, and the first terminal end is connected to the PIC chip.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: July 14, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Selaka Bandara Bulumulla, Md Sayed Kaysar Bin Rahim, Tanya Andreeva Atanasova
  • Patent number: 10658539
    Abstract: A light emitting diode device is described which includes at least one planar non-periodic high-index-contrast grating. The light emitting diode device includes a cavity formed between a reflective optical element and a transmissive optical element. One or both of the optical elements can be a planar non-periodic high-index-contrast grating. The transmissive optical element can be a collimating lens used to collimate incident beams of light while the reflective optical element can be a parabolic reflector used to reflect incident beams of light along a direction opposite to an incidence direction. A light emitter can be disposed within the cavity and can emit beams of light.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: May 19, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Zhen Peng, Nathaniel Quitoriano, Marco Fiorentino
  • Patent number: 10564354
    Abstract: The optical-electrical interconnection device comprises a glass support member with front-end and back-end portions that define a plane and an aperture. A cantilever member extends from the back-end portion into the aperture. The cantilever member supports an interconnection optical waveguide. The cantilever member comprises a bend region that causes a front-end section of the cantilever member to extend out of the plane. The front-end section is flexible, which allows for the interconnection optical waveguide to be aligned and optically coupled to a device waveguide of an optical-electrical device. A photonic assembly is formed using the optical-electrical interconnection device and at least one optical-electrical device. Methods of forming optical and electrical interconnections using the optical-electrical interconnection device are also disclosed.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: February 18, 2020
    Assignee: Corning Optical Communications LLC
    Inventors: Davide Domenico Fortusini, Scott Christopher Pollard, Alexander Mikhailovich Streltsov, James Scott Sutherland
  • Patent number: 10514499
    Abstract: A photonic chip includes a device layer and a port layer, with an optical port located at the port layer. Inter-layer optical couplers are provided for coupling light between the device and port layers. The inter-layer couplers may be configured to couple signal light but block pump light or other undesired wavelength from entering the device layer, operating as an input filter. The port layer may accommodate other light pre-processing functions, such as optical power splitting, that are undesirable in the device layer.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: December 24, 2019
    Assignee: Elenion Technologies, LLC
    Inventors: Ari Novack, Ruizhi Shi, Alexandre Horth, Ran Ding, Michael J. Hochberg
  • Patent number: 10353158
    Abstract: A light emitting element bonded board includes an optical waveguide formed within a board, a hollowed portion in the board, a light emitting element installed in the hollowed portion, and a conductive portion formed in an upper layer and/or a lower layer of the optical waveguide, wherein an optical axis of the light emitting element coincides with a center line of the optical waveguide, and a bonding portion of the light emitting element is bonded to the conductive portion.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: July 16, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Yoshiyuki Hiroshima, Akiko Matsui, Mitsuhiko Sugane, Takahide Mukoyama, Tetsuro Yamada, Kohei Choraku
  • Patent number: 10285270
    Abstract: A rigid flex circuit comprised of high thermal conductivity sections, said sections having components disposed so as to have their contacts substantially planar with the surface of the thermally conductive section and wherein the contacts are interconnected directly to the traces without the use of solder and further having the thermally conductive sections interconnected to one another by means of flexible circuit sections.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: May 7, 2019
    Inventor: Joseph Fjelstad
  • Patent number: 10217041
    Abstract: A radio-frequency identification device for identifying a tubular element is provided that includes a radio-frequency identification chip connected to at least one antenna having two conductive strands and a flexible envelope enveloping the radio-frequency identification chip and strands. The envelope is a silicone material and includes a central portion overmolding the radio-frequency identification chip, and two strips extend on either side of the central portion and each strip overmolds at least one strand. Each of the two strips has a free end with a pierced boss capable of cooperating with a hose clamp. The two strips are thermoformed in a twisted configuration around a common twisting axis.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: February 26, 2019
    Assignee: SYSTEMES ET TECHNOLOGIES IDENTIFICATION (STID)
    Inventors: Vincent Dupart, Aurélie Margalef, Sylvain Poitrat
  • Patent number: 10121847
    Abstract: A galvanic isolation device includes a first integrated circuit (IC) die that has communication circuitry formed in a circuit layer below the top surface. A first conductive plate is formed on the IC die proximate the top surface, and is coupled to the communication circuitry. A dielectric isolation layer is formed over a portion of the top surface of the IC after the IC is fabricated such that the dielectric isolation layer completely covers the conductive plate. A second conductive plate is juxtaposed with the first conductive plate but separated by the dielectric isolation layer such that the first conductive plate and the second conductive plate form a capacitor. The second conductive plate is configured to be coupled to a second communication circuit.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: November 6, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Stassen Cook, Barry Jon Male, Robert Alan Neidorff
  • Patent number: 10026682
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: July 17, 2018
    Assignee: Intel Corporation
    Inventors: Zhiguo Qian, Kemal Aygun, Yu Zhang
  • Patent number: 10025029
    Abstract: An optoelectronic device includes an integrated circuit including electronic devices formed on a front side of a semiconductor substrate. A barrier layer is formed on a back side of the semiconductor substrate. A photonics layer is formed on the barrier layer. The photonics layer includes a core for transmission of light and a cladding layer encapsulating the core and including a different index of refraction than the core. The core is configured to couple light generated from a component of the optoelectronic device.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: July 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Russell A. Budd, Effendi Leobandung, Ning Li, Jean-Olivier Plouchart, Devendra K. Sadana
  • Patent number: 9997504
    Abstract: In one general aspect, an electronic device module includes a first board, a first device mounted on a first surface of the first board, a second board disposed below the first board, and a plurality of second devices disposed between the first board and the second board, wherein a surface of each second device the plurality of second devices is bonded to a second surface of the first board and another surface of each of the second devices is bonded to the second board.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: June 12, 2018
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jae Hyun Lim, Jong In Ryu, Sung Ho Kim, Jin Su Kim
  • Patent number: 9885827
    Abstract: Apparatuses and methods for photonic communication and photonic addressing are disclosed herein. An example apparatus includes a plurality of photonic sources, a plurality of memory die, a logic die, Each of the plurality of photonic sources provides a photonic signal of a different wavelength and are provided to a first photonic path. Each memory die of the plurality of memory die includes a photonic modulation circuit coupled to the first photonic path, and further includes a photonic detector circuit coupled to a second photonic path. Each memory die of the plurality of memory die is associated with and addressed by a respective wavelength of a photonic signal. The logic die is coupled to the first and second photonic paths, and includes a plurality of photonic circuits. Each of the photonic circuits of the plurality of photonic circuits is associated with a respective wavelength of a photonic signal.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: February 6, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Sion Quinlan
  • Patent number: 9786641
    Abstract: Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For example, a package structure includes an integrated circuit (IC) chip, and an optoelectronics device and interposer mounted to the IC chip. The IC chip includes a SOI substrate having a buried oxide layer, an active silicon layer disposed adjacent to the buried oxide layer, and a BEOL structure formed over the active silicon layer. An optical waveguide structure is patterned from the active silicon layer of the IC chip. The optoelectronics device is mounted on the buried oxide layer in alignment with a portion of the optical waveguide structure to enable direct or adiabatic coupling between the optoelectronics device and the optical waveguide structure. The interposer is bonded to the BEOL structure, and includes at least one substrate having conductive vias and wiring to provide electrical connections to the BEOL structure.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: October 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Russell A. Budd, Mounir Meghelli, Jason Scott Orcutt, Jean-Olivier Plouchart
  • Patent number: 9739939
    Abstract: Apparatuses and methods for photonic communication and photonic addressing are disclosed herein. An example apparatus includes a photonic source layer that provides a plurality of photonic sources, each at a different wavelength, a plurality of second layers, and a third layer. Each of the plurality of second layers may be associated with a respective wavelength, and each of the plurality of second layers may include photonic filters tuned to their respective wavelength, a photonic modulator, and a photonic detector. The third layer may include a plurality of photonic circuits, with each of the plurality of photonic circuits associated with a respective second layer of the plurality of second layers. Additionally, each of the plurality of photonic circuits may include a photonic filter tuned to a respective wavelength associated with a respective second layer, a photonic detector and a photonic modulator.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: August 22, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Sion Quinlan
  • Patent number: 9715062
    Abstract: An optical axis adjustment method for optical interconnection, includes: providing, on a substrate, an optical transmitter including light sources and a mark for acquiring a position of each of the light sources; providing, on the substrate, an optical waveguide including cores each allowing light emitted from the respective light sources to propagate through the core; determining a first position based on the mark as a position of each of the light sources; and forming, at a second position in the optical waveguide corresponding to the first position, first mirrors configured to reflect the light emitted from the respective light sources and make the light propagate through the respective cores.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: July 25, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Kohei Choraku, Akiko Matsui, Tetsuro Yamada, Yoshiyuki Hiroshima
  • Patent number: 9693124
    Abstract: A macro-switch is described. This macro-switch includes facing integrated circuits, one of which implements optical waveguides that convey optical signals, and the other which implements control logic, electrical switches and memory buffers at each of multiple switch sites. Moreover, the macro-switch has a fully connected topology between the switch sites. Furthermore, the memory buffers at each switch site provide packet buffering and congestion relief without causing undue scheduling/routing complexity. Consequently, the macro-switch can be scaled to an arbitrarily large switching matrix (i.e., an arbitrary number of switch sites and/or switching stages).
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: June 27, 2017
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Leick D. Robinson, Avadh Pratham Patel, Ashok V. Krishnamoorthy, Alan P. Wood
  • Patent number: 9660147
    Abstract: The present invention relates to a method for providing a reflective coating (114) to a substrate (104) for a light-emitting device (112), comprising the steps of: providing (201) a substrate (104) having a first surface portion (116) with a first surface material and a second surface portion (106, 108) with a second surface material different from the first surface material; applying (202) a reflective compound (401) configured to attach to said first surface material to form a bond with the substrate (104) in the first surface portion (116) that is stronger than a bond between the reflective compound (401) and the substrate (104) in the second surface portion (106, 108); curing (203) said reflective compound (401) to form a reflective coating (114) having said bond between the reflective coating (114) and the substrate (104) in the first surface portion (116); and subjecting said substrate (104) to a mechanical treatment with such an intensity as to remove (205) said reflective coating (114) from said secon
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: May 23, 2017
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventors: Hendrik Johannes Boudewijn Jagt, Christian Kleijnen
  • Patent number: 9648399
    Abstract: The present disclosure relates to a system having a plurality of electronic devices interconnected by way of dielectric waveguides. In some embodiments, the system has a plurality of electronic devices respectively including a data element and a multiplexing element. The data element has a plurality of electronic device terminals that output and receive data. The multiplexing element provides the data output from the plurality of electronic device terminals to a transceiver element, which generates a wireless signal that transmits the data in a manner that distinctly identifies data from different electronic device terminals. A plurality of dielectric waveguides are disposed at locations between the plurality of electronic devices. The plurality of dielectric waveguides convey the wireless signal between the plurality of electronic devices. By interconnecting electronic devices using dielectric waveguides, disadvantages associates with metal interconnect wires can be mitigated.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: May 9, 2017
    Assignee: Infineon Technologies AG
    Inventors: Harald Witschnig, Dirk Hammerschmidt, David Levy
  • Patent number: 9560763
    Abstract: A package for optical module includes a flat-plate-shaped metal base, and a ceramic circuit board in which a plurality of terminals are arranged in a longitudinal direction, and which is joined to an upper surface of the metal base by soldering. The ceramic circuit board has a shape change portion in which the ceramic circuit board is changed in shape along the longitudinal direction, and a region of the ceramic circuit board not including the shape change portion is joined to the metal base by soldering. The shape change portion of the ceramic circuit board is a portion where a width is changed along the longitudinal direction, or a portion where a thickness is changed along the longitudinal direction.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: January 31, 2017
    Assignees: Nippon Telegraph and Telephone Corporation, NTT Electronics corporation
    Inventors: Ikuo Ogawa, Ryoichi Kasahara, Toshiki Nishizawa, Yuji Mitsuhashi
  • Patent number: 9444510
    Abstract: A circuit including a first die, an integrated passive device and a second layer. The first die includes a first substrate and active devices. The integrated passive device includes a first layer, a second substrate and passive devices. The second substrate includes vias. The passive devices are implemented at least on the first layer or the second substrate. A resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate. The second layer is disposed between the first die and the integrated passive device. The second layer includes pillars. Each of the pillars connects a corresponding one of the active devices to (i) one of the vias, or (ii) one of the passive devices. The first die, the integrated passive device and the second layer are disposed relative to each other to form a stack.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: September 13, 2016
    Assignee: MARVELL WORLD TRADE LTD.
    Inventors: Poh Boon Leong, Albert Wu, Long-Ching Wang, Sehat Sutardja
  • Patent number: 9184840
    Abstract: An optical module includes first optical elements disposed on a first surface side of optical waveguides, first signal wirings disposed on the first surface side in parallel with each other in a direction intersecting with a transmission direction of an electrical signal transmitted by a first signal wiring, second optical elements disposed on a second surface side of the optical waveguides, and second signal wirings disposed on the second surface side in parallel with each other in a direction intersecting with a transmission direction of an electrical signal transmitted by a second signal wirings, the optical waveguides being disposed in parallel with each other in a direction intersecting with an optical waveguide direction of an optical signal guided by an optical waveguide at an interval which is narrower than an interval between the adjacent first signal wirings and narrower than an interval between the adjacent second signal wirings.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: November 10, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Takashi Shiraishi, Takatoshi Yagisawa
  • Patent number: 9040346
    Abstract: In one embodiment, a semiconductor package includes a semiconductor chip having a first contact region on a first major surface and a second contact region on an opposite second major surface. The semiconductor chip is configured to regulate flow of a current from the first contact region to the second contact region. An encapsulant is disposed at the semiconductor chip. A first contact plug is disposed within the encapsulant and coupled to the first contact region. A second side conductive layer is disposed under the second major surface and coupled to the second contact region. A through via is disposed within the encapsulant and coupled to the second side conductive layer. The first contact plug and the through via form terminals above the first major surface for contacting the semiconductor package.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ivan Nikitin, Edward Fuergut
  • Patent number: 9041185
    Abstract: A semiconductor device includes a substrate, a first land formed in a first surface of the substrate, a second land formed in a second surface of the substrate, a first terminal coupled to the second land, a line coupled to the first land and the second land, a second terminal formed in the second surface of the substrate and a branch line coupled to the line and the second terminal. The second terminal is coupled to the first land and the second land and is not coupled to other lands in the first surface. The second surface is different surface from the first surface.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: May 26, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Naoto Akiyama, Toshiaki Umeshima
  • Patent number: 9035466
    Abstract: The present invention provides a dicing tape-integrated film for semiconductor back surface, which includes: a dicing tape including a base material and a pressure-sensitive adhesive layer provided on the base material; and a film for flip chip type semiconductor back surface provided on the pressure-sensitive adhesive layer, in which the film for flip chip type semiconductor back surface contains a black pigment.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: May 19, 2015
    Assignee: NITTO DENKO CORPORATION
    Inventors: Naohide Takamoto, Takeshi Matsumura, Goji Shiga
  • Patent number: 9030020
    Abstract: In one embodiment, a semiconductor memory device includes a substrate, and device regions formed in the substrate to extend in a first direction which is parallel to a principal plane of the substrate. The device further includes select gates disposed on the substrate to extend in a second direction which is perpendicular to the first direction, and a contact region provided between the select gates on the substrate and including contact plugs disposed on the respective device regions. Further, the contact region includes partial regions, in each of which N contact plugs are disposed on N successive device regions to be arranged on a straight line being non-parallel to the first and second directions, where N is an integer of 2 or more. Further, the contact region includes the partial regions of at least two types whose values of N are different.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: May 12, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiko Kato, Hidenobu Nagashima
  • Patent number: 9029903
    Abstract: A light emitting diode package including a package body with a cavity, a plurality of light emitting diode (LED) chips in the cavity, a plurality of wires connected to the plurality of LED chips, and a plurality of lead frames in the package body, wherein the lead frames comprise a first lead frame electrically connected to a first electrode of a first LED chip, a second lead frame electrically connected to a second electrode of the first LED chip and a second electrode of a second LED chip, a third lead frame electrically connected to a first electrode of the second LED chip, and fourth lead frame electrically connected to a second electrode of a third LED chip. Further, ends of the lead frames are exposed outside of the package body and penetrate the package body, and the first electrodes are P electrodes and the second electrodes are N electrodes.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: May 12, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: Won-Jin Son
  • Patent number: 9029993
    Abstract: A semiconductor device includes a lead frame, a semiconductor chip, a substrate, a plurality of chip parts, a plurality of wires, and a resin member. The lead frame includes a chip mounted section and a plurality of lead sections. The semiconductor chip is mounted on the chip mounted section. The substrate is mounted on the chip mounted section. The chip parts are mounted on the substrate. Each of the chip parts has a first end portion and a second end portion in one direction, and each of the chip parts has a first electrode at the first end portion and a second electrode at the second end portion. Each of the wires couples the second electrode of one of the chip parts and one of the lead sections. The resin member covers the lead frame, the semiconductor chip, the substrate, the chip parts, and the wires.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: May 12, 2015
    Assignee: DENSO CORPORATION
    Inventors: Masao Yamada, Tetsuo Fujii
  • Patent number: 9018759
    Abstract: A semiconductor package substrate including a substrate body having a front surface configured for mounting a semiconductor chip on the front surface and a rear surface facing the front surface and comprising a window passing through the front and rear surfaces, the window having one or more surfaces inclined from the front surface toward the rear surface; and a conductive pattern arranged along an inclined surface of the window so as to extend from the front surface to the rear surface of the substrate body.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: April 28, 2015
    Assignee: SK Hynix Inc.
    Inventor: Jong Hoon Kim
  • Patent number: 9018044
    Abstract: In one embodiment, a chip-on-lead package structures includes an electronic chip having opposing major surfaces. One major surface of the electronic chip is attached to first and second leads. The one major surface is electrically connected to the first lead, and electrically isolated from the second lead. The other major surface where active device are formed may be electrically connected to the second lead.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: April 28, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Atapol Prajuckamol, Bih Wen Fon, Jun Keat Lee
  • Patent number: 9006869
    Abstract: A light emitting device package is provided comprising a light emitting device including at least one light emitting diode and a body including a first lead frame on which the light emitting device is mounted and a second lead frame spaced apart from the first lead frame, wherein at least one of the first and second lead frames is extending to a bending region in a first direction by a predetermined length on the basis of an outer surface of the body and is bent in a second direction intersecting the first direction.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: April 14, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: JaeJoon Yoon
  • Patent number: 9000582
    Abstract: A power semiconductor module includes: a circuit body having a power semiconductor element and a conductor member connected to the power semiconductor element; a case in which the circuit body is housed; and a connecting member which connects the circuit body and the case. The case includes: a first heat dissipating member and a second heat dissipating member which are disposed in opposed relation to each other while interposing the circuit body in between; a side wall which joins the first heat dissipating member and the second heat dissipating member; and an intermediate member which is formed on the periphery of the first heat dissipating member and connected to the side wall, the intermediate member including a curvature that is projected toward a housing space of the case.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: April 7, 2015
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Shinji Hiramitsu, Atsushi Koshizaka, Masato Higuma, Hiroshi Tokuda, Keiji Kawahara
  • Patent number: 8994176
    Abstract: Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of the interposer substrate. A dam surrounds an area where connectors such as solder balls may be located to connect to other packages. A non-conductive dam may be formed above the dam. An underfill may be formed under the package connected to the connector, above the metal layer, and contained within the area surrounded by the dams at the corner, so that the connectors are well protected by the underfill. Such dams may be further formed on a printed circuit board as well.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chiang Wu, Hsien-Wei Chen, Yu-Feng Chen, Chun-Hung Lin, Ming-Kai Liu, Chun-Lin Lu
  • Patent number: 8994161
    Abstract: Some embodiments have a semiconductor chip supported above a substrate, a filler layer encapsulating the semiconductor chip, a heat sink; and through contacts extending upwardly from the substrate nearly to an upper surface of the filler layer. In some embodiments of electronic packages, the through contacts separated from the heat sink by a trench cut into the upper surface of the filler layer, the through contacts intersecting one wall of the trench and the heat sink intersecting the other wall of the trench an electronic semiconductor package. A method of forming the package and a lead frame are also disclosed.
    Type: Grant
    Filed: January 2, 2007
    Date of Patent: March 31, 2015
    Assignee: Infineon Technologies AG
    Inventors: Michael Ahr, Bakuri Lanchava
  • Patent number: 8987913
    Abstract: Disclosed herein is a deformable network structure, which includes a first device portion, a second device portion and at least one connector interconnecting between the first device portion and the second device portion. Moreover, the second device portion can be electrically connected to the first device portion through one of the connectors. The first and second device portions respectively have a first and a second center. Each of the connectors may be deformable from an initial state to a final state, such that a first distance between the first and second centers in the final state varies by at least 10% of a second distance between the first and second centers in the initial state.
    Type: Grant
    Filed: May 27, 2013
    Date of Patent: March 24, 2015
    Assignee: MonoLithe Semiconductor Inc.
    Inventors: Kevin T. Y. Huang, Hsiao-Huey Huang
  • Patent number: 8987921
    Abstract: A method for producing a component with at least one micro-structured or nano-structured element includes applying at least one micro-structured or nano-structured element to a carrier. The element has at least one area configure to make contact and the element is applied to the carrier such that the at least one area adjoins the carrier. The element is enveloped in an enveloping compound and the element-enveloping compound composite is detached from the carrier. A first layer comprising electrically conductive areas is applied to the side of the element-enveloping compound composite that previously adjoined the carrier. At least one passage is introduced into the enveloping compound. A conductor layer is applied to the surface of the passage and at least to a section of the layer comprising the first electrically conductive areas to generate a through contact, which enables space-saving contacting. A component is formed from the method.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: March 24, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Ulrike Scholz, Ralf Reichenbach
  • Patent number: 8975749
    Abstract: A method of making a semiconductor device includes forming a dielectric layer over a semiconductor substrate. The method further includes forming a copper-containing layer in the dielectric layer, wherein the copper-containing layer has a first portion and a second portion. The method further includes forming a first barrier layer between the first portion of the copper-containing layer and the dielectric layer. The method further includes forming a second barrier layer at a boundary between the second portion of the copper-containing layer and the dielectric layer wherein the second barrier layer is adjacent to an exposed portion of the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer, and a boundary between a sidewall of the copper-containing layer and the first barrier layer is free of the second barrier layer.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Wei Liu, Zhen-Cheng Wu, Cheng-Lin Huang, Po-Hsiang Huang, Yung-Chih Wang, Shu-Hui Su, Dian-Hau Chen, Yuh-Jier Mii
  • Patent number: 8975735
    Abstract: A redistribution board includes a first conductive layer including a redistribution structure for low voltage signals, a second conductive layer including a redistribution structure for high voltage signals, and a non-conductive layer. The second conductive layer is spaced apart from the first conductive layer by the non-conductive layer. The redistribution board further includes a conductive connector extending from a mounting surface of the redistribution board to the second conductive layer. The conductive connector is surrounded by a low voltage trace of the first conductive layer.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: March 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef Höglauer
  • Patent number: 8970031
    Abstract: A method of making semiconductor die terminals and a semiconductor device with die terminals made according to the present method. At least a first mask layer is selectively printed on at least a portion of a wafer containing a plurality of the semiconductor devices to create first recesses aligned with electrical terminals on the semiconductor devices. A conductive material is deposited in a plurality of the first recesses to form die terminals on the semiconductor devices. The first mask layer is removed to expose the die terminals, and the wafer is diced into a plurality of discrete semiconductor devices.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: March 3, 2015
    Assignee: Hsio Technologies, LLC
    Inventor: James Rathburn
  • Patent number: 8970033
    Abstract: A device includes a work piece, and a metal trace on a surface of the work piece. A Bump-on-Trace (BOT) is formed at the surface of the work piece. The BOT structure includes a metal bump, and a solder bump bonding the metal bump to a portion of the metal trace. The metal trace includes a metal trace extension not covered by the solder bump.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Feng Chen, Yuh Chern Shieh, Tsung-Shu Lin, Han-Ping Pu, Jiun Yi Wu, Tin-Hao Kuo
  • Patent number: 8963332
    Abstract: A semiconductor device includes a first main strap, a second main strap, a plurality of first sub straps, a plurality of second sub straps, and a plurality of dummy lines. The first main strap is extended in a first direction. The second main strap is extended in the first direction. A plurality of first sub straps is branched from the first main strap. The plurality of second sub straps is branched from the second main strap. The plurality of dummy lines is positioned between the first main strap and the second main strap. Each of the plurality of dummy lines is positioned between each of the plurality of first sub straps and each of the plurality of second sub straps. Each of the dummy lines is spaced apart from the first main strap, the second main strap, each of the first sub straps and each of the second sub straps.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Soo Kim, Byung-Hee Kim
  • Patent number: 8945986
    Abstract: One method of making an electronic assembly includes mounting one electrical substrate on another electrical substrate with a face surface on the one substrate oriented transversely of a face surface of the other substrate. The method also includes inkjet printing on the face surfaces a conductive trace that connects an electrical contact on the one substrate with an electrical connector on the other substrate. An electronic assembly may include a first substrate having a generally flat surface with a first plurality of electrical contacts thereon; a second substrate having a generally flat surface with a second plurality of electrical contacts thereon, the surface of the second substrate extending transversely of the surface of said first substrate; and at least one continuous conductive ink trace electrically connecting at least one of the first plurality of electrical contacts with at least one of the second plurality of electrical contacts.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: February 3, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Matthew David Romig, Lance Cole Wright, Leslie Edward Stark, Frank Stepniak, Sreenivasan K. Koduri
  • Patent number: 8946832
    Abstract: A representative filter comprises a silicon-on-insulator substrate having a top surface, a metal shielding positioned above the top surface of the silicon-on-insulator substrate, and a band-pass filter device positioned above the metal shielding. The band-pass filter device includes a first port, a second port, and a coupling metal positioned between the first and second ports.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Chung Chen, Chewn-Pu Jou, Chin-Wei Kuo
  • Patent number: 8945983
    Abstract: A method embodiment includes forming a packaging unit by attaching a die to a packaging substrate, applying plasma treatment to a first portion of the packaging substrate, wherein the first portion corresponds to a portion of the packaging substrate underneath the die, not applying plasma treatment to a second portion of the packaging substrate, wherein the second portion of the packaging substrate surrounds the first portion of the packaging substrate, and applying an underfill material over the first portion of the packaging substrate.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Hsin Liu, Cing He Chen, Kewei Zuo, Chien Rhone Wang
  • Patent number: 8946870
    Abstract: A semiconductor die has a first semiconductor die mounted to a carrier. A plurality of conductive pillars is formed over the carrier around the first die. An encapsulant is deposited over the first die and conductive pillars. A first stepped interconnect layer is formed over a first surface of the encapsulant and first die. The first stepped interconnect layer has a first opening. A second stepped interconnect layer is formed over the first stepped interconnect layer. The second stepped interconnect layer has a second opening. The carrier is removed. A build-up interconnect structure is formed over a second surface of the encapsulant and first die. A second semiconductor die over the first semiconductor die and partially within the first opening. A third semiconductor die is mounted over the second die and partially within the second opening. A fourth semiconductor die is mounted over the second stepped interconnect layer.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: February 3, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Byung Tai Do, Linda Pei Ee Chua
  • Patent number: 8941152
    Abstract: A method of forming a semiconductor device comprises forming a base wafer comprising a first chip package portion, a second chip package portion, and a third chip package portion. The method also comprises forming a capping wafer comprising a plurality of isolation trenches, each of the plurality of isolation trenches being configured to substantially align with one of the first chip package portion, the second chip package portion or the third chip package portion. The method further comprises eutectic bonding the capping wafer and the base wafer to form a wafer package. The method additionally comprises dicing the wafer package into a first chip package, a second chip package, and a third chip package. The method also comprises placing the first chip package, the second chip package, and the third chip package onto a substrate.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-wen Cheng, Jung-Huei Peng, Shang-Ying Tsai, Hung-Chia Tsai, Yi-Chuan Teng
  • Patent number: 8937386
    Abstract: The formation of the conductive wire of a chip package consists of a plurality of steps. Coat a first dielectric layer on the pad-mounting surface and a slot is formed on each bonding pad correspondingly. Then coat a second dielectric layer and produce a wiring slot corresponding to each bonding pad and the slot thereof. Next each wiring slot is filled with electrically conductive metal so as to form a conductive wire. Later Coat a third dielectric layer and a corresponding slot is formed on one end of each conductive wire while this slot is filled with electrically conductive metal to form a solder point. The above steps can further be repeated so as to form an upper-layer and a lower-layer conductive wire. Thereby precision of the chip package, use efficiency of the wafer and yield rate of manufacturing processes are all improved.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: January 20, 2015
    Assignee: Aflash Technology Co., Ltd.
    Inventors: Tse-Ming Chu, Sung-Chuan Ma
  • Patent number: 8937387
    Abstract: The disclosure concerns a semiconductor device having conductive vias. In an embodiment, the semiconductor device includes a substrate having at least one conductive via formed therein. The conductive via has a first end substantially coplanar with an inactive surface of the substrate. A circuit layer is disposed adjacent to an active surface of the substrate and electrically connected to a second end of the conductive via. A redistribution layer is disposed adjacent to the inactive surface of the substrate, the redistribution layer having a first portion disposed on the first end an electrically connected thereto, and a second portion positioned upward and away from the first portion. A die is disposed adjacent to the inactive surface of the substrate and electrically connected to the second portion of the redistribution layer.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: January 20, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Che-Hau Huang, Ying-Te Ou
  • Patent number: 8933552
    Abstract: In one embodiment, a semiconductor package comprising a metal base coupled to one or more pins, a semiconductor body having a top side and a bottom side, the top side comprising an integrated circuit and one or more metal surfaces for coupling the integrated circuit to the one more pins with one or more bonding wires, the bottom side non-positively coupled to the metal base, a disk having a top area and a base area, the base area coupled to the top side of the semiconductor body and at least partially covering the integrated circuit, the disk being electrically insulated from the semiconductor body, and a plastic compound completely enclosing the one or more bonding wires, and at least partially enclosing the top side of the integrated circuit, the top area of the disk, and the one or more pins.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: January 13, 2015
    Assignee: Atmel Corporation
    Inventor: Gerald Krimmer
  • Patent number: 8927333
    Abstract: A package-on-package arrangement for maintaining die alignment during a reflow operation is provided. A first top die has a first arrangement of solder bumps. A bottom package has a first electrical arrangement to electrically connect to the first arrangement of solder bumps. A die carrier has a plurality of mounting regions defined on its bottom surface, wherein the first top die is adhered to the die carrier at a first of the plurality of mounting regions. One of a second top die and a dummy die having a second arrangement of solder bumps is also fixed to the die carrier at a second of the plurality of mounting regions of the die carrier. The first and second arrangements of solder bumps are symmetric to one another, therein balancing a surface tension during a reflow operation, and generally fixing an orientation of the die carrier with respect to the bottom package.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Shu Lin, Yu-Ling Tsai, Han-Ping Pu
  • Patent number: 8928129
    Abstract: A semiconductor device includes a substrate, a semiconductor chip, a first molding member and a metal layer. The substrate includes a first ground pad formed therein, the first ground pad having a first exposed surface exposed at a first surface of the substrate. The semiconductor chip is formed on the first surface of the substrate. The first molding member is formed on the first surface of the substrate and covers the semiconductor chip while not covering the first exposed surface. The metal layer covers the first molding member and extends to lateral surfaces of the substrate while contacting the first exposed surface.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: In-Sang Song