Plug Formation (i.e., In Viahole) Patents (Class 438/672)
  • Patent number: 10566232
    Abstract: Implementations of the present disclosure provide methods for preventing contact damage or oxidation after via/trench opening formation. In one example, the method includes forming an opening in a structure on the substrate to expose a portion of a surface of an electrically conductive feature, and bombarding a surface of a mask layer of the structure using energy species formed from a plasma to release reactive species from the mask layer, wherein the released reactive species form a barrier layer on the exposed surface of the electrically conductive feature.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: February 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bo-Jhih Shen, Yi-Wei Chiu, Hung Jui Chang
  • Patent number: 10510804
    Abstract: The present disclosure provides a semiconductor structure including a substrate, a transistor region having a gate over the substrate and a doped region at least partially in the substrate, a first metal layer over the transistor region, and a magnetic tunneling junction (MTJ) between the transistor region and the first metal layer. The present disclosure provides a method for manufacturing a semiconductor structure, including forming a transistor region over a substrate, the transistor region comprising a gate and a doped region, forming a magnetic tunneling junction (MTJ) over the transistor region, electrically coupling to the transistor region, and forming a first metal layer over the MTJ, electrically coupling to the MTJ and the transistor region.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Alexander Kalnitsky, Harry-Hak-Lay Chuang, Sheng-Haung Huang, Tien-Wei Chiang
  • Patent number: 10176996
    Abstract: Embodiments of the present invention provide a replacement metal gate and a fabrication process with reduced lithography steps. Using selective etching techniques, a layer of fill metal is used to protect the dielectric layer in the trenches, eliminating the need for some lithography steps. This, in turn, reduces the overall cost and complexity of fabrication. Furthermore, additional protection is provided during etching, which serves to improve product yield.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: January 8, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Min Gyu Sung, Chanro Park, Hoon Kim
  • Patent number: 10177131
    Abstract: Provided are a semiconductor package and a method of manufacturing the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, an interconnect substrate spaced apart from the semiconductor chip on the substrate and including a conductive member therein, a solder ball on the interconnect substrate and electrically connected to the conductive member, a polymer layer on the interconnect substrate and the semiconductor chip and including an opening through which the solder ball is exposed, and polymer particles in the solder ball and including the same material as the polymer layer.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: January 8, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Lyong Kim, Jin-woo Park, Choongbin Yim, Younji Min
  • Patent number: 10128237
    Abstract: A method of forming a semiconductor device includes forming a plurality of fins on a substrate, forming a polysilicon gate structure, and replacing the polysilicon gate structure with a metal gate structure. Replacing the polysilicon gate structure includes depositing a work function metal layer over the plurality of fins, forming a metal oxide layer over the work function metal layer, and depositing a first metal layer over the metal oxide layer. A first portion of the metal oxide layer is formed within an area between adjacent fins from among the plurality of fins. An example benefit includes reduced diffusion of unwanted and/or detrimental elements from the first metal layer into its underlying layers and consequently, the reduction of the negative impact of these unwanted and/or detrimental elements on the semiconductor device performance.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: November 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh Wen Tsau, Chia-Ching Lee, Chung-Chiang Wu, Da-Yuan Lee
  • Patent number: 10103171
    Abstract: An integrated circuit containing elongated contacts, including elongated contacts which connect to at least three active areas and/or MOS gates, and including elongated contacts which connect to exactly two active areas and/or MOS gates and directly connect to a first level interconnect. A process of forming an integrated circuit containing elongated contacts, including elongated contacts which connect to at least three active areas and/or MOS gates, using exactly two contact photolithographic exposure operations, and including elongated contacts which connect to exactly two active areas and/or MOS gates and directly connect to a first level interconnect.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: October 16, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: James Walter Blatchford, Scott William Jessen
  • Patent number: 10056291
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to post spacer self-aligned cut structures and methods of manufacture. The method includes: providing a non-mandrel cut; providing a mandrel cut; forming blocking material on underlying conductive material in the non-mandrel cut and the mandrel cut; forming trenches with the blocking material acting as a blocking mask at the mandrel cut and the non-mandrel cut; and filling the trenches with metallization features such that the metallization features have a tip to tip alignment.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: August 21, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shao Beng Law, Xunyuan Zhang, Frank W. Mont, Genevieve Beique, Lei Sun
  • Patent number: 9905574
    Abstract: Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: February 27, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changhyun Lee, Byoungkeun Son, Hyejin Cho
  • Patent number: 9905661
    Abstract: There is set forth herein a method of fabricating a semiconductor structure, the method including forming a conductive metal layer over a source/drain region. The conductive metal layer in one aspect can prevent gouging of a source/drain region during removal of materials above a source/drain region. The conductive metal layer in one aspect can be used to pattern an air spacer for reduced parasitic capacitance. The conductive metal layer in one aspect can reduce a contact resistance between a source/drain region and a contact above a source/drain region.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: February 27, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Hui Zang
  • Patent number: 9859390
    Abstract: Embodiments of the present disclosure include contact structures and methods of forming the same. An embodiment is a method of forming a semiconductor device, the method including forming a contact region over a substrate, forming a dielectric layer over the contact region and the substrate, and forming an opening through the dielectric layer to expose a portion of the contact region. The method further includes forming a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening; and filling the opening with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou, Chia-Lin Hsu
  • Patent number: 9856564
    Abstract: A technique related with a lithography system is disclosed. The lithography system includes at least one target object disposed on a substrate, a processor configured to process an image of the target object to determine an optical pattern for a coating layer of the target object, and an exposure apparatus configured to provide light having the optical pattern determined by the processor to the substrate.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: January 2, 2018
    Assignee: SNU R&DB FOUNDATION
    Inventors: Sunghoon Kwon, Sueun Chung, Seungah Lee, Jisung Jang, Sangkwon Han
  • Patent number: 9734271
    Abstract: In some embodiments, in a method for a semiconductor device having an interconnect structure, a design layout is received. A metal line in the design layout is identified, which has at least one via thereon and does not couple downward with an oxide diffusion region. The area of a gate oxide coupled with the metal line is obtained from the design layout. The method comprises determining whether the area of the gate oxide is greater than a first predetermined value. When the area of the gate oxide is greater than the first predetermined value, a charge release path is coupled with the metal line.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: August 15, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu Ching Lee, Jian-Hong Lin, Te-Liang Lee, Jyh-Weei Hsia
  • Patent number: 9728455
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure; forming a sacrificial layer on the gate structure; forming a first contact plug in the sacrificial layer and the ILD layer; removing the sacrificial layer; and forming a first dielectric layer on the gate structure and the first contact plug.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: August 8, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Feng-Yi Chang, Chieh-Te Chen
  • Patent number: 9666477
    Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film as a portion of a laminated insulating film on a substrate in which a plurality of circuit configurations is formed; polishing the first insulating film; measuring a film thickness distribution of the first insulating film; and forming a second insulating film as a portion of the laminated insulating film on the polished first insulating film at a film thickness distribution differing from the film thickness distribution of the first insulating film to correct a film thickness of the laminated insulating film.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: May 30, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Naofumi Ohashi, Satoshi Takano
  • Patent number: 9583538
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnects extending in a first direction, a plurality of second interconnects extending in a second direction, a plurality of stacked films respectively provided between the first interconnects and the second interconnects, each of the plurality of stacked films including a variable resistance film, a first inter-layer insulating film provided in a first region between the stacked films, and a second inter-layer insulating film provided in a second region having a wider width than the first region. The second inter-layer insulating film includes a plurality of protrusions configured to support one portion of the plurality of second interconnects on the second region. A protruding length of the protrusions is less than a stacking height of the stacked films.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: February 28, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kotaro Noda
  • Patent number: 9576846
    Abstract: Methods for manufacturing a data storage device are provided. A method may include forming an interlayer dielectric layer on a substrate, patterning the interlayer dielectric layer in a peripheral region of the substrate to form first trenches, forming first bit lines in the first trenches, patterning the interlayer dielectric layer between the first bit lines in the peripheral region to form second trenches extending along the first trenches after the formation of the first bit lines, and forming second bit lines in the second trenches.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: February 21, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kilho Lee
  • Patent number: 9564371
    Abstract: A manufacturing method for forming a semiconductor device includes: first, a substrate is provided, a fin structure is formed on the substrate, and a plurality of gate structures are formed on the fin structure, next, a hard mask layer and a first photoresist layer are formed on the fin structure, an first etching process is then performed on the first photoresist layer, afterwards, a plurality of patterned photoresist layers are formed on the remaining first photoresist layer and the remaining hard mask layer, where each patterned photoresist layer is disposed right above each gate structure, and the width of each patterned photoresist is larger than the width of each gate structure, and the patterned photoresist layer is used as a hard mask to perform an second etching process to form a plurality of second trenches.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: February 7, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Tsung-Hung Chang, Jia-Rong Wu, Ching-Ling Lin, Yi-Hui Lee, Chih-Sen Huang, Yi-Wei Chen
  • Patent number: 9385112
    Abstract: A semiconductor device includes a substrate having laterally-adjacent first and second substrate regions. A first isolation region is at least in the first substrate region. An active region is at least in the second substrate region. The active region is laterally adjacent to the first isolation region. A conductive line extends from the first substrate region into the second substrate region. The conductive line is over the first isolation region and over the active region. A top surface of the conductive line over the first isolation region in the first substrate region is lower in the substrate than an elevationally outer surface of active material of the active region in the second substrate region. A top surface of the conductive line over the active region in the second substrate region is higher in the substrate than the elevationally outer surface of the active material of the active region in the second substrate region.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: July 5, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Kazuaki Takesako
  • Patent number: 9330975
    Abstract: A method of forming a through-substrate via includes forming a through-substrate via opening at least partially through a substrate from one of opposing sides of the substrate. A first material is deposited to line and narrow the through-substrate via opening. The first material is etched to widen at least an elevationally outermost portion of the narrowed through-substrate via opening on the one side. After the etching, a conductive second material is deposited to fill the widened through-substrate via opening. Additional implementations are disclosed. Integrated circuit substrates are disclosed independent of method of manufacture.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: May 3, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Anurag Jindal, Hongqi Li
  • Patent number: 9087727
    Abstract: A semiconductor device includes a semiconductor body including a first upper surface with a first side surface extending downwardly therefrom, a second upper surface with a second side surface extending downwardly therefrom, and a bottom surface interfacing first and second side surfaces. The first and second side surfaces and the bottom surface together define a groove. A conductive film partially fills the groove with an intervention of an insulating film therebetween so the conductive film terminates at a first intermediate portion of the first side surface between the first upper surface and the bottom surface and at a second intermediate portion of the second side surface between the second upper surface and the bottom surface. A distance between the first intermediate portion of the first side surface and the first upper surface exceeds a distance between the second intermediate portion of the second side surface and the second upper surface.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: July 21, 2015
    Assignee: PS4 LUXCO S.A.R.L.
    Inventor: Koji Hamada
  • Patent number: 9059103
    Abstract: Disclosed is a processing method that removes moisture in a low permittivity film formed on a substrate to be processed which has a damaged layer on the surface thereof while maintaining the specific permittivity or a leakage current value low when the film is subjected to a recovery processing. The method for the recovery processing includes applying, on the damaged layer of the low permittivity film, a first processing gas whose molecules are small sufficient to permeate the inside of the damaged layer of the low permittivity film and which is able to remove the moisture in the damaged layer and a second processing gas which forms a hydrophobic dense reformatted layer on the surface of the damaged layer, thereby allowing the first processing gas and the second processing gas to react with the damaged layer.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: June 16, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Wataru Shimizu, Kiyoshi Maeda, Toshifumi Nagaiwa
  • Patent number: 9040421
    Abstract: Methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a semiconductor substrate disposed with a device therein and/or thereon. A contact structure including a barrier layer and a plug metal overlying the barrier layer is formed in electrical contact with the device. A hardmask is formed overlying the contact structure. The method includes performing an etch to form a via opening through the hardmask and to expose the barrier layer and the plug metal. Further, the method removes a remaining portion of the hardmask with a wet etchant, while the contact structure is configured to inhibit the wet etchant from etching the barrier layer. In the method, the via opening is filled with a conductive material to form an interconnect to the contact structure.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: May 26, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Xunyuan Zhang, Xuan Lin, Vimal Kamineni
  • Patent number: 9034753
    Abstract: A method is disclosed that includes forming a conductive logic contact in a logic area of a semiconductor device, forming a bit line contact and a capacitor contact in a memory array of the semiconductor device, and performing at least one first common process to form a first metallization layer comprising a first conductive line in the logic area that is conductively coupled to the conductive logic contact and a bit line in the memory array that is conductively coupled to the bit line contact. The method further includes performing at least one second common process to form a second metallization layer comprising a first conductive structure conductively coupled to the first conductive line in the logic area and a second conductive structure in the memory array that that is conductively coupled to the capacitor contact.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: May 19, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Till Schloesser, Peter Baars
  • Patent number: 9035397
    Abstract: A method for manufacturing a gate structure may include the following steps: providing a stack on a substrate, the first stack including (from top to bottom) a dummy layer, a first TiN layer, a TaN layer, a second TiN layer, a high-k first dielectric layer, and an interfacial layer; etching the stack to result in a remaining stack that includes at least a remaining dummy layer, a first remaining TiN layer, and a remaining TaN layer; providing an etching stop layer on the substrate; providing a second dielectric layer on the etching stop layer; performing planarization according to the remaining dummy layer; removing the remaining dummy layer and a first portion of the first remaining TiN layer using a dry etching process; removing a second portion of the first remaining TiN layer using a wet etching process; and providing a metal gate layer on the remaining TaN layer.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: May 19, 2015
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Aileen Li, Jinghua Ni, David Han
  • Patent number: 9034745
    Abstract: A semiconductor device and a method for manufacturing the same are disclosed. A semiconductor device includes a contact hole formed over a semiconductor substrate so as to open an active region, a contact plug coupled to the active region in the contact hole and having a height lower than that of the contact hole, and a bit line that is coupled to the contact plug and has the same width as the contact plug. When forming a bit line of a cell region, a barrier metal layer is formed between a bit line contact plug and a bit line conductive layer, such that interfacial resistance is reduced, a thickness of the bit line conductive layer is increased, conductivity is improved, and the height of overall bit line is reduced, resulting in reduction in parasitic capacitance.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: May 19, 2015
    Assignee: SK Hynix Inc.
    Inventor: Song Hynix Im
  • Patent number: 9034758
    Abstract: A spacer etching process produces ultra-narrow conductive lines in a plurality of semiconductor dice. Trenches are formed in a first dielectric then a sacrificial film is deposited onto the first dielectric and the trench surfaces formed therein. Planar sacrificial film is removed from the face of the first dielectric and bottom of the trenches, leaving only sacrificial films on the trench walls. A gap between the sacrificial films on the trench walls is filled in with a second dielectric. A portion of the second dielectric is removed to expose tops of the sacrificial films. The sacrificial films are removed leaving ultra-thin gaps that are filled in with a conductive material. The tops of the conductive material in the gaps are exposed to create “fence conductors.” Portions of the fence conductors and surrounding insulating materials are removed at appropriate locations to produce desired conductor patterns comprising isolated fence conductors.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 19, 2015
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventor: Paul Fest
  • Patent number: 9029260
    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Chieh Lin, Hung-Wen Su, Minghsing Tsai, Syun-Ming Jang
  • Patent number: 9029193
    Abstract: A semiconductor device has a first interconnect structure formed over a first side of a substrate. A semiconductor die is mounted to the first interconnect structure. An encapsulant is deposited over the semiconductor die and first interconnect structure for structural support. A portion of a second side of the substrate, opposite the first side of the substrate, is removed to reduce its thickness. The encapsulant maintains substrate robustness during thinning process. A TSV is formed through the second side of the substrate to the first interconnect structure. A second interconnect structure is formed in the TSV. The TSV has a first insulating layer formed over the second side of the substrate and first conductive layer formed over the first insulating layer and into the TSV. The second interconnect structure has a second conductive layer formed over the first conductive layer in an area away from the TSV.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: May 12, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Pandi Chelvam Marimuthu, Nathapong Suthiwongsunthorn, Kock Liang Heng
  • Patent number: 9029257
    Abstract: Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate. Organic fill material is formed over the liner and between the posts. A planarized surface is formed which extends across the posts and across one or both of the liner and the fill material. Some embodiments include a semiconductor construction containing a semiconductor die. Electrically conductive posts extend through the die. The posts have upper surfaces above a backside surface of the die, and have sidewall surfaces extending between the backside surface and the upper surfaces. A liner is across the backside surface of the die and along the sidewall surfaces of the posts. Electrically conductive caps are over the upper surfaces of the posts, and have rims along the liner adjacent the sidewall surfaces of the posts.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: May 12, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Jaspreet S. Gandhi
  • Publication number: 20150126013
    Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.
    Type: Application
    Filed: October 16, 2014
    Publication date: May 7, 2015
    Inventors: Chang-Youn HWANG, Noh-Jung KWAK, Hong-Gu YI, Yun-Je CHOI, Se-Han KWON, Ki-Soo CHOI, Seung-Bum KIM, Do-Hyung KIM, Doo-Sung JUNG, Dae-Sik PARK
  • Patent number: 9018091
    Abstract: Various methods for forming a low profile assembly are described. The low profile assembly may include an integrated circuit. The integrated circuit as well as components associated with the integrated circuit may be positioned below a surface plane of a printed circuit board in which the integrated circuit is located. The integrated circuit may include bond wires configured to electrically connect the integrated circuits to other components. The low profile assembly may include forming various layers over a substrate and later removing some of the layers.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: April 28, 2015
    Assignee: Apple Inc.
    Inventors: Shawn X. Arnold, Terry L. Gilton, Matthew E. Last
  • Patent number: 9006039
    Abstract: A fabrication method of a packaging substrate includes: providing a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; forming a first encapsulant in the first openings; forming a second encapsulant in the second openings; and forming a surface circuit layer on the first encapsulant and the first core circuit layer.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: April 14, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chi-Ching Ho, Yu-Chih Yu, Ying-Chou Tsai
  • Patent number: 8999846
    Abstract: An integrated circuit structure includes a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator layers, and conductive via material within the via openings. The conductive via material within corresponding via openings of adjacent insulator layers are electrically connected to form continuous electrical via paths through the insulator layers between the top surface and the bottom surface of the laminated structure. Within each of the continuous electrical via paths, the via openings are positioned relative to each other to form a diagonal structural path of the conductive via material through the laminated structure. The corresponding via openings of the adjacent insulator layers partially overlap each other. The diagonal structural paths are non-perpendicular to the top surface and the bottom surface.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Luke D. LaCroix, Mark C. H. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
  • Patent number: 8999843
    Abstract: A semiconductor device and method of fabricating the device are provided, the method including providing an insulating layer, wherein the insulating layer covers an active region and a gate of at least one semiconductor device; forming connection holes to the active region in the insulating layer to expose at least part of the active region, wherein the connection holes include a first portion of a first width and a second portion of a second width, the first portion of the connection holes being adjacent to the active region, and the first width being less than the second width; filling the connection holes with a metal material to form the contacts to the active region. As such, contacts formed for the active region also include a first portion of a first width and a second portion of a second width.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: April 7, 2015
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Steven Zhang, Liya Fu
  • Patent number: 8993377
    Abstract: A semiconductor wafer has first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the semiconductor wafer. The semiconductor wafer is singulated into a plurality of first semiconductor die. The first semiconductor die are mounted to a carrier. A second semiconductor die is mounted to the first semiconductor die. A footprint of the second semiconductor die is larger than a footprint of the first semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. The carrier is removed. A portion of the second surface is removed to expose the conductive vias. An interconnect structure is formed over a surface of the first semiconductor die opposite the second semiconductor die. Alternatively, a first encapsulant is deposited over the first semiconductor die and carrier, and a second encapsulant is deposited over the second semiconductor die.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: March 31, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Jun Mo Koo, Pandi C. Marimuthu, Seung Wook Yoon, Il Kwon Shim
  • Patent number: 8981569
    Abstract: According to one embodiment, a semiconductor device includes an insulating film, a catalytic layer and a wiring layer. The insulating film has a hole. The catalytic layer is formed at the bottom of the hole, at the peripheral wall of the hole, and on the upper surface of the insulating film outside the hole. A contact is formed of a carbon nanotube provided on the portion of the catalytic layer at the bottom of the hole. The wiring layer is formed of graphene and provided on the catalytic layer outside the hole in contact with the carbon nanotube. The catalytic layer at the bottom of the hole is a perforated film, and the catalytic layer outside the hole is a continuous film.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuro Saito, Makoto Wada, Atsunobu Isobayashi, Yuichi Yamazaki, Akihiro Kajita
  • Publication number: 20150069616
    Abstract: A semiconductor device includes a substrate on which a plurality of contact regions are defined, a plurality of transistors formed in the plurality of contact regions, a support body formed over the plurality of transistors and including a top surface, portions of which have different heights in the plurality of contact regions, a plurality of stacked structures including a plurality of conductive layers stacked over the support body, slits located between the plurality of stacked structures, first lines coupled to first junctions of the plurality of transistors through the slits, and second lines coupled to second junctions of the plurality of transistors through the slits.
    Type: Application
    Filed: March 21, 2014
    Publication date: March 12, 2015
    Applicant: SK hynix Inc.
    Inventors: Sung Lae OH, Chang Man SON, Sang Hyun SUNG, Jin Ho KIM
  • Patent number: 8969193
    Abstract: A semiconductor substrate (1) is provided on a main surface (14) with an intermetal dielectric (4) including metal planes (5) and on an opposite rear surface (15) with an insulation layer (2) and an electrically conductive connection pad (7). An etch stop layer (6) is applied on the intermetal dielectric to prevent a removal of the intermetal dielectric above the metal planes during subsequent method steps. An opening (9) having a side wall (3) and a bottom (13) is formed from the main surface through the substrate above the connection pad. A side wall spacer (10) is formed on the side wall by a production and subsequent partial removal of a dielectric layer (11). The insulation layer is removed from the bottom to uncover an area of the connection pad. A metal layer is applied in the opening and is provided for an interconnect through the substrate.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: March 3, 2015
    Assignee: ams AG
    Inventors: Jochen Kraft, Franz Schrank, Martin Schrems
  • Publication number: 20150056805
    Abstract: A bowing control pattern is formed on an intermediate layer. A hardmask pattern is formed on the bowing control layer. The hardmask pattern has a first opening, and the bowing control pattern has a second opening. A third opening passes through the intermediate layer and is connected to the second opening. The bowing control pattern includes first and second edges on a lower end of the second opening, and a third edge on an upper end of the second opening. When a first point on the first edge, a second point on the second edge, and a third point on a horizontal line passing through the third edge are defined, an intersecting angle between a first side from the first point to the second point, and a second side from the second point to the third point is from about 50° to about 80°.
    Type: Application
    Filed: April 8, 2014
    Publication date: February 26, 2015
    Inventors: Jae-Hong Park, Min-Joon Park, Jun-Ho Yoon, Gyung-Jin Min, Jin-Young Park, Je-Woo Han
  • Publication number: 20150054171
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate on which a contact region and a cell region are defined, sub-patterns formed in the contact region, on the substrate, and insulating patterns and conductive patterns stacked alternately along the sub-patterns.
    Type: Application
    Filed: January 9, 2014
    Publication date: February 26, 2015
    Applicant: SK hynix Inc.
    Inventor: Hyun Ho LEE
  • Patent number: 8962476
    Abstract: A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: February 24, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Xia Feng, Jianmin Feng, Kang Chen
  • Patent number: 8963333
    Abstract: Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: February 24, 2015
    Assignee: Intel Corporation
    Inventors: Jiamiao Tang, Henry Xu, Shinichi Sakamoto
  • Patent number: 8962482
    Abstract: An integrated circuit interconnect is fabricated by using a mask to form a via in an insulating layer for a conductive plug. After the plug is formed in the via, a thin (e.g., <100 nm) isolation layer is deposited over the resulting structure. An opening is created in the isolation layer by using the same mask at a different radiation exposure level to make the opening more narrow than the underlying plug. A conductive line is then formed which makes electrical contact with the plug through the opening in the isolation layer. By vertically separating and electrically isolating the conductive plug from adjacent conductive lines, the isolation layer advantageously reduces the likelihood of an undesired electrical short occurring between the conductive plug and a nearby conductive line.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Todd Albertson, Darin Miller, Mark Anderson
  • Patent number: 8956889
    Abstract: In a method of testing a plurality of through silicon vias (TSVs) chained together by interconnect on a substrate, a test signal is applied to a first test pad among a plurality of test pads, and a return signal is measured at a second test pad among the plurality of test pads. At least one test pad of the plurality of test pads is grounded to the substrate. The remaining test pads of the plurality of test pads are either connected to the plurality of chained TSVs or are grounded.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: February 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chih Lin, Mill-Jer Wang, Ching-Nen Peng, Hao Chen
  • Patent number: 8951900
    Abstract: The present disclosure is directed to, among other things, an illustrative method that includes forming an opening in a dielectric material of a contact level of a semiconductor device, and selectively depositing a conductive material in the opening to form a contact element therein, the contact element extending to a contact area of a circuit element and having a laterally restricted excess portion formed outside of the opening and above the dielectric material. The disclosed method further includes forming a sacrificial material layer above the dielectric material and the contact element, the sacrificial material layer surrounding the laterally restricted excess portion. Additionally, the method includes planarizing a surface topography of the contact level in the presence of the sacrificial material so as to remove the laterally restricted excess portion from above the dielectric material.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: February 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Axel Preusse, Norbert Schroeder, Uwe Stoeckgen
  • Patent number: 8951906
    Abstract: A method for fabricating through-silicon vias (TSVs) for semiconductor devices is provided. Specifically, the method involves utilizing copper contact pads in a back-end-of-line wiring level, wherein the copper contact pads act as cathodes for performing an electroplating technique to fill TSVs with plated-conductive material (e.g., copper) from an electroplating solution. Moreover, the method provides a way to fill high aspect ratio TSVs with minimal additional semiconductor fabrication process steps, which can increase the silicon area that is available for forming additional electronic components on integrated circuits.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Troy L. Graves-Abe
  • Patent number: 8946087
    Abstract: A method for providing metal filled features in a layer is provided. A metal seed layer is deposited on tops and bottoms of the features. Metal seed layer on tops of the features and overhangs is removed without removing metal seed layer on bottoms of features. An electroless deposition of metal is provided to fill the features, wherein the electroless deposition first deposits on the metal seed layer on bottoms of the features.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: February 3, 2015
    Assignee: Lam Research Corporation
    Inventor: Praveen Reddy Nalla
  • Patent number: 8945994
    Abstract: An electronic chip package comprising at least one chip bonded to a routing layer of an interposer comprising a routing layer and a via post layer that is surrounded by a dielectric material comprising glass fibers in a polymer matrix, wherein the electronic chip package further comprises a second layer of a dielectric material encapsulating the at least one chip, the routing layer and the wires, and methods of fabricating such electronic chip packages.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: February 3, 2015
    Assignee: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.
    Inventors: Dror Hurwitz, Shih-Fu Alex Huang
  • Patent number: 8940635
    Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate and forming a dielectric layer over the semiconductor substrate. An opening is formed in the dielectric layer. A conductive line is formed in the opening, wherein the conductive line has an open void formed therein. A sealing metal layer is formed overlying the conductive line, the dielectric layer, and the open void, wherein the sealing metal layer substantially fills the open void. The sealing metal layer is planarized so that a top surface thereof is substantially level with a top surface of the conductive line. An interconnect feature is formed above the semiconductor substrate, wherein the interconnect feature is electrically coupled with the conductive line and the sealing metal layer-filled open void.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Chi, Huang-Yi Huang, Szu-Ping Tung, Ching-Hua Hsieh
  • Patent number: 8937009
    Abstract: Disclosed are a method for metallization during semiconductor wafer processing and the resulting structures. In this method, a passivation layer is patterned with first openings aligned above and extending vertically to metal structures below. A mask layer is formed and patterned with second openings aligned above the first openings, thereby forming two-tier openings extending vertically through the mask layer and passivation layer to the metal structures below. An electrodeposition process forms, in the two-tier openings, both under-bump pad(s) and additional metal feature(s), which are different from the under-bump pad(s) (e.g., a wirebond pad; a final vertical section of a crackstop structure; and/or a probe pad). Each under-bump pad and additional metal feature initially comprises copper with metal cap layers thereon.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: January 20, 2015
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Karen P. McLaughlin, Ekta Misra, Christopher D. Muzzy, Eric D. Perfecto, Wolfgang Sauter