Abstract: Embodiments disclosed herein include methods of patterning a back end of line (BEOL) stack and the resulting structures. In an embodiment a method of patterning a BEOL stack comprises forming a grating over an interlayer dielectric (ILD), and forming a spacer over the grating. In an embodiment, the spacer is etch selective to the grating. In an embodiment, the method further comprises disposing a hardmask over the grating and the spacer, and patterning the hardmask to form an opening in the hardmask. In an embodiment, the method further comprises filling the opening with a plug, removing the hardmask, and etching the spacer. In an embodiment, a portion of the spacer is protected from the etch by the plug. In an embodiment, the method may further comprise removing the plug, and transferring the grating into the ILD with an etching process.

Abstract: A method for forming a storage node contact structure and semiconductor structure are provided. The method includes providing a substrate having a surface on which bit line structures are formed; forming a groove at a part, corresponding to an active region, of bottom of the contact hole; and growing a silicon crystal from the groove in the contact hole by using an epitaxial growth process, and controlling growth rates of the silicon crystal in a first and second directions in a growth process to enable the growth rate of the silicon crystal in the first direction to be greater than the growth rate of the silicon crystal in the second direction at beginning of growth and enable the growth rate of the silicon crystal in the first direction to be equal to the growth rate of the silicon crystal in the second direction at end of the growth.

Abstract: According to one embodiment, a display device including a display panel including a mount side curved to correspond to the curved shape of a display surface, a flat circuit board, and a first flexible wiring board mounted on the display panel in a first end side while being connected to the circuit board in a second end side, wherein the first flexible wiring board includes a first base member including a first surface and a second surface, a first line positioned in the first surface side, and a first protection layer covering the first line, and includes a first bending part to be bent between a first bending boundary and a second bending boundary, the second bending boundary is inclined with respect to the first bending boundary, and the first base member includes a first groove positioned in the first bending part and formed in the second surface.

Abstract: A method for forming a memory includes: providing a substrate, a plurality of discrete bit line structures being located on the substrate, and an area surrounded by the adjacent bit line structures and the substrate and having a central axis; forming, on the substrate, a first conductive film filling an area between the adjacent bit line structures; etching the first conductive film by a first etching process to form a first conductive layer; forming a second conductive film on the top surface of the first conductive layer; and etching the second conductive film and the first conductive layer by a second etching process, the remaining second conductive film and the first conductive layer forming a capacitive contact window.

Abstract: The present disclosure describes a method for reducing RC delay in radio frequency operated devices or devices that would benefit from an RC delay reduction. The method includes forming, on a substrate, a transistor structure having source/drain regions and a gate structure; depositing a first dielectric layer on the substrate to embed the transistor structure; forming, within the first dielectric layer, source/drain contacts on the source/drain regions of the transistor structure; depositing a second dielectric layer on the first dielectric layer; forming metal lines in the second dielectric layer; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching, through the opening, the second dielectric layer between the metal lines and the first dielectric layer between the source/drain contacts; and depositing a third dielectric layer to form an air-gap in the first and second dielectric layers and over the transistor structure.

Abstract: An apparatus comprises a conductive structure, another conductive structure, and a laminate spacer structure interposed between the conductive structure and the another conductive structure in a first direction. The laminate spacer structure comprises a dielectric spacer structure, another dielectric spacer structure, and an additional dielectric spacer structure interposed between the dielectric spacer structure and the another dielectric spacer structure. The additional dielectric spacer structure comprises at least one dielectric material, and gas pockets dispersed within the at least one dielectric material. Additional apparatuses, memory devices, electronic systems, and a method of forming an apparatus are also described.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to forming via rail and deep via structures to reduce parasitic capacitances in standard cell structures. Via rail structures are formed in a level different from the conductive lines. The via rail structure can reduce the number of conductive lines and provide larger separations between conductive lines that are on the same interconnect level and thus reduce parasitic capacitance between conductive lines.

Abstract: A semiconductor device includes: an FET structure that is formed next to a looped trench on a semiconductor substrate and that has an n+ emitter region and an n? drain region facing each other in the depth direction of the looped trench across a p-type base region; a p-type floating region formed on the side of the looped trench opposite to the FET structure; and an emitter connecting part that is electrically connected to the n+ emitter region and a trench gate provided in the same trench, the emitter connecting part and the trench gate being insulated from each other by the looped trench. The trench gate faces the FET structure, and the emitter connecting part faces the p-type floating region, across an insulating film.

Abstract: The present application provides a manufacturing method of a memory. The manufacturing method includes: providing a substrate, where the substrate includes a core region and a peripheral region, and a first barrier layer is provided in the core region; laminating and forming a first conductive layer and a first mask layer on the substrate in sequence; etching the first mask layer, the first conductive layer, and the first barrier layer in the core region, to form a first etched hole; etching the substrate along the first etched hole, to form a bit line contact hole; removing the first mask layer and the first conductive layer in the core region and located around the bit line contact hole; and forming a bit line contact in the bit line contact hole.

Abstract: A method of fabricating an integrated circuit device is provided. The method includes depositing a first dielectric layer over a semiconductor substrate and forming first and second via contacts in the first dielectric layer and extending below a bottom surface of the first dielectric layer. The method also includes etching back the first dielectric layer to expose upper portions of the first and second via contacts. The method further includes depositing an etch stop layer conformally on the upper portions of the first and second via contacts and on the first dielectric layer. In addition, the method includes depositing a second dielectric layer on the etch stop layer and forming first and second metal lines in the second dielectric layer to be electrically connected to the first via contact and the second via contact, respectively.

Abstract: A backside connection access structure and method for manufacturing are described. The method including forming a gold layer over at least a portion of a substrate. The method also including forming a metal layer over the gold layer. And, the method includes forming an opening in the substrate to expose at least a portion of the gold layer.

Abstract: Electronic devices and methods of forming electronic devices using a reduced number of hardmask materials and reusing lithography reticles are described. Patterned substrates are formed using a combination of etch selective hardmask materials and reusing reticles to provide a pattern of repeating trapezoidal and rhomboidal openings.

Abstract: A package structure and method of forming the same are provided. The package structure includes a die, a TIV, an encapsulant, an adhesion promoter layer, a RDL structure and a conductive terminal. The TIV is laterally aside the die. The encapsulant laterally encapsulates the die and the TIV. The adhesion promoter layer is sandwiched between the TIV and the encapsulant. The RDL structure is electrically connected to the die and the TIV. The conductive terminal is electrically connected to the die through the RDL structure.

Abstract: An apparatus comprises a conductive structure, another conductive structure, and a laminate spacer structure interposed between the conductive structure and the another conductive structure in a first direction. The laminate spacer structure comprises a dielectric spacer structure, another dielectric spacer structure, and an additional dielectric spacer structure interposed between the dielectric spacer structure and the another dielectric spacer structure. The additional dielectric spacer structure comprises at least one dielectric material, and gas pockets dispersed within the at least one dielectric material. Additional apparatuses, memory devices, electronic systems, and a method of forming an apparatus are also described.

Abstract: A method includes providing a structure having a substrate, a gate, a gate spacer, a dielectric gate cap, a source/drain (S/D) feature, a contact etch stop layer (CESL) covering a sidewall of the gate spacer and a top surface of the S/D feature, and an inter-level dielectric (ILD) layer. The method includes etching a contact hole through the ILD layer and through a portion of the CESL, the contact hole exposing the CESL covering the sidewalls of the gate spacer and exposing a top portion of the S/D feature. The method includes forming a silicide feature on the S/D feature and selectively depositing an inhibitor on the silicide feature. The inhibitor is not deposited on surfaces of the CESL other than at a corner area where the CESL and the silicide feature meet.

Abstract: A semiconductor element includes a semiconductor substrate; a collector layer on the semiconductor substrate; a base layer on the collector layer; an emitter layer on the base layer; emitter wiring electrically coupled to the emitter layer; a top metal layer on the emitter wiring; a first protective film covering the emitter wiring and the top metal layer, the first protective film having a first opening that overlaps at least the collector layer; and a bump including an under-bump metal layer electrically coupled to the emitter wiring via the first opening, the under-bump metal layer being larger than the first opening in plan-view area. The first protective film has an inner edge around the first opening, and the inner edge is on the top metal layer.

Abstract: Aluminum-containing layers and systems and methods for forming the same are provided. In an embodiment, a method includes depositing an aluminum-containing layer on a substrate in a chamber by atomic layer deposition. The depositing further includes contacting the substrate with an aluminum-containing precursor in a first pulse having a first peak pulse flow rate and a first pulse width; contacting the substrate with a nitrogen-containing precursor; contacting the substrate with the aluminum-containing precursor in a second pulse having a second peak pulse flow rate and a second pulse width; and contacting the substrate with the nitrogen-containing precursor. The first peak pulse flow rate is greater than the second peak pulse flow rate. The first pulse width is smaller than the second pulse width.

Abstract: Methods of manufacturing an integrated circuit device are provided. A method of manufacturing an integrated circuit device includes sequentially forming a device layer, a wiring insulating layer, and a hard mask layer on a semiconductor substrate. The method includes sequentially removing a first region and a second region of the hard mask layer by using a first mask layer having a first opening and a second mask layer having a second opening as an etch mask, respectively. The method includes forming a first wiring recess through the wiring insulating layer and a second wiring recess having a depth that is less than that of the first wiring recess by removing a portion of the wiring insulation layer by using a portion of the hard mask layer as an etching mask. Moreover, the method includes forming a wiring structure that is in the first wiring recess and the second wiring recess.

Abstract: Implementations of the present disclosure provide methods for preventing contact damage or oxidation after via/trench opening formation. In one example, the method includes forming an opening in a structure on the substrate to expose a portion of a surface of an electrically conductive feature, and bombarding a surface of a mask layer of the structure using energy species formed from a plasma to release reactive species from the mask layer, wherein the released reactive species form a barrier layer on the exposed surface of the electrically conductive feature.

Abstract: The present disclosure provides a semiconductor structure including a substrate, a transistor region having a gate over the substrate and a doped region at least partially in the substrate, a first metal layer over the transistor region, and a magnetic tunneling junction (MTJ) between the transistor region and the first metal layer. The present disclosure provides a method for manufacturing a semiconductor structure, including forming a transistor region over a substrate, the transistor region comprising a gate and a doped region, forming a magnetic tunneling junction (MTJ) over the transistor region, electrically coupling to the transistor region, and forming a first metal layer over the MTJ, electrically coupling to the MTJ and the transistor region.

Abstract: Embodiments of the present invention provide a replacement metal gate and a fabrication process with reduced lithography steps. Using selective etching techniques, a layer of fill metal is used to protect the dielectric layer in the trenches, eliminating the need for some lithography steps. This, in turn, reduces the overall cost and complexity of fabrication. Furthermore, additional protection is provided during etching, which serves to improve product yield.

Abstract: Provided are a semiconductor package and a method of manufacturing the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, an interconnect substrate spaced apart from the semiconductor chip on the substrate and including a conductive member therein, a solder ball on the interconnect substrate and electrically connected to the conductive member, a polymer layer on the interconnect substrate and the semiconductor chip and including an opening through which the solder ball is exposed, and polymer particles in the solder ball and including the same material as the polymer layer.

Abstract: A method of forming a semiconductor device includes forming a plurality of fins on a substrate, forming a polysilicon gate structure, and replacing the polysilicon gate structure with a metal gate structure. Replacing the polysilicon gate structure includes depositing a work function metal layer over the plurality of fins, forming a metal oxide layer over the work function metal layer, and depositing a first metal layer over the metal oxide layer. A first portion of the metal oxide layer is formed within an area between adjacent fins from among the plurality of fins. An example benefit includes reduced diffusion of unwanted and/or detrimental elements from the first metal layer into its underlying layers and consequently, the reduction of the negative impact of these unwanted and/or detrimental elements on the semiconductor device performance.

Abstract: An integrated circuit containing elongated contacts, including elongated contacts which connect to at least three active areas and/or MOS gates, and including elongated contacts which connect to exactly two active areas and/or MOS gates and directly connect to a first level interconnect. A process of forming an integrated circuit containing elongated contacts, including elongated contacts which connect to at least three active areas and/or MOS gates, using exactly two contact photolithographic exposure operations, and including elongated contacts which connect to exactly two active areas and/or MOS gates and directly connect to a first level interconnect.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to post spacer self-aligned cut structures and methods of manufacture. The method includes: providing a non-mandrel cut; providing a mandrel cut; forming blocking material on underlying conductive material in the non-mandrel cut and the mandrel cut; forming trenches with the blocking material acting as a blocking mask at the mandrel cut and the non-mandrel cut; and filling the trenches with metallization features such that the metallization features have a tip to tip alignment.

Abstract: There is set forth herein a method of fabricating a semiconductor structure, the method including forming a conductive metal layer over a source/drain region. The conductive metal layer in one aspect can prevent gouging of a source/drain region during removal of materials above a source/drain region. The conductive metal layer in one aspect can be used to pattern an air spacer for reduced parasitic capacitance. The conductive metal layer in one aspect can reduce a contact resistance between a source/drain region and a contact above a source/drain region.

Abstract: Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.

Abstract: A technique related with a lithography system is disclosed. The lithography system includes at least one target object disposed on a substrate, a processor configured to process an image of the target object to determine an optical pattern for a coating layer of the target object, and an exposure apparatus configured to provide light having the optical pattern determined by the processor to the substrate.

Abstract: Embodiments of the present disclosure include contact structures and methods of forming the same. An embodiment is a method of forming a semiconductor device, the method including forming a contact region over a substrate, forming a dielectric layer over the contact region and the substrate, and forming an opening through the dielectric layer to expose a portion of the contact region. The method further includes forming a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening; and filling the opening with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region.

Abstract: In some embodiments, in a method for a semiconductor device having an interconnect structure, a design layout is received. A metal line in the design layout is identified, which has at least one via thereon and does not couple downward with an oxide diffusion region. The area of a gate oxide coupled with the metal line is obtained from the design layout. The method comprises determining whether the area of the gate oxide is greater than a first predetermined value. When the area of the gate oxide is greater than the first predetermined value, a charge release path is coupled with the metal line.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure; forming a sacrificial layer on the gate structure; forming a first contact plug in the sacrificial layer and the ILD layer; removing the sacrificial layer; and forming a first dielectric layer on the gate structure and the first contact plug.

Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film as a portion of a laminated insulating film on a substrate in which a plurality of circuit configurations is formed; polishing the first insulating film; measuring a film thickness distribution of the first insulating film; and forming a second insulating film as a portion of the laminated insulating film on the polished first insulating film at a film thickness distribution differing from the film thickness distribution of the first insulating film to correct a film thickness of the laminated insulating film.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnects extending in a first direction, a plurality of second interconnects extending in a second direction, a plurality of stacked films respectively provided between the first interconnects and the second interconnects, each of the plurality of stacked films including a variable resistance film, a first inter-layer insulating film provided in a first region between the stacked films, and a second inter-layer insulating film provided in a second region having a wider width than the first region. The second inter-layer insulating film includes a plurality of protrusions configured to support one portion of the plurality of second interconnects on the second region. A protruding length of the protrusions is less than a stacking height of the stacked films.

Abstract: Methods for manufacturing a data storage device are provided. A method may include forming an interlayer dielectric layer on a substrate, patterning the interlayer dielectric layer in a peripheral region of the substrate to form first trenches, forming first bit lines in the first trenches, patterning the interlayer dielectric layer between the first bit lines in the peripheral region to form second trenches extending along the first trenches after the formation of the first bit lines, and forming second bit lines in the second trenches.

Abstract: A manufacturing method for forming a semiconductor device includes: first, a substrate is provided, a fin structure is formed on the substrate, and a plurality of gate structures are formed on the fin structure, next, a hard mask layer and a first photoresist layer are formed on the fin structure, an first etching process is then performed on the first photoresist layer, afterwards, a plurality of patterned photoresist layers are formed on the remaining first photoresist layer and the remaining hard mask layer, where each patterned photoresist layer is disposed right above each gate structure, and the width of each patterned photoresist is larger than the width of each gate structure, and the patterned photoresist layer is used as a hard mask to perform an second etching process to form a plurality of second trenches.

Abstract: A semiconductor device includes a substrate having laterally-adjacent first and second substrate regions. A first isolation region is at least in the first substrate region. An active region is at least in the second substrate region. The active region is laterally adjacent to the first isolation region. A conductive line extends from the first substrate region into the second substrate region. The conductive line is over the first isolation region and over the active region. A top surface of the conductive line over the first isolation region in the first substrate region is lower in the substrate than an elevationally outer surface of active material of the active region in the second substrate region. A top surface of the conductive line over the active region in the second substrate region is higher in the substrate than the elevationally outer surface of the active material of the active region in the second substrate region.

Abstract: A method of forming a through-substrate via includes forming a through-substrate via opening at least partially through a substrate from one of opposing sides of the substrate. A first material is deposited to line and narrow the through-substrate via opening. The first material is etched to widen at least an elevationally outermost portion of the narrowed through-substrate via opening on the one side. After the etching, a conductive second material is deposited to fill the widened through-substrate via opening. Additional implementations are disclosed. Integrated circuit substrates are disclosed independent of method of manufacture.

Abstract: A semiconductor device includes a semiconductor body including a first upper surface with a first side surface extending downwardly therefrom, a second upper surface with a second side surface extending downwardly therefrom, and a bottom surface interfacing first and second side surfaces. The first and second side surfaces and the bottom surface together define a groove. A conductive film partially fills the groove with an intervention of an insulating film therebetween so the conductive film terminates at a first intermediate portion of the first side surface between the first upper surface and the bottom surface and at a second intermediate portion of the second side surface between the second upper surface and the bottom surface. A distance between the first intermediate portion of the first side surface and the first upper surface exceeds a distance between the second intermediate portion of the second side surface and the second upper surface.

Abstract: Disclosed is a processing method that removes moisture in a low permittivity film formed on a substrate to be processed which has a damaged layer on the surface thereof while maintaining the specific permittivity or a leakage current value low when the film is subjected to a recovery processing. The method for the recovery processing includes applying, on the damaged layer of the low permittivity film, a first processing gas whose molecules are small sufficient to permeate the inside of the damaged layer of the low permittivity film and which is able to remove the moisture in the damaged layer and a second processing gas which forms a hydrophobic dense reformatted layer on the surface of the damaged layer, thereby allowing the first processing gas and the second processing gas to react with the damaged layer.

Abstract: Methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a semiconductor substrate disposed with a device therein and/or thereon. A contact structure including a barrier layer and a plug metal overlying the barrier layer is formed in electrical contact with the device. A hardmask is formed overlying the contact structure. The method includes performing an etch to form a via opening through the hardmask and to expose the barrier layer and the plug metal. Further, the method removes a remaining portion of the hardmask with a wet etchant, while the contact structure is configured to inhibit the wet etchant from etching the barrier layer. In the method, the via opening is filled with a conductive material to form an interconnect to the contact structure.

Abstract: A method for manufacturing a gate structure may include the following steps: providing a stack on a substrate, the first stack including (from top to bottom) a dummy layer, a first TiN layer, a TaN layer, a second TiN layer, a high-k first dielectric layer, and an interfacial layer; etching the stack to result in a remaining stack that includes at least a remaining dummy layer, a first remaining TiN layer, and a remaining TaN layer; providing an etching stop layer on the substrate; providing a second dielectric layer on the etching stop layer; performing planarization according to the remaining dummy layer; removing the remaining dummy layer and a first portion of the first remaining TiN layer using a dry etching process; removing a second portion of the first remaining TiN layer using a wet etching process; and providing a metal gate layer on the remaining TaN layer.

Abstract: A method is disclosed that includes forming a conductive logic contact in a logic area of a semiconductor device, forming a bit line contact and a capacitor contact in a memory array of the semiconductor device, and performing at least one first common process to form a first metallization layer comprising a first conductive line in the logic area that is conductively coupled to the conductive logic contact and a bit line in the memory array that is conductively coupled to the bit line contact. The method further includes performing at least one second common process to form a second metallization layer comprising a first conductive structure conductively coupled to the first conductive line in the logic area and a second conductive structure in the memory array that that is conductively coupled to the capacitor contact.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. A semiconductor device includes a contact hole formed over a semiconductor substrate so as to open an active region, a contact plug coupled to the active region in the contact hole and having a height lower than that of the contact hole, and a bit line that is coupled to the contact plug and has the same width as the contact plug. When forming a bit line of a cell region, a barrier metal layer is formed between a bit line contact plug and a bit line conductive layer, such that interfacial resistance is reduced, a thickness of the bit line conductive layer is increased, conductivity is improved, and the height of overall bit line is reduced, resulting in reduction in parasitic capacitance.

Abstract: A spacer etching process produces ultra-narrow conductive lines in a plurality of semiconductor dice. Trenches are formed in a first dielectric then a sacrificial film is deposited onto the first dielectric and the trench surfaces formed therein. Planar sacrificial film is removed from the face of the first dielectric and bottom of the trenches, leaving only sacrificial films on the trench walls. A gap between the sacrificial films on the trench walls is filled in with a second dielectric. A portion of the second dielectric is removed to expose tops of the sacrificial films. The sacrificial films are removed leaving ultra-thin gaps that are filled in with a conductive material. The tops of the conductive material in the gaps are exposed to create “fence conductors.” Portions of the fence conductors and surrounding insulating materials are removed at appropriate locations to produce desired conductor patterns comprising isolated fence conductors.

Abstract: A semiconductor device has a first interconnect structure formed over a first side of a substrate. A semiconductor die is mounted to the first interconnect structure. An encapsulant is deposited over the semiconductor die and first interconnect structure for structural support. A portion of a second side of the substrate, opposite the first side of the substrate, is removed to reduce its thickness. The encapsulant maintains substrate robustness during thinning process. A TSV is formed through the second side of the substrate to the first interconnect structure. A second interconnect structure is formed in the TSV. The TSV has a first insulating layer formed over the second side of the substrate and first conductive layer formed over the first insulating layer and into the TSV. The second interconnect structure has a second conductive layer formed over the first conductive layer in an area away from the TSV.

Abstract: Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate. Organic fill material is formed over the liner and between the posts. A planarized surface is formed which extends across the posts and across one or both of the liner and the fill material. Some embodiments include a semiconductor construction containing a semiconductor die. Electrically conductive posts extend through the die. The posts have upper surfaces above a backside surface of the die, and have sidewall surfaces extending between the backside surface and the upper surfaces. A liner is across the backside surface of the die and along the sidewall surfaces of the posts. Electrically conductive caps are over the upper surfaces of the posts, and have rims along the liner adjacent the sidewall surfaces of the posts.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.

Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.

Abstract: Various methods for forming a low profile assembly are described. The low profile assembly may include an integrated circuit. The integrated circuit as well as components associated with the integrated circuit may be positioned below a surface plane of a printed circuit board in which the integrated circuit is located. The integrated circuit may include bond wires configured to electrically connect the integrated circuits to other components. The low profile assembly may include forming various layers over a substrate and later removing some of the layers.

Abstract: A fabrication method of a packaging substrate includes: providing a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; forming a first encapsulant in the first openings; forming a second encapsulant in the second openings; and forming a surface circuit layer on the first encapsulant and the first core circuit layer.