Method For Producing A Semiconductor Wafer With A Polished Edge

- SILTRONIC AG

The invention relates to a method for producing a semiconductor wafer with a polished edge, said method comprising the following steps: a polishing of at least one side of the semiconductor wafer, and a polishing of the edge of the polished semiconductor wafer, wherein the edge is polished in the presence of a polishing agent by means of a polishing cloth containing fixed abrasive.

Skip to: Description  ·  Claims  · Patent History  ·  Patent History
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

The patent application relates to a method for producing a semiconductor wafer with a polished edge, which method involves using a polishing cloth containing fixed abrasive for polishing the edge. The polishing of the edge by means of such a polishing cloth is abbreviated to “FA” polishing hereinafter.

2. Background Art

The machining of the edge of a semiconductor wafer is receiving increasing attention. A smooth edge having a predetermined edge form is required. The edge form is usually produced by grinding the rough edge of a semiconductor wafer sliced for a crystal. In order to smooth the edge and to remove crystal lattice damage left in the course of grinding, it is necessary for the edge to be polished. This can be done using a polishing cloth containing no fixed abrasive. In this case, the polishing is effected in the presence of a slurry containing free abrasive. By comparison with this edge polishing, referred to hereinafter as cloth polishing for short, FA polishing has the advantage of obviating the comparatively complicated handling of slurry and enabling higher throughputs. This advantage is opposed by the disadvantage that the polished edge is less smooth. U.S. Pat. No. 6,514,423 B1 proposes etching the edge after the FA polishing in order to reduce its roughness.

As already mentioned, besides the low roughness of the edge, attention must also be paid to ensuring that the form of the edge meets the requirements. With regard to this it can be established that a polishing of one or both sides of the semiconductor wafer disadvantageously alters the form of the edge. Moreover, this problem cannot be solved by choosing a process chain, as described in U.S. Pat. No. 6,162,730, for example, which provides a cloth polishing of the edge only after a first polishing of the sides of the semiconductor wafer.

SUMMARY OF THE INVENTION

It is an object of the present invention, therefore, to propose a method which makes it possible to produce a semiconductor wafer with a polished edge which fully meets the requirements with regard to roughness and form.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

These and other objects are achieved by means of a method for producing a semiconductor wafer with a polished edge, comprising polishing at least one side of the semiconductor wafer; and polishing the edge of the polished semiconductor wafer, wherein the edge is polished in the presence of a polishing agent by means of a polishing cloth containing fixed abrasive.

The invention exploits the unexpected advantage that the form of the edge of the polished semiconductor wafer can be corrected by means of an FA polishing, but not by means of a cloth polishing.

The method is applied to a semiconductor wafer whose edge has already undergone a shaping machining step, preferably a grinding step, but whose edge has not yet been polished. The method begins with the polishing of at least one side of the semiconductor wafer. This involves a single-side polishing or a double-side polishing. A double-side polishing carried out simultaneously is preferred. A suitable machine for double-side polishing is described for example in DE 100 07 390 A1. During the polishing, the semiconductor wafer lies in a cutout, provided therefor, in a carrier acting as a guide cage and between an upper and a lower polishing plate. At least one polishing plate and the carrier are rotated, and the semiconductor wafer moves, with a polishing agent being supplied, on a path predetermined by a rolling curve, relative to the polishing plates covered with polishing cloth. The polishing pressure with which the polishing plates press on to the semiconductor wafer and the duration of the polishing are parameters which crucially codetermine the material removal brought about by means of the polishing.

The polishing of at least one side of the semiconductor wafer is preferably performed as removal polishing, that is to say with the aim of removing material with a thickness of at least 5 μm from the semiconductor wafer side to be polished.

Alterations of the edge form which are attributable to the polishing of one or both sides of the semiconductor wafer are corrected by an FA polishing of the edge.

A polishing cloth containing fixed abrasive, for example particles of silicon carbide, silicon dioxide or diamond, is used during the FA polishing. In accordance with one embodiment, the FA polishing is effected in the presence of a liquid polishing agent, for example in the presence of water. For smoothing the edge, that is to say for reducing the roughness thereof, in this case use is preferably made of a polishing cloth having particularly fine abrasive, preferably with a mesh size of not less than 4000, that is to say with an average particle diameter of not more than 5 μm, more preferably not more than 4 μm. A multistage FA polishing in the course of which polishing is effected using finer and finer abrasive and which is concluded with the fine abrasive is also particularly suitable. Such a polishing step sequence and suitable polishing devices are described for example in US 2006/0252355 A1.

In accordance with a second embodiment of the method, the FA polishing is performed in the presence of a slurry containing free abrasive, for example colloidal silicon dioxide or cerium oxide.

A third embodiment involves carrying out firstly an FA polishing in the presence of a liquid polishing agent and then a cloth polishing in the presence of a slurry containing free abrasive, for example colloidal silicon dioxide or cerium oxide. In this case, the average particle diameter of the fixed abrasive in the polishing cloth can be larger than when the subsequent cloth polishing is dispensed with. The use of a polishing cloth having fixed abrasive with a mesh of 1000 to 2000, that is to say with an average particle diameter of 7 to 25 μm, is preferred when a subsequent cloth polishing is carried out. The duration of the cloth polishing can be made very short, for example 15 to 30 s.

The method according to the invention preferably also comprises a polishing of the front side of the semiconductor wafer that is carried out as a single-side polishing. The front side of the semiconductor wafer is deemed to be that side of the semiconductor wafer on which provision is made for constructing electronic components. The single-side polishing, referred to hereinafter as CMP (“chemical-mechanical polishing”), is preferably performed as luster polishing with the aim of providing a smoothest possible side surface. The material removal of the CMP, with a thickness of at most 1 μm, is significantly smaller than in the case of a removal polishing. The CMP of the front side is preferably carried out after the double-side polishing and before or after the FA polishing.

The method according to the invention optionally also comprises the deposition of an epitaxial layer on the front side of the semiconductor wafer.

The following four step sequences a) to d) are particularly preferred:

    • a) double-side polishing→FA polishing→CMP
    • b) double-side polishing→FA polishing→cloth polishing→CMP
    • c) double-side polishing→CMP→FA polishing
    • d) double-side polishing→CMP→FA polishing→cloth polishing

While embodiments of the invention have been illustrated and described, it is not intended that these embodiments illustrate and describe all possible forms of the invention. Rather, the words used in the specification are words of description rather than limitation, and it is understood that various changes may be made without departing from the spirit and scope of the invention.

Claims

1. A method for producing a semiconductor wafer with a polished edge, comprising wherein the edge is polished in the presence of a polishing agent by means of a polishing cloth containing fixed abrasive.

polishing at least one side of the semiconductor wafer;
polishing the edge of the polished semiconductor wafer,

2. The method of claim 1, wherein the polishing agent contains free abrasive.

3. The method of claim 1, wherein the polishing of at least one side of the semiconductor wafer comprises a double-side polishing.

4. The method of claim 3, wherein the polishing of at least one side of the semiconductor wafer comprises double-side polishing and a single-side polishing performed thereafter.

5. The method of claim 4, comprising a further polishing of the edge, wherein the previously polished edge of the polished semiconductor wafer is further polished in the presence of a slurry containing free abrasive by means of a polishing cloth containing no fixed abrasive.

6. The method of claim 5, wherein the fixed abrasive in the polishing cloth has a mesh size of 1000 to 2000.

7. The method of claim 1, wherein the fixed abrasive in the polishing cloth has a mesh size of not less than 4000.

8. The method of claim 4, wherein the single-side polishing is carried out after the polishing of the edge.

9. The method of claim 5, wherein single-side polishing is carried out after the further polishing of the edge.

10. The method of claim 4, wherein single-side polishing is carried out before the polishing of the edge.

11. The method of claim 5, wherein single-side polishing is carried out before the polishing of the edge, and the further polishing of the edge is carried out after the initial polishing of the edge.

12. The method of claim 1, further comprising the deposition of an epitaxial layer on the polished side of the semiconductor wafer with a polished edge.

Patent History
Publication number: 20090130960
Type: Application
Filed: Oct 31, 2008
Publication Date: May 21, 2009
Applicant: SILTRONIC AG (Munich)
Inventors: Klaus Roettger (Bachmehring), Werner Aigner (Pfarrkirchen), Makoto Tabata (Burghausen)
Application Number: 12/262,202
Classifications
Current U.S. Class: Edging (451/44); Combined Abrading (451/57)
International Classification: B24B 1/00 (20060101); B24B 7/17 (20060101); B24B 9/02 (20060101);