Chip packaging process including simpification and mergence of burn-in test and high temperature test
A chip packaging process integrates a burn-in test or a high temperature test to simplify overall packaging and testing process flow. One or more chips are disposed on one or more units of a substrate strip where the substrate strip has a plurality of electrical open sections at the plating lines to electrically isolate the external pads between different units. After electrical connection and encapsulation, a burn-in test is executed at the same time of a post mold curing step, with a high-temperature testing if necessary. Therefore, the chips on the substrate strip has been gone through the burn-in test during the encapsulant is completely cured at the post mold curing step and the burn-in test is finished before the singulation step to reduce the overall testing time.
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The present invention relates to chip packaging processes, especially to chip packaging processes integrating burn-in test with high temperature test to simplify overall packaging and testing process flow.
BACKGROUND OF THE INVENTIONThe conventional manufacture of IC (integrated circuit) chip packages primarily divide into two major processes where one is the chip packaging process to package IC chips into BGA (Ball Grid Array) type chip packages or the other types of packages and the other is the package-level testing to separate failed chip packages from good ones with speed sorting. The conventional chip packaging process is to dispose a plurality of IC chips on a substrate strip until ball placement. After singulation, the packaged chips on a substrate strip become individual chip packages. Then package-level testing is followed by depositing individual chip packages into testing sockets for final test to screen failed packages from good ones with speed sorting. Especially, since memory chip packages are mass-production IC commodities with standard specifications, therefore, yields and productivities are very important to increase revenues and profits. How to lower the overall manufacture cost, including packaging and testing, becomes the first priority.
The conventional packaging process primarily comprises the steps as shown in
Furthermore, the conventional package-level testing process for chip packages includes a burn-in test to screen those “early failure” chip packages when the manufactured chip packages is memory devices or includes memory cells. The conventional package level testing process primarily comprises the steps as shown in
The main purpose of the present invention is to provide a chip packaging process integrating burn-in test to simplify overall packaging and testing process flow, so that testing time of memory chip packages is reduced leading to shorter overall manufacture cycle time.
The second purpose of the present invention is to provide a chip packaging process integrating burn-in test to simplify overall packaging and testing process flow. By substrate-level bum in test, the post mold curing step and burn-in test can be integrated and executed in single equipment to reduce capital investment of packaging and testing and to reduce damages of external terminals during testing processes.
According to the present invention, a chip packaging process integrating burn-in test is revealed. Firstly, one or more chips are provided, then, the chips are attached to one or more units of a substrate strip where each unit has a die-attaching surface and a corresponding SMT surface, moreover, a plurality of external pads are disposed on the SMT surface. Then, the chips are electrically connected to the corresponding units. Then, an encapsulant is formed on the die-attaching surface of the substrate strip to encapsulate the chips. Then, a post mold curing (PMC) step is executed to completely cure the encapsulant, meanwhile, a substrate-level burn-in test, even a high-temperature test, is executed where the external pads of the substrate strip are electrically contacted by a plurality of probing terminals of a burn-in probing board to create electrical connections to the chips for burn-in. Moreover, before the PMC step, the substrate strip has a plurality of electrical open sections at the plating lines so that the external pads between different units are electrically isolated. Finally, a step of package singulation is executed, the units including encapsulated chips are separated to form individual chip packages by sawing the substrate strip.
Please refer to the attached drawings, the present invention will be described by means of embodiment(s) below.
According to a preferred embodiment of the present invention, a chip packaging process integrating burn-in test is illustrated as shown in
Firstly, before the step 31 of “wafer lapping”, a wafer is provided can be shown in
The step 31 of “wafer lapping” can be shown in
Then, step 32 of “die sawing” is executed. As shown in
Next, steps 33 to 38 including burn-in test are executed on a substrate strip as shown from
As shown in
Then, step 34 of “electrically connecting” can be shown in
Then, as shown in
Then, as shown in
Preferably, the above described PMC step 36 further comprises a high temperature storage test which can be executed to further enhance to screen the failed packages.
In the present embodiment, without any limitations, the terminal-depositing step 37 can be further executed after PMC step 36 and before step 38 of package singulation. As shown in
Finally, the package singulation step 38 is executed as shown in
The chip packaging process is implemented to simplify overall packaging and testing process flow according to the present invention. As shown in
The above description of embodiments of this invention is intended to be illustrative and not limiting. Other embodiments of this invention will be obvious to those skilled in the art in view of the above disclosure.
Claims
1. A chip packaging process comprising:
- providing one or more chips;
- depositing the chips on one or more units of a substrate strip, each unit having a die-attaching surface and a corresponding SMT surface, a plurality of external pads formed on the SMT surface;
- electrically connecting the chips to the corresponding units;
- forming an encapsulant on the substrate strip to encapsulate the chips;
- executing a post mold curing step to completely cure the encapsulant, meanwhile, executing a burn-in testing step where the external pads of the substrate strip are electrically contacted by a plurality of probing terminals of a burn-in probing board, where the substrate strip has a plurality of electrical open sections at the plating lines before the post mold curing step to electrically isolate the external pads between different units; and
- executing a singulation step to form a plurality of individual chip packages each including a unit and the encapsulated chip by sawing the substrate strip.
2. The chip packaging process as claimed in claim 1, wherein the post mold curing step further includes a high-temperature storage test executed at the same time.
3. The chip packaging process as claimed in claim 1, further comprising the step of depositing a plurality of external terminals on the external pads of the substrate strip after the post mold curing step and before the singulation step.
4. The chip packaging process as claimed in claim 3, wherein the external terminals include a plurality of solder balls.
5. The chip packaging process as claimed in claim 1, wherein the electrical open sections are formed at the peripheries of the units on the SMT surface.
6. The chip packaging process as claimed in claim 1, wherein the electrical open sections are formed within one or more wire-bonding slots of the units.
7. The chip packaging process as claimed in claim 1, wherein each unit further has a wire-bonding slot and a plurality of bonding fingers adjacent to the wire-bonding slot, the chip has a plurality of bonding pads aligned in and exposed from the wire-bonding slot, moreover, a plurality of bonding wires are formed to connect the bonding pads with the bonding fingers during the electrically connecting step.
8. The chip packaging process as claimed in claim 1, wherein the encapsulant is sawed at the same time of sawing the substrate strip.
9. The chip packaging process as claimed in claim 1, wherein the electric open sections are formed before the die-attaching process.
10. The chip packaging process as claimed in claim 1, wherein the electrical open sections are formed after forming the encapsulant.
Type: Application
Filed: Nov 28, 2007
Publication Date: May 28, 2009
Applicant:
Inventors: Li-Chih Fang (Hsinchu), Wen-Jeng Fan (Hsinchu)
Application Number: 11/987,235
International Classification: H01L 21/66 (20060101);