Abstract: A method for processing a silicon wafer, the method including cutting an ingot to form a wafer, extracting from measured shape data a cross-sectional profile, the cross-sectional profile passing through the center of the wafer and being aligned with a cutting direction of an ingot, interpolating the shape data with a fixed and pre-determined step size, fitting a first second-degree polynomial to the cross-sectional profile, determining a residual profile by subtracting the polynomial from the cross-sectional profile, fitting a second second-degree polynomial to the residual profile using a sliding window of pre-determined width to determine a position, height, and curvature of each peak and valley of the residual profile, determining a waviness parameter based on the position, height, and curvature of each peak and valley of the residual profile, and further processing the wafer based on the waviness parameter and a predetermined waviness threshold.

Abstract: A semiconductor package includes a die attach pad; a plurality of lead terminals disposed around the die attach pad; a semiconductor die mounted on the die attach pad; a molding compound encapsulating the plurality of lead terminals, the semiconductor die, and the die attach pad; and a step cut sawn into the molding compound along a perimeter of a bottom surface of the semiconductor package. The step cut penetrates through an entire thickness of each of the plurality of lead terminals, whereby each of the plurality of lead terminals has at least an exposed outer end at the step cut.

Abstract: A semiconductor package includes a supporting wiring structure including a first redistribution dielectric layer and a first redistribution conductive structure; a frame on the supporting wiring structure, having a mounting space and a through hole, and including a conductive material; a semiconductor chip in the mounting space and electrically connected to the first redistribution conductive structure; a cover wiring structure on the frame and the semiconductor chip and including a second redistribution dielectric layer and a second redistribution conductive structure; an antenna structure on the cover wiring structure; a connection structure extending in the through hole and electrically connecting the first redistribution conductive structure to the second redistribution conductive structure; and a dielectric filling member between the connection structure in the through hole and the frame and surrounding the semiconductor chip, the frame, and the connection structure.

Abstract: An electronic device including a substrate, an electronic unit, a data line, a control unit, a test pad and a test switch element is provided by the present disclosure. The substrate includes a first surface and a second surface opposite to the first surface, wherein the first surface includes an active area. The electronic unit is disposed on the substrate and located in the active area. The data line is disposed on the substrate. The control unit is disposed on the substrate and located in the active area, and the control unit is electrically connected between the electronic unit and the data line. The test pad is disposed on the second surface of the substrate. The test switch element is disposed on the substrate and located in the active area, and the test switch element is electrically connected between the data line and the test pad.

Abstract: A method of picking up a die may include classifying a pickup region of a diced wafer, in which targeted pickup dies are placed, into first to n-th regions and performing a pickup step on dies in the first to n-th regions. The first region may include first dies, which are outermost dies of the targeted pickup dies. An (x+1)-th region may include regions, occupied by dies adjacent to at least one of x-th dies in an x-th region and proximate to a center of the pickup region in relation to the x-th region, n may be a natural number, and x may be an arbitrary natural number that is smaller than the n. The n-th region may have a rectangular shape, and a quantity of n-th dies in the n-th region in contact with a short side of the n-th region may be one or two.

Abstract: A semiconductor package includes a supporting wiring structure including a first redistribution dielectric layer and a first redistribution conductive structure; a frame on the supporting wiring structure, having a mounting space and a through hole, and including a conductive material; a semiconductor chip in the mounting space and electrically connected to the first redistribution conductive structure; a cover wiring structure on the frame and the semiconductor chip and including a second redistribution dielectric layer and a second redistribution conductive structure; an antenna structure on the cover wiring structure; a connection structure extending in the through hole and electrically connecting the first redistribution conductive structure to the second redistribution conductive structure; and a dielectric filling member between the connection structure in the through hole and the frame and surrounding the semiconductor chip, the frame, and the connection structure.

Abstract: A display device includes a substrate includes a display area having a plurality of pixels, a pad area including a plurality of input pads, and a circuit area positioned between the pad area and the display area; a crack sensor having a first end and a second end, the first end being connected to a first input pad of the plurality of input pads; a first shorting element extending through the pad area, the first shorting element being connected to the second end and extending to an edge of the substrate; a plurality of data lines connected to the plurality of pixels; and a crack sensing circuit including a first switching element having an input terminal connected to the first end and an output terminal connected to a first data line of the plurality of data lines, and a second switching element having an input terminal connected to the second end and an output terminal connected to a second data line of the plurality of data lines.

Abstract: A semiconductor device includes a metal base, a semiconductor chip provided on the metal base, and a frame work located on the metal base and having a metal pattern of an input pattern, an output pattern, and a bias pad. The bias pad and the input pattern or the output pattern are electrically connected by a conductor located on the frame work. The conductor has a characteristic of isolation at a frequency around an input signal or an output signal of the semiconductor device.

Abstract: A display device including a substrate having a display area and a non-display area outside the display area, a plurality of pixels disposed on the substrate in the display area, an external circuit bonded on the substrate in the non-display area, a first signal line disposed on the substrate in the non-display area and surrounding at least a portion of the display area, the first signal line being electrically connected to the external circuit, and a second signal line disposed in the non-display area and surrounding at least a portion of the first signal line, the second signal line being electrically connected to the external circuits.

Abstract: A display device includes a substrate including a display area, a hole area, a peripheral area, and a bending area, a printed circuit board disposed on the pad area, a first hole crack detection line and a second hole crack detection line disposed in the peripheral area and extending to the bending area and the pad area, a first transistor including a gate electrode connected to a first signal line to apply a first signal, a first electrode, and a second electrode connected to the first hole crack detection line, and a second transistor including a gate electrode connected to a second signal line to receive a second signal, a first electrode connected to a high voltage line applying a high voltage, and a second electrode connected to the first hole crack detection line.

Abstract: Embodiments of the present application provide a semiconductor structure that comprises a semiconductor substrate having a first surface and a second surface opposite to the first surface, a solder pad located at the first surface, a heat transfer layer located at the first surface and being in contact with the solder pad, and a groove located in the semiconductor substrate and being connected to the heat transfer layer.

Abstract: Disclosed is a method for detecting coverage rate of an intermetallic compound, the method comprising putting a chip subjected to wire bonding into a mixed reagent of fuming nitric acid and fuming sulfuric acid for soaking, wherein the chip subjected to wire bonding comprises a silver wire and an aluminum; taking out the chip after the silver wire is removed; and detecting the coverage rate of an intermetallic compound on the aluminum pad.

Abstract: Provided in a method of fabricating an optical element array including providing a silicon substrate, providing a first element layer on the silicon substrate, the first element layer including a plurality of passive optical elements, providing a plurality of semiconductor blocks on a compound semiconductor wafer, providing semiconductor dies by dicing the compound semiconductor wafer by the plurality of semiconductor blocks, and providing a second element layer by providing the semiconductor dies on the first element layer, each of the plurality of semiconductor blocks contacting at least one corresponding passive optical element from among the plurality of passive optical elements.

Abstract: A method of manufacturing a semiconductor memory device includes processing a first substrate including a first align mark and a first structure, processing a second substrate including a second align mark and a second structure, orientating the first substrate and the second substrate such that the first structure and the second structure face each other, and controlling alignment between the first structure and the second structure by using the first align mark and the second align mark to couple the first structure with the second structure.

Abstract: An apparatus for aligning a device having a fine pitch includes: a base plate, which has vacuum holes respectively formed at seating points for devices and suctions the devices with the vacuum pressure that allows minute movement as the vacuum pressure is applied in a state in which the devices are loaded; a jig plate, which is fixedly installed so as to be positioned on the upper portion of the base plate and has openings, in which the devices are received, in the same number as the number of the devices loaded on the base plate; and a base plate position adjusting means for finely moving the positions of the devices loaded on the base plate in X-Y-? directions so as to position the devices in the openings (formed in the jig plate.

Abstract: A semiconductor package includes a base including a first bonding structure; and a first semiconductor chip, including a second bonding structure, the second bonding structure being coupled to the first bonding structure of the base, wherein the first bonding structure includes: a test pad; a first pad being electrically connected to the test pad; and a first insulating layer, wherein the second bonding structure includes: a second pad being electrically connected to the first pad; and a second insulating layer being in contact with the first insulating layer, and wherein at least a portion of the test pad is in contact with the second insulating layer.

Abstract: A device including a first voltage domain and a second voltage domain is provided, the voltage domains being separated by an isolation barrier. In addition, the device includes a scratch detection circuit including a first and a second electrode at a distance of less than 2 ?m.

Abstract: A device, mechanism, and methodology for regular and consistent cleaning of the vacuum aperture, nozzle, and contacting surfaces of a pick-and-place apparatus and the pick-up tools of automated or manual semiconductor device and die handling machines are disclosed. The cleaning material may include a cleaning pad layer with one or more intermediate layers that have predetermined characteristics, regular geometrical features, and/or an irregular surface morphology.

Abstract: A semiconductor package includes: a first wiring pattern; a dielectric layer that covers the first wiring pattern; a second wiring pattern on the dielectric layer, wherein the second wiring pattern includes a line part that extends in a first direction and a via part that connects the line part to the first wiring pattern; a pad pattern electrically connected to the second wiring pattern, wherein the pad pattern includes a connection part and an extension part, wherein the connection part covers a first surface of the line part of the second wiring pattern, and the extension part has a top surface at a level lower than a level of the top surface of the line part of the second wiring pattern; and a seed pattern between the extension part and the dielectric layer.

Abstract: A wafer processing method for processing a wafer formed on a front surface thereof with a plurality of devices having projection-shaped electrodes, the devices being partitioned by streets, includes a cutting step of holding a back surface of the wafer by a holding surface of a chuck table and cutting head portions of the projection-shaped electrodes by a cutting tool slewed in parallel to the holding surface, to make uniform the electrodes in height and expose metallic surfaces; a thermocompression bonding sheet laying step of laying a thermocompression bonding sheet on the front surface of the wafer; a thermocompression bonding step of heating and pressing the thermocompression bonding sheet to perform thermocompression bonding; and a peeling step of peeling off the thermocompression bonding sheet from the wafer, before dividing the wafer into individual device chips and bonding the electrodes to a circuit board.

Abstract: The present application provides a semiconductor module and a power conversion device wherein wiring inductance is reduced. The semiconductor module is characterized by including a semiconductor element, a first terminal on which the semiconductor element is mounted, a second terminal disposed in a periphery of the semiconductor element and having a multiple of wiring portions, and a multiple of connection lines extending in multiple directions from an upper face of the semiconductor element and connected to each of the multiple of wiring portions of the second terminal, wherein a free region is provided among the multiple of wiring portions, and the multiple of connection lines and the multiple of wiring portions forming current paths with each of the multiple of connection lines are of the same potential.

Abstract: An object of the present disclosure is to be able to further reduce the size of a substrate structure including a plurality of elements. The substrate structure includes: a base substrate that includes a first conductive plate and a second conductive plate; a first element connected to the first conductive plate and the second conductive plate; and a second element connected to the first conductive plate and the second conductive plate. The first conductive plate and the second conductive plate are disposed on the same plane on the base substrate in a state of being electrically insulated from each other, the first element is mounted on a first main surface of the base substrate, and the second element is mounted on a second main surface that is on the opposite side to the first main surface relative to the base substrate.

Abstract: Provided in a method of fabricating an optical element array including providing a silicon substrate, providing a first element layer on the silicon substrate, the first element layer including a plurality of passive optical elements, providing a plurality of semiconductor blocks on a compound semiconductor wafer, providing semiconductor dies by dicing the compound semiconductor wafer by the plurality of semiconductor blocks, and providing a second element layer by providing the semiconductor dies on the first element layer, each of the plurality of semiconductor blocks contacting at least one corresponding passive optical element from among the plurality of passive optical elements.

Abstract: A method includes, receiving a layout design of at least part of an electronic module, the design specifying at least (i) an electronic device coupled to at least a substrate, and (ii) an electrical trace that is connected to the electronic device and has a designed route. A digital input, which represents at least part of an actual electronic module that was manufactured in accordance with the layout design but without at least a portion of the electrical trace, is received. An error in coupling the electronic device to the substrate, relative to the layout design, is estimated based on the digital input. An actual route that corrects the estimated error, is calculated for at least the portion of the electrical trace. At least the portion of the electrical trace is formed on the substrate of the actual electronic module, along the actual route instead of the designed route.

Abstract: In a method of manufacturing a semiconductor package, information with respect to a downward warpage of a reference package substrate, which may be bent with respect to a long axis and/or a short axis of the reference package substrate in applying heat to the reference package substrate to which a plurality of semiconductor chips may be attached using a die attach film (DAF), may be obtained. A package substrate, which may include a first surface to which the semiconductor chips may be attached using the DAF and a second surface opposite to the first surface, may be rotated with respect to the long axis or the short axis at an angle selected based on the information. The heat may be applied to the package substrate to cure the DAF and correct a warpage of the package substrate. Thus, warpage of the package substrate may be corrected for.

Abstract: A semiconductor package includes a supporting wiring structure including a first redistribution dielectric layer and a first redistribution conductive structure; a frame on the supporting wiring structure, having a mounting space and a through hole, and including a conductive material; a semiconductor chip in the mounting space and electrically connected to the first redistribution conductive structure; a cover wiring structure on the frame and the semiconductor chip and including a second redistribution dielectric layer and a second redistribution conductive structure; an antenna structure on the cover wiring structure; a connection structure extending in the through hole and electrically connecting the first redistribution conductive structure to the second redistribution conductive structure; and a dielectric filling member between the connection structure in the through hole and the frame and surrounding the semiconductor chip, the frame, and the connection structure.

Abstract: A semiconductor device includes a semiconductor substrate including a chip region and an edge region around the chip region, a lower insulating layer on the semiconductor substrate, a chip pad on the lower insulating layer on the chip region, an upper insulating layer provided on the lower insulating layer to cover the chip pad, the upper and different insulating layers including different materials, and a redistribution chip pad on the chip region and connected to the chip pad. The upper insulating layer includes a first portion on the chip region having a first thickness, a second portion on the edge region having a second thickness, and a third portion on the edge region, the third portion extending from the second portion, spaced from the first portion, and having a decreasing thickness away from the second portion. The second thickness is smaller than the first thickness.

Abstract: A method of producing a laser diode bar includes producing a plurality of emitters arranged side by side, emitters each including a semiconductor layer sequence having an active layer that generates laser radiation, a p-contact on a first main surface of the laser diode bar and an n-contact on a second main surface of the laser diode bar opposite the first main surface, testing at least one optical and/or electrical property of the emitters, wherein emitters in which the optical and/or electrical property lies within a predetermined setpoint range are assigned to a group of first emitters, and emitters in which the at least one optical and/or electrical property lies outside the predetermined setpoint range are assigned to a group of second emitters, and electrically contacting first emitters, wherein second emitters are not electrically contacted so that they are not supplied with current during operation of the laser diode bar.

Abstract: A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump.

Abstract: A semiconductor package includes an interposer, a number of a first integrated circuit (IC) dies, one or more second IC dies, and one or more dummy dies. The first IC dies, the second IC dies and the dummy dies are implemented on the interposer. The dummy dies are configured to enable routing of pins of the first IC dies to selected circuits of the second IC dies while conforming to predefined routing rules.

Abstract: An apparatus comprises a transceiver (Tx/Rx) printed circuit board (PCB) with a top surface and a bottom surface and a power supply PCB. The Tx/Rx PCB includes two transmitter devices, each comprising a number N of channels. A first transmitter device is arranged on the bottom surface and a second transmitter device is arranged on the top surface over the first transmitter device. One or more pins of the second transmitter device are shorted with one or more pins of the first transmitter device with the same function. An analog front end (AFE) device comprising N input channels is arranged on the top surface of the Tx/Rx PCB, and a digital signal processor is coupled to the AFE device. The power supply PCB comprises a power supply module configured to provide a plurality of supply voltages to the Tx/Rx PCB and the power supply PCB.

Abstract: A semiconductor wafer includes a silicon carbide wafer and an epitaxial layer, which is disposed at a surface of the silicon carbide wafer and made of silicon carbide. The semiconductor wafer satisfies a condition that a waviness value is equal to or smaller than 1 micrometer. The waviness value is a sum of an absolute value of a value ? and an absolute value of a value ?. A highest height among respective heights of a plurality of points with reference to a surface reference plane within a light exposure area is denoted as the value ?. A lowest height among the respective heights of the points at the epitaxial layer with reference to the surface reference plane within the light exposure area is denoted as the value ?.

Abstract: The disclosure concerns an electronic device and methods of making an electronic device. The electronic device includes a circuit that is at least partially formed in an active region of a substrate. An electronic package is stacked on the substrate. A via extends through the circuit from the active region of the substrate to a surface of the substrate that is opposite the active region. At least one contacting element connects the via to the electronic package.

Abstract: A pick and place LED testing apparatus, comprising: a test station operative in use to power a group of LEDs; a bondhead operative in use to pick said group of LEDs from a source wafer and place said group of LEDs on said test station for testing; and an optical sensor operative in use to measure an optical characteristic of said group of LEDs when tested, wherein at least a portion of said bondhead is translucent to provide an optical path from said group of LEDs to said optical sensor.

Abstract: In a method of manufacture, a displacement sensor is provided over a conditioner disk. The conditioner disk is rotated to perform a conditioning process on a polishing surface of a polishing pad. A displacement of the rotating conditioner disk is detected using the displacement sensor during the conditioning process. A height of the conditioner disk is calculated from the detected displacement. An end point of the conditioning process is determined on the polishing surface based on the calculated height.

Abstract: A device includes a substrate, a vertical cavity surface emitting laser (VCSEL) array on top of the substrate, a via through the substrate and the VCSEL array, a first electrode extended from a top of the VCSEL array to a bottom of the substrate, through the via, the first electrode electrically connected to the VCSEL array, a second electrode on the bottom of the substrate, the second electrode electrically connected to the VCSEL array, and an isolator in the via providing electrical isolation between the first electrode and the second electrode.

Abstract: A computer-implemented method of authenticating a product comprises receiving, from a scanner terminal, a query message including a hapto-signature of the product to be authenticated, the hapto-signature including at least one haptic characteristic of the product as scanned by a touch-sensitive surface of the scanner terminal. The method comprises comparing the received hapto-signature against a hapto-signature database comprising a plurality of reference hapto-signatures, each reference hapto-signature having an associated product, to determine whether or not the received hapto-signature matches at least one of the reference hapto-signatures, wherein a determination that the received hapto-signature matches at least one of the reference hapto-signatures indicates that the product is authentic. The method comprises generating and sending a response message indicative of whether or not the received hapto-signature matches at least one of the reference hapto-signature.

Abstract: The proposed masking dam protects ball grid array integrated circuit components from conformal coating overflow, preventing joint breakage and thermal mismatch. The masking dam includes a frame with an integrated seal, a cover, and a fastening mechanism. The frame is sealed to a circuit board surround a component, the cover is attached to the frame, and the masking dam is secured to protect the component.

Abstract: A micro LED transfer device is provided. The micro LED transfer device includes a transfer part configured to arrange a first substrate wherein a plurality of LEDs are disposed on a lower surface relative to an upper surface of a second substrate; a memory storing characteristic information of each of the plurality of LEDs; a laser light source configured to irradiate laser light; a mask comprising a plurality of shutters configured to selectively open and close a plurality of openings of the mask, the mask being interposed between the first substrate and the laser light source; and a processor configured to identify an LED from among the plurality of LEDs to be arranged on the second substrate based on the stored characteristic information, and control the mask such that a shutter from among the plurality of shutters that corresponds to the LED is opened.

Abstract: There is provided an apparatus including a substrate holder to hold substrates including a product substrate and a dummy substrate, a transfer mechanism that loads the substrates into the substrate holder, a storage part to store a device parameter including at least the number of substrates that can be loaded on the substrate holder and the number of product substrates to be loaded on the substrate holder, and a controller to: (1) create substrate transfer data, which includes information indicating an order for transferring the substrates, transfer source information, and transfer destination information, according to the device parameter, (2) read the created substrate transfer data, (3) by transferring the substrates to the transfer mechanism based on the read substrate transfer data, transfer the dummy substrate to a substrate holding region except for a heat equalization region, and transfer the product substrate to the heat equalization region on the substrate holder.

Abstract: A method for fault detection in a fabrication tool is provided. The method includes processing a semiconductor wafer in a fabrication tool according to a plurality of process events of a process run. The method further includes measuring humidity in the fabrication tool in at least one of the process events. The method also includes comparing the humidity measured in one of the process events with an expected humidity associated with the process event. In addition, the method includes based on the comparison, indicating an alarm condition when a difference between the measured humidity and the expected humidity exceeds a range of acceptable values associated with the process event.

Abstract: A memory module includes a first redistribution structure, a second redistribution structure, first semiconductor dies, second semiconductor dies, an encapsulant, through insulator vias and thermally conductive material. Second redistribution structure is stacked over first redistribution structure. First semiconductor dies are sandwiched between first redistribution structure and second redistribution structure and disposed side by side. Second semiconductor dies are disposed on the second redistribution structure. The encapsulant laterally wraps the second semiconductor dies. The through insulator vias are disposed among the first semiconductor dies, extending from the first redistribution structure to the second redistribution structure. The through insulator vias are electrically connected to the first redistribution structure and the second redistribution structure.

Abstract: A method of predicting the dominant failure mode and/or the failure rate of a plurality of features formed on a substrate, and an associated inspection apparatus. The method may include determining a placement metric for each feature, the placement metric including a measure of whether the feature is in an expected position, and comparing a distribution of the placement metric to a reference (e.g., Gaussian) distribution. The placement metric may include a boundary metric for a plurality of boundary points on a boundary defining each feature, the boundary metric including a measure of whether a boundary point is in an expected position. The dominant failure mode and/or the failure rate of the plurality of features is predicted from the comparison.

Abstract: The present disclosure provides a dehydrating chemical for dehydrating a semiconductor substrate under an ambient temperature, including a first chemical having a melting point below the ambient temperature, and a second chemical having a melting point greater than the melting point of the first chemical, wherein the dehydrating chemical has a melting point less than the ambient temperature by predetermined ?T0 degrees, and at least one of the first chemical and the second chemical has a saturated vapor pressure greater than a predetermined pressure PSV under 1 atm.

Abstract: A method of forming a semiconductor device includes forming a plurality of metal pads over a semiconductor substrate of a wafer, forming a passivation layer covering the plurality of metal pads, patterning the passivation layer to reveal the plurality of metal pads, forming a first polymer layer over the passivation layer, forming a plurality of redistribution lines extending into the first polymer layer and the passivation layer to connect to the plurality of metal pads, forming a second polymer layer over the first polymer layer, and patterning the second polymer layer to reveal the plurality of redistribution lines. The first polymer layer is further revealed through openings in remaining portions of the second polymer layer.

Abstract: Systems and methods for efficient transfer of elements are disclosed. A film which supports a plurality of diced integrated device dies can be provided. The plurality of diced integrated device dies can be disposed adjacent one another along a surface of the film. The film can be positioned adjacent the support structure such that the surface of the film faces a support surface of the support structure. The film can be selectively positioned laterally relative to the support structure such that a selected first die is aligned with a first location of the support structure. A force can be applied in a direction nonparallel to the surface of the film to cause the selected first die to be directly transferred from the film to the support structure.

Abstract: A computer-implemented method for sorting non-volatile random access memories (NVRAMS) includes testing a failure metric for each of a plurality of NVRAMS over a plurality of testing sessions to capture failure metric data that corresponds to the plurality of NVRAMS. The method also includes determining a trend in the failure metric as a function of testing cycles for each of the plurality of NVRAMS from the failure metric data, and separating the plurality of NVRAMS into groups based on the trend in the failure metric as a function of testing cycles. A corresponding computer program product and computer system are also disclosed herein.

Abstract: The present invention relates to a device and method for self-assembling semiconductor light-emitting diodes. Particularly, a method for manufacturing a display device according to the present invention includes: feeding a substrate to an assembly site and putting semiconductor light-emitting diodes having a magnetic material into a fluid chamber; applying a magnetic force to the semiconductor light-emitting diodes so that the semiconductor light-emitting diodes move in one direction within the fluid chamber; and guiding the semiconductor light-emitting diodes to preset positions on the substrate by applying an electric field, so that the semiconductor light-emitting diodes are mounted at the preset positions while in the process of being moved.

Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.

Abstract: An optoelectronic device and a method are disclosed.