Packaging (e.g., With Mounting, Encapsulating, Etc.) Or Treatment Of Packaged Semiconductor Patents (Class 438/15)
  • Patent number: 10896902
    Abstract: Systems and methods for efficient transfer of elements are disclosed. A film which supports a plurality of diced integrated device dies can be provided. The plurality of diced integrated device dies can be disposed adjacent one another along a surface of the film. The film can be positioned adjacent the support structure such that the surface of the film faces a support surface of the support structure. The film can be selectively positioned laterally relative to the support structure such that a selected first die is aligned with a first location of the support structure. A force can be applied in a direction nonparallel to the surface of the film to cause the selected first die to be directly transferred from the film to the support structure.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: January 19, 2021
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Cyprian Emeka Uzoh, Paul M. Enquist, Gaius Gillman Fountain, Jr.
  • Patent number: 10886004
    Abstract: A computer-implemented method for sorting non-volatile random access memories (NVRAMS) includes testing a failure metric for each of a plurality of NVRAMS over a plurality of testing sessions to capture failure metric data that corresponds to the plurality of NVRAMS. The method also includes determining a trend in the failure metric as a function of testing cycles for each of the plurality of NVRAMS from the failure metric data, and separating the plurality of NVRAMS into groups based on the trend in the failure metric as a function of testing cycles. A corresponding computer program product and computer system are also disclosed herein.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey W. Christensen, Phillip E. Christensen, Daniel E. Moore, Antoine G. Sater, Jung H. Yoon
  • Patent number: 10825702
    Abstract: The present invention relates to a device and method for self-assembling semiconductor light-emitting diodes. Particularly, a method for manufacturing a display device according to the present invention includes: feeding a substrate to an assembly site and putting semiconductor light-emitting diodes having a magnetic material into a fluid chamber; applying a magnetic force to the semiconductor light-emitting diodes so that the semiconductor light-emitting diodes move in one direction within the fluid chamber; and guiding the semiconductor light-emitting diodes to preset positions on the substrate by applying an electric field, so that the semiconductor light-emitting diodes are mounted at the preset positions while in the process of being moved.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: November 3, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Bongchu Shim, Dohee Kim, Changseo Park, Hyunwoo Cho
  • Patent number: 10811338
    Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Horng Chang, Jie-Cheng Deng, Tin-Hao Kuo, Ying-Yu Chen
  • Patent number: 10804433
    Abstract: An optoelectronic device and a method are disclosed.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: October 13, 2020
    Assignee: OSRAM OLED GMBH
    Inventors: Alexander F. Pfeuffer, Sophia Huppmann, Andrea Winnerl, Jens Müller
  • Patent number: 10763415
    Abstract: Disclosed is a method for manufacturing a semiconductor light emitting device, the method including: providing a mask having a plurality of openings on a base; placing semiconductor light emitting chips on exposed portions of the base through the openings, respectively, by a device carrier which recognizes a shape of the mask and calibrates position for a semiconductor light emitting chip to be seated; and supplying an encapsulant to each of the openings, with the mask serving as a dam.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: September 1, 2020
    Assignee: SEMICON LIGHT CO., LTD.
    Inventors: Soo Kun Jeon, Seung Ho Baek, Da Rae Lee, Bong Hwan Kim, Dong So Jung
  • Patent number: 10748824
    Abstract: Representative implementations of devices and techniques provide a temporary access point (e.g., for testing, programming, etc.) for a targeted interconnect located among multiple finely spaced interconnects on a surface of a microelectronic component. One or more sacrificial layers are disposed on the surface of the microelectronic component, overlaying the multiple interconnects. An insulating layer is disposed between a conductive layer and the surface, and includes a conductive via through the insulating layer that electrically couples the conductive layer to the target interconnect. The sacrificial layers are configured to be removed after the target interconnect has been accessed, without damaging the surface of the microelectronic component.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: August 18, 2020
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Javier A. Delacruz, Paul M. Enquist, Gaius Gillman Fountain, Jr., Ilyas Mohammed
  • Patent number: 10741415
    Abstract: A method of making a package is disclosed. The method may include forming bond pads on a first surface of a substrate, forming leads in the substrate by etching recesses in a second surface of the substrate, the second surface being opposite the first surface, and plating at least a portion of a top surface of the leads with a layer of finish plating. The method may also include thermosonically bonding the leads to a die by thermosonically bonding the finish plating to the die and encapsulating the die and the leads in an encapsulant.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: August 11, 2020
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Mauro Mazzola, Battista Vitali, Matteo De Santa
  • Patent number: 10727112
    Abstract: A method for rewiring of semiconductor devices is provided, in which deviations of electrical connection terminals (211, 212, 221, 222, 231, 232) on a carrier (100) are calculated and corrected by forming rewiring structures on the electrical connection terminals by mask-free photolithography. A wiring layer and/or solder balls (700) is/are then formed on the rewiring structures by processing the carrier (100) in a monolithic manner using mask-based photolithography. In this way, the combined use of mask-free photolithography and mask-based photolithography allows for higher efficiency and a shorter process cycle, compared to only using mask-free photolithography.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: July 28, 2020
    Assignee: SHANGHAI MICRO ELECTRONICS EQUIPMENT (GROUP) CO., LTD.
    Inventors: Yonghui Chen, Shiyi Tang
  • Patent number: 10699977
    Abstract: A method of detecting delamination in an integrated circuit package structure, the method includes forming a plurality of through vias over a carrier substrate; placing a device die over the carrier substrate and between the through vias, wherein the device die comprises a metal pillar; forming a molding material surrounding the device die and the through vias; forming a testing metal line extending along a top surface of the molding material and past an interface between the device die and the molding material; applying a current to the testing metal line; detecting an electrical signal of the testing metal line during the applying the current to the testing metal line; and determining, based on the detected electrical signal of the testing metal line, whether a delamination occurs between the device die and the molding material.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yang-Che Chen, Tsung-Te Chou, Chen-Hua Lin, Huang-Wen Tseng, Chwen-Ming Liu
  • Patent number: 10657639
    Abstract: Systems and methods for identifying defective individual packaged modules are presented. A Printed Circuit Board (PCB) having a set of individual module substrates can be received. Further, capturing an image of the PCB and loading a PCB recipe associated with the PCB can be performed. The image of the PCB can be captured by an image capture module that can include one or more cameras. For each individual module substrate, a portion of the image corresponding to the individual module substrate can be compared to the PCB recipe. In addition, it can be determined based on the comparison whether the individual module substrate matches the PCB recipe within a degree of tolerance. In response to determining that the individual module substrate does not match the PCB recipe within the degree of tolerance, a location of the individual module substrate within a map of the PCB can be stored.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: May 19, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventors: Carlos Fabian Nava, Viviano Almonte
  • Patent number: 10573601
    Abstract: A semiconductor device may include a semiconductor die disposed within an encapsulant, the semiconductor die being misaligned with a package edge formed by the encapsulant. A total radial shift of the semiconductor die may account for the misalignment between semiconductor die and the package edge. A build-up interconnect structure may comprise two or more layers formed over the semiconductor die and the encapsulant, the two or more layers comprising at least one redistribution layer (RDL). The total radial shift may be distributed over the two or more layers of the build-up interconnect structure to form a unit specific pattern for each of the two or more layers. An average misalignment of the semiconductor die and the package edge may be greater than the average misalignment of the at least one unit specific pattern with respect to the package edge.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: February 25, 2020
    Assignee: Deca Technologies Inc.
    Inventors: Christopher M. Scanlan, Craig Bishop
  • Patent number: 10529632
    Abstract: A method, in some embodiments, comprises: providing a component having first and second electrical nodes; determining that the component lacks multiple, functional electrical couplings between said first and second nodes; damaging at least part of the component as a result of said determination; and determining, as a result of said damage, that the component is defective.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: January 7, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Darrell D. Truhitte, James P. Letterman, Jr.
  • Patent number: 10473714
    Abstract: A method for automated alignment between a plurality of electronic components and at least one testing device for receiving the electronic components for testing which includes defining a fiducial marker and positioning a moveable imaging device relative to a stationary imaging device, such that the fiducial marker is within a field of view of the moveable imaging device and within a field of view of the stationary imaging device. The moveable imaging device determines, with respect to each of the at least one testing device, a first offset between the testing device and the fidicual marker. The stationary imaging device determines, with respect to each electronic component, a second offset between the electronic component and the fidicual marker. Alignment is effected between each electronic component and the testing device in accordance with the first and second offsets.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: November 12, 2019
    Assignee: ASM TECHNOLOGY SINGAPORE PTE LTD
    Inventors: Chi Wah Cheng, Chi Hung Leung, Yu Sze Cheung, Kai Fung Lau
  • Patent number: 10459007
    Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: October 29, 2019
    Assignee: VIA Technologies, Inc.
    Inventors: Chen-Yueh Kung, Wen-Yuan Chang, Wei-Cheng Chen
  • Patent number: 10412869
    Abstract: A component mounting device performs measurement of a position of a reference section of a head and measurement of calibration data of the head, and the calibration data of the head and the position of the reference section are stored in association. The component mounting device controls operation of the head holding body in which the head is held based on the calibration data of the head and the position of the reference section. In a case where it is not necessary to generate the calibration data of the predetermined head, the component mounting device measures the position of the reference section, and controls operation of the head holding body in which the head is held based on the measured position of the reference section, the position of the reference section which is stored, and the calibration data of the head.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: September 10, 2019
    Assignee: FUJI CORPORATION
    Inventor: Ryohei Kamio
  • Patent number: 10199087
    Abstract: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: February 5, 2019
    Assignee: III HOLDINGS 2, LLC
    Inventor: Michael C. Stephens, Jr.
  • Patent number: 10170381
    Abstract: A semiconductor test system has a film frame including a tape portion with one or more openings through the tape portion. The opening is disposed in a center region of the tape portion of the film frame. The film frame may have conductive traces formed on or through the tape portion. A thin semiconductor wafer includes a conductive layer formed over a surface of the semiconductor wafer. The semiconductor wafer is mounted over the opening in the tape portion of the film frame. A wafer probe chuck includes a lower surface and raised surface. The film frame is mounted to the wafer probe chuck with the raised surface extending through the opening in the tape portion to contact the conductive layer of the semiconductor wafer. The semiconductor wafer is probe tested through the opening in the tape portion of the film frame.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: January 1, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Heng Chen Lee
  • Patent number: 10157803
    Abstract: A semiconductor device and method can comprise measuring a true position of each of a plurality of semiconductor die within an embedded die panel and determining a total radial shift of each of the plurality of semiconductor die. The total radial shift of each of the plurality of semiconductor die can be distributed to two or more layers for each of the plurality of semiconductor die by assigning a portion of the total radial shift to each of the layers according to a priority list to form a distributed radial shift for each of the layers. A transformation for each of the layers for each of the plurality of semiconductor die can be transformed using the distributed radial shift for each of the layers. A unit specific pattern can be formed over each of the plurality of semiconductor die with the transformation for each of the layers.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: December 18, 2018
    Assignee: DECA Technologies Inc.
    Inventors: Craig Bishop, Christopher M. Scanlan
  • Patent number: 10062679
    Abstract: Apparatuses and methods for forming die stacks are disclosed herein. An example method includes dispensing a temporary adhesive onto a substrate, placing a base die onto the temporary adhesive, curing the temporary adhesive, forming a die stack that includes the base die, activating a release layer disposed on the substrate, wherein the release layer is between the substrate and the temporary adhesive, removing the die stack from the substrate, and removing the temporary adhesive from the die stack.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: August 28, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Michel Koopmans
  • Patent number: 10032751
    Abstract: Capacitive coupling of integrated circuit die components and other conductive areas is provided. Each component to be coupled has a surface that includes at least one conductive area, such as a metal pad or plate. An ultrathin layer of dielectric is formed on at least one surface to be coupled. When the two components, e.g., one from each die, are permanently contacted together, the ultrathin layer of dielectric remains between the two surfaces, forming a capacitor or capacitive interface between the conductive areas of each respective component. The ultrathin layer of dielectric may be composed of multiple layers of various dielectrics, but in one implementation, the overall thickness is less than approximately 50 nanometers. The capacitance per unit area of the capacitive interface formed depends on the particular dielectric constants ? of the dielectric materials employed in the ultrathin layer and their respective thicknesses.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: July 24, 2018
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Arkalgud R. Sitaram
  • Patent number: 10014272
    Abstract: A method of bonding a die comprising solder bumps to a substrate comprising bond pads, the method comprising the steps of heating the die from a first temperature to a second temperature, wherein the first temperature is below the melting point of the solder bumps, and the second temperature is above the melting point of the solder bumps; moving the die relative to the substrate to a first height, whereat the solder bumps contact the bond pads; moving the die further away from the substrate to a second height, while maintaining contact between the solder bumps and bond pads; and thereafter cooling the die from the second temperature to a third temperature to allow the solder bumps to solidify so as to bond the die to the substrate.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: July 3, 2018
    Assignee: ASM TECHNOLOGY SINGAPORE PTE LTD
    Inventors: Dewen Tian, Yiu Ming Cheung, Ming Li
  • Patent number: 9899298
    Abstract: Methods for fabricating microelectronic packages, such as Fan-Out Wafer Level Packages, and microelectronic packages are provided. In one embodiment, the method includes placing a first semiconductor die on a temporary substrate, forming an electrically-conducive trace in contact with at least one of the first semiconductor die and the temporary substrate, and encapsulating the first semiconductor die and the electrically-conductive trace within a molded panel. The temporary substrate is removed to reveal a frontside of the molded panel through which the electrically-conducive trace is at least partially exposed. At least one redistribution layer is formed over the frontside of the molded panel, the at least one redistribution layer comprises an interconnect line in ohmic contact with the electrically-conducive trace.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: February 20, 2018
    Assignee: NXP USA, INC.
    Inventors: Michael B. Vincent, Zhiwei Gong, Jason R. Wright
  • Patent number: 9881910
    Abstract: Apparatuses and methods for forming die stacks are disclosed herein. An example method includes dispensing a temporary adhesive onto a substrate, placing a base die onto the temporary adhesive, curing the temporary adhesive, forming a die stack that includes the base die, activating a release layer disposed on the substrate, wherein the release layer is between the substrate and the temporary adhesive, removing the die stack from the substrate, and removing the temporary adhesive from the die stack.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: January 30, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Michel Koopmans
  • Patent number: 9824998
    Abstract: Provided are a device packing facility and method using DEHT and a device processing apparatus utilizing the DEHT. The device packaging facility includes a mounting unit providing bis(2-ethylhexyl) terephthalate (DEHT) between first and second devices to attach the first and second devices to each other, a processing unit thermally processing the first and second devices that are attached to each other to remove the DEHT and fix the first and second devices to each other, and a transfer unit transferring the first and second devices that are attached to each other from the mounting unit to the processing unit.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: November 21, 2017
    Assignee: Semigear, Inc.
    Inventors: Jian Zhang, Joshua Pinnolis, Shijian Luo
  • Patent number: 9818659
    Abstract: A method of making a semiconductor device can include forming an embedded die panel by encapsulating a first semiconductor die and a second semiconductor die with conductive interconnects in a single step. An actual position of the first semiconductor die and second semiconductor die can be measured within the embedded die panel. The first semiconductor die and the second semiconductor die can be interconnected by a build-up interconnect structure comprising a first unit specific alignment portion aligned with the first semiconductor die, a second unit specific alignment portion aligned with the second semiconductor die, unit specific routing connecting the first unit specific alignment portion and the second unit specific alignment portion, and a fixed portion aligned with outline of embedded die panel and coupled to the unit specific routing.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: November 14, 2017
    Assignee: DECA Technologies Inc.
    Inventor: Craig Bishop
  • Patent number: 9496189
    Abstract: Stacked semiconductor devices and methods of forming the same are disclosed. First tier workpieces are mounted on a top surface of a semiconductor device to form first tier stacks, the semiconductor device comprising one or more integrated circuit dies, the semiconductor device having one or more test pads per integrated circuit die on the top surface of the semiconductor device. Each of the first tier stacks is electrically tested to identify first known good stacks and first known bad stacks. Second tier workpieces are mounted atop the first known good stacks, thereby forming second tier stacks. Each of the second tier stacks is electrically tested to identify second known good stacks and second known bad stacks. Stacking process further comprises one or more workpiece mounting/testing cycles. The stacking process continues until the stacked semiconductor devices comprise desired number of workpieces.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: November 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chien-Hsun Lee, Tsung-Ding Wang, Jung Wei Cheng
  • Patent number: 9425174
    Abstract: An integrated circuit package may include an integrated circuit die and a package substrate having a conductive pad. A conductive pillar is formed on a front surface of the integrated circuit die and directly contacts the conductive pad. Prior to contacting the conductive pad directly, the conductive pillar may be positioned adjacent to the conductive pad such that it is aligned to the conductive pad. The integrated circuit package further includes an interconnect structure that is formed in the package substrate. The interconnect structure may include conductive traces that are electrically connected to the conductive pad and the conductive pillar. An additional integrated circuit die may be mounted on the package substrate. The additional integrated circuit die may couple to the integrated circuit die through the interconnect structure.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: August 23, 2016
    Assignee: Altera Corporation
    Inventors: Tze Yang Hin, Loon Kwang Tan, Chew Ching Lim
  • Patent number: 9373554
    Abstract: A method of monitoring an OLED production process for making an OLED device is disclosed. According to the method, at least one reference OLED device similar to said OLED device is fabricated. Said at least one reference OLED device has a layered structure corresponding to said OLED device and a range of hole injection and/or transport layer thicknesses. A spectral variation of a light output of said at least one reference OLED device with respect to variation in said hole injection and/or transport layer thickness is characterized. A said OLED device is partially fabricated by depositing one or more layers comprising at least said hole injection and/or transport layer and a thickness of said one or more layers is measured such that a light output for said partially fabricated OLED device can be predicted, in a target color space, from said measuring, using said characterized spectral variation.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: June 21, 2016
    Assignee: CAMBRIDGE DISPLAY TECHNOLOGY LIMITED
    Inventors: Graham Anderson, Michael Cass, Daniel Forsythe
  • Patent number: 9362248
    Abstract: A coreless package structure and a method for manufacturing same includes the steps of providing a supporting substrate comprising an etching resist layer and a copper foil. A groove is defined in the copper foil and a plurality of contact pads are formed on the surface of the copper foil. A chip including a plurality of electrode pads is received in the groove and a packaging layer is formed on a side of the copper foil. An insulating layer and a conductive pattern layer are formed on the packaging layer in that order, the conductive pattern layer being electrically connected to the contact pads and the electrode pads by a plurality of conductive bumps. Finally, the etching resist layer and the copper foil are removed to obtain a coreless package structure.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: June 7, 2016
    Assignee: Zhen Ding Technology Co., Ltd.
    Inventors: Yong Ha Woo, E-Tung Chou, Wen-Lun Lo
  • Patent number: 9310437
    Abstract: A method includes testing a first device and a second device identical to each other and comprising integrated circuits. The testing of the first device is performed according to a first test sequence of the first device, wherein the first test sequence includes a plurality of ordered test items, and wherein the first test sequence includes a test item. A test priority of the test item is calculated based on a frequency of fails of the test item in the testing of a plurality of devices having an identical structure as the first device. The first test sequence is then adjusted to generate a second test sequence in response to the test priority of the test item, wherein the second test sequence is different from the first test sequence. The second device is tested according to the second test sequence.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: April 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Cheng Chen, Hung-Chih Lin, Mill-Jer Wang, Hao Chen, Ching-Nen Peng
  • Patent number: 9293441
    Abstract: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: March 22, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Masataka Hoshino, Junichi Kasai, Kouichi Meguro, Ryota Fukuyama, Yasuhiro Shinma, Koji Taya, Masanori Onodera, Naomi Masuda
  • Patent number: 9287251
    Abstract: In a method, a first opening is formed in a first insulating interlayer on a first substrate. A first conductive pattern structure contacting a first diffusion prevention insulation pattern and having a planarized top surface is formed in the first opening. Likewise, a second conductive pattern structure contacting a second diffusion prevention insulation pattern is formed in a second insulating interlayer on a second substrate. A plasma treatment process is performed on at least one of the first and second substrates having the first and second conductive pattern structures thereon, respectively. The first and second conductive pattern structures are contacted to each other to bond the first and second substrates.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: March 15, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Pil-Kyu Kang, Seok-Ho Kim, Tae-Yeong Kim, Hyo-Ju Kim, Byung-Lyul Park, Yeun-Sang Park, Jin-Ho An, Ho-Jin Lee, Joo-Hee Jang, Deok-Young Jung
  • Patent number: 9277104
    Abstract: A method of assembling a vehicular camera includes providing a lens assembly having a base portion, a lens barrel and a plurality of optical elements in the lens barrel, and providing a circuit element having a circuit board and an imaging array. An adhesive bead is dispensed at the base portion and/or circuit element. The circuit element is placed at the base portion with the adhesive bead therebetween and the optical elements are aligned with the imaging array via a six axis robotic device when the circuit element is at the base portion and in contact with the adhesive bead. The adhesive bead is cured to a first cure level via exposure of the adhesive bead to ultraviolet light. The assembly is moved to a second curing stage and the adhesive bead is cured to a second cure level via heating the adhesive bead.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: March 1, 2016
    Assignee: Magna Electronics Inc.
    Inventors: Matthew C. Sesti, Robert A. Devota, Yuesheng Lu, Steven V. Byrne, Joel S. Gibson
  • Patent number: 9257812
    Abstract: Provided is a laser module wherein any defective laser device can be isolated by performing burn-in on laser devices mounted on a mounting substrate. The laser module includes laser devices that emit laser light, a driver IC for driving the laser devices, a mounting substrate on which the laser devices and the driver IC are mounted, a common electrode terminal to which a common electrode of the laser devices is connected, individual electrode terminals to which individual electrodes of the laser devices are respectively connected, driver terminals to which the driver IC is connected, and test terminals which are respectively connected to the common electrode terminal and the individual electrode terminals, and to which an external power supply is to be connected when performing burn-in of the laser devices, wherein the number of the laser devices and the number of the test terminals are each larger than the number of the driver terminals.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: February 9, 2016
    Assignee: CITIZEN HOLDINGS CO., LTD.
    Inventors: Masafumi Ide, Kaoru Yoda, Shinpei Fukaya
  • Patent number: 9230829
    Abstract: The invention relates to a method for encapsulating an electronic arrangement against permeants, wherein an electronic arrangement is made available on a substrate, wherein, in a vacuum, that area of the substrate which embraces that region of the electronic arrangement which is to be encapsulated, preferably said area and that region of the electronic arrangement which is to be encapsulated, is brought into contact with a sheet material comprising at least one adhesive compound and a composite is produced therefrom. The invention also relates to an apparatus for implementing the method and to an encapsulated electronic arrangement produced thereby.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: January 5, 2016
    Assignee: TESA SE
    Inventors: Klaus Telgenbüscher, Judith Grünauer, Jan Ellinger
  • Patent number: 9230938
    Abstract: Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes). By this test, conduction between the bumps (electrodes) on the back surface side is checked.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: January 5, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Akio Hasebe, Naohiro Makihira, Bunji Yasumura, Mitsuyuki Kubo, Fumikazu Takei, Yoshinori Deguchi
  • Patent number: 9190371
    Abstract: In general, embodiments of the present invention provide a chip package with multiple TSV configurations. Specifically, the chip package typically includes a backend layer (e.g., metal interconnect layer); a substrate coupled to the backend layer; a set (at least one) of backend side interconnects extending (e.g., angularly) from a side surface of the backend layer to a bottom surface of the backend layer; a set of optional vertical TSVs extending from a top surface of the backend layer through the substrate; and a network organizer positioned in the substrate organizer for handling communications made using the set of backend side interconnects and the set of vertical TSVs. A set of connections (e.g., controlled collapse chip connections (C4s) can be positioned adjacent to any of the vias to provide connectively to other hardware elements such as additional chip packages, buses, etc.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: November 17, 2015
    Inventor: Moon J. Kim
  • Patent number: 9147617
    Abstract: In a resin coating which is used in the manufacture of an LED package which is made by covering an LED element with resin that includes fluorescent substance, a light-passing member (43) on which the resin (8) is test coated for light emission characteristic measurement is carried on a light-passing member carrying unit (41), a deviation between a measurement result obtained after the light emission characteristic of the light that the resin (8) emits, when an light source unit (45), which is placed above, emits excitation light which excites the fluorescent substance, and irradiates the excitation light from above to the resin (8) which is coated on the light-passing member (43), is measured and the light emission characteristic prescribed beforehand is obtained, and an appropriate resin coating quantity with which the resin should be coated on the LED element is derived for practical production based on the deviation.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: September 29, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Masaru Nonomura
  • Patent number: 9129840
    Abstract: When a conductive post is bonded to a bonding target member such as a semiconductor chip or an insulating substrate with conductive patterns by using metal nanoparticles, a strong bonding layer can be obtained by forming a bottom surface of the distal end of the conductive post in a concave shape.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: September 8, 2015
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Norihiro Nashida
  • Patent number: 9093281
    Abstract: A luminescence device used in a backlight unit for lighting or displaying may include a substrate having a first electrode and a second electrode, and an LED chip disposed on the first electrode. A dam is disposed on the substrate. The dam is disposed spaced from the LED chip, and the substrate comprises a direct copper bonding (DCB) substrate including a first copper layer and a second copper layer. The first electrode and the second electrode include respectively a metal film which fills a void of the surfaces thereof.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: July 28, 2015
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Sampei Tomohiro
  • Patent number: 9082881
    Abstract: Semiconductor On Polymer (SOP) is a flexible ultra-thin substrate that can be used as the starting material for CMOS, MEMS or Complex Interconnects such as an interposer. The described process results in a flexible SOP device with open bond pads. After deposition of a liquid polymer onto a semiconductor substrate, the polymer is converted to a solid, creating a new substrate that is temporarily bonded to a carrier wafer. The semiconductor layer is then etched to be ultra-thin and highly uniform, specifically, a single crystalline silicon layer. Following fabrication of devices and interconnects on the polymer substrate, the ultra thin wafer is released from the carrier wafer in substrate form to be used whole or tiled for subsequent assembly. Among other advantages, the flexible format of the SOP substrate enables low resistance 3-D interconnects, and provides for a significant increase in performance due to a reduction in parasitic capacitance.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: July 14, 2015
    Assignee: American Semiconductor, Inc.
    Inventors: Douglas R. Hackler, Sr., Richard L. Chaney
  • Patent number: 9064717
    Abstract: A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: June 23, 2015
    Assignee: International Business Machines Corporation
    Inventors: Sampath Purushothaman, Mary E. Rothwell, Ghavam Ghavami Shahidi, Roy Rongqing Yu
  • Patent number: 9065033
    Abstract: The present application relates to a light emitting device package. The light emitting device package includes a package substrate in which a via hole is formed. An electrode layer extends to both surfaces of the package substrate after passing through the via hole. A light emitting device is arranged on the package substrate and is connected to the electrode layer. A fluorescence film includes a first part that fills at least a part of an internal space of the via hole and a second part that covers at least a part of the light emitting device.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: June 23, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-hyun Lee, Dong-hyuck Kam, Gam-han Yong, Jin-gi Hong, Seong-deok Hwang
  • Publication number: 20150145440
    Abstract: An organic EL panel with less variation in an emission luminance thereof and a method for manufacturing a light-emitting device using the same are provided. The organic EL panel of the present invention includes: a substrate; a light-emitting section of the organic EL panel provided on the substrate; a current supply terminal provided on the substrate for supplying a current to the light-emitting section; and a current density adjusting section electrically connected to the current supply terminal in parallel to the light-emitting section and provided on the substrate. A current density of the light-emitting section is adjusted by processing of the current density adjusting section. Moreover, in the method for manufacturing a light-emitting device according to the present invention, after a light-emitting characteristic is adjusted by processing a post-processing region of the above-described organic EL panel, a light-emitting device including the processed organic EL panel is manufactured.
    Type: Application
    Filed: May 22, 2012
    Publication date: May 28, 2015
    Applicant: PIONEER CORPORATION
    Inventor: Shinichi Ishizuka
  • Patent number: 9040316
    Abstract: A semiconductor device and method of adaptive patterning for panelized packaging with dynamic via clipping is described. A panel comprising an encapsulating material disposed around a plurality of semiconductor die can be formed. An actual position for each of the plurality of semiconductor die within the panel can be measured. A conductive redistribution layer (RDL) comprising first capture pads aligned with the actual positions of each of the plurality of semiconductor die can be formed. A plurality of second capture pads at least partially disposed over the first capture pads and aligned with a package outline for each of the plurality of semiconductor packages can be formed. A nominal footprint of a plurality of conductive vias can be adjusted to account for a misalignment between each semiconductor die and its corresponding package outline.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: May 26, 2015
    Assignee: Deca Technologies Inc.
    Inventors: Christopher M. Scanlan, Craig Bishop
  • Patent number: 9041219
    Abstract: A multi-chip package is provided. The multi-chip package includes a plurality of chips including at least one bad chip and at least one good chip that are stacked and a plurality of through electrodes each penetrating the chips. A logic circuit included in the at least one bad chip is isolated from each of the plurality of through electrodes.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: May 26, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byung-Hyun Lee, Hoon Lee
  • Patent number: 9040350
    Abstract: A method includes placing a plurality of bottom units onto a jig, wherein the plurality of bottom units is not sawed apart and forms an integrated component. Each of the plurality of bottom units includes a package substrate and a die bonded to the package substrate. A plurality of upper component stacks is placed onto the plurality of bottom units, wherein solder balls are located between the plurality of upper component and the plurality of bottom units. A reflow is performed to join the plurality of upper component stacks with respective ones of the plurality of bottom units through the solder balls.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Juin Liu, Chita Chuang, Ching-Wen Hsiao, Chen-Shien Chen, Chen-Cheng Kuo, Chih-Hua Chen
  • Publication number: 20150137358
    Abstract: A semiconductor device according to the present invention includes: a combination object; and a chip having a front surface opposed to a front surface of the combination object. The chip includes: a multi-level wiring structure provided in the front surface of the chip; a connection electrode provided in the multi-level wiring structure and electrically connected to the combination object; an alignment mark set provided in the multi-level wiring structure and electrically isolated from the connection electrode; and an electrically conductive film provided at a higher level than the alignment mark set in association with the multi-level wiring structure to cover the alignment mark set and electrically isolated from the connection electrode.
    Type: Application
    Filed: November 14, 2014
    Publication date: May 21, 2015
    Applicant: ROHM CO., LTD.
    Inventor: Azusa YANAGISAWA
  • Patent number: RE45931
    Abstract: For the manufacturing of semiconductor devices, in which multiple semiconductor chips which are mounted on a wiring substrate are processed for block molding and thereafter the wiring substrate is diced into individual resin-molded semiconductor devices, disclosed herein is a technique for easily determining the position of each resin-molded semiconductor device in its former state on the wiring substrate even after the dicing process. The processing steps include implementing the block molding with resin for multiple semiconductor chips mounted on a wiring substrate and thereafter dicing the wiring substrate into individual resin-molded semiconductor devices, with the substrate dicing step being preceded by a step of appending an address information pattern to each of the resin-molded semiconductor devices.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: March 15, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tsutomu Wada, Masachika Masuda