Packaging (e.g., With Mounting, Encapsulating, Etc.) Or Treatment Of Packaged Semiconductor Patents (Class 438/15)
  • Patent number: 11887900
    Abstract: A semiconductor package includes a base including a first bonding structure; and a first semiconductor chip, including a second bonding structure, the second bonding structure being coupled to the first bonding structure of the base, wherein the first bonding structure includes: a test pad; a first pad being electrically connected to the test pad; and a first insulating layer, wherein the second bonding structure includes: a second pad being electrically connected to the first pad; and a second insulating layer being in contact with the first insulating layer, and wherein at least a portion of the test pad is in contact with the second insulating layer.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: January 30, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyuek Jae Lee, Tae Hun Kim, Ji Hwan Hwang, Ji Hoon Kim, Ji Seok Hong
  • Patent number: 11754640
    Abstract: A device including a first voltage domain and a second voltage domain is provided, the voltage domains being separated by an isolation barrier. In addition, the device includes a scratch detection circuit including a first and a second electrode at a distance of less than 2 ?m.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: September 12, 2023
    Assignee: Infineon Technologies AG
    Inventors: Matthias Stecher, Hermann Gruber, Thorsten Hinderer
  • Patent number: 11756811
    Abstract: A device, mechanism, and methodology for regular and consistent cleaning of the vacuum aperture, nozzle, and contacting surfaces of a pick-and-place apparatus and the pick-up tools of automated or manual semiconductor device and die handling machines are disclosed. The cleaning material may include a cleaning pad layer with one or more intermediate layers that have predetermined characteristics, regular geometrical features, and/or an irregular surface morphology.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: September 12, 2023
    Assignee: International Test Solutions, LLC
    Inventors: Alan E. Humphrey, Bret A. Humphrey, Jerry J. Broz, Wayne C. Smith
  • Patent number: 11735571
    Abstract: A semiconductor package includes: a first wiring pattern; a dielectric layer that covers the first wiring pattern; a second wiring pattern on the dielectric layer, wherein the second wiring pattern includes a line part that extends in a first direction and a via part that connects the line part to the first wiring pattern; a pad pattern electrically connected to the second wiring pattern, wherein the pad pattern includes a connection part and an extension part, wherein the connection part covers a first surface of the line part of the second wiring pattern, and the extension part has a top surface at a level lower than a level of the top surface of the line part of the second wiring pattern; and a seed pattern between the extension part and the dielectric layer.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: August 22, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Yonghwan Kwon
  • Patent number: 11712747
    Abstract: A wafer processing method for processing a wafer formed on a front surface thereof with a plurality of devices having projection-shaped electrodes, the devices being partitioned by streets, includes a cutting step of holding a back surface of the wafer by a holding surface of a chuck table and cutting head portions of the projection-shaped electrodes by a cutting tool slewed in parallel to the holding surface, to make uniform the electrodes in height and expose metallic surfaces; a thermocompression bonding sheet laying step of laying a thermocompression bonding sheet on the front surface of the wafer; a thermocompression bonding step of heating and pressing the thermocompression bonding sheet to perform thermocompression bonding; and a peeling step of peeling off the thermocompression bonding sheet from the wafer, before dividing the wafer into individual device chips and bonding the electrodes to a circuit board.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: August 1, 2023
    Assignee: DISCO CORPORATION
    Inventor: Ye Chen
  • Patent number: 11710685
    Abstract: The present application provides a semiconductor module and a power conversion device wherein wiring inductance is reduced. The semiconductor module is characterized by including a semiconductor element, a first terminal on which the semiconductor element is mounted, a second terminal disposed in a periphery of the semiconductor element and having a multiple of wiring portions, and a multiple of connection lines extending in multiple directions from an upper face of the semiconductor element and connected to each of the multiple of wiring portions of the second terminal, wherein a free region is provided among the multiple of wiring portions, and the multiple of connection lines and the multiple of wiring portions forming current paths with each of the multiple of connection lines are of the same potential.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: July 25, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Dai Yoshii, Hantaro Ozawa
  • Patent number: 11711887
    Abstract: An object of the present disclosure is to be able to further reduce the size of a substrate structure including a plurality of elements. The substrate structure includes: a base substrate that includes a first conductive plate and a second conductive plate; a first element connected to the first conductive plate and the second conductive plate; and a second element connected to the first conductive plate and the second conductive plate. The first conductive plate and the second conductive plate are disposed on the same plane on the base substrate in a state of being electrically insulated from each other, the first element is mounted on a first main surface of the base substrate, and the second element is mounted on a second main surface that is on the opposite side to the first main surface relative to the base substrate.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: July 25, 2023
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Shungo Hiratani, Shinsuke Okumi, Arinobu Nakamura
  • Patent number: 11675220
    Abstract: Provided in a method of fabricating an optical element array including providing a silicon substrate, providing a first element layer on the silicon substrate, the first element layer including a plurality of passive optical elements, providing a plurality of semiconductor blocks on a compound semiconductor wafer, providing semiconductor dies by dicing the compound semiconductor wafer by the plurality of semiconductor blocks, and providing a second element layer by providing the semiconductor dies on the first element layer, each of the plurality of semiconductor blocks contacting at least one corresponding passive optical element from among the plurality of passive optical elements.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: June 13, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dongsik Shim, Changgyun Shin, Changbum Lee
  • Patent number: 11652008
    Abstract: A method includes, receiving a layout design of at least part of an electronic module, the design specifying at least (i) an electronic device coupled to at least a substrate, and (ii) an electrical trace that is connected to the electronic device and has a designed route. A digital input, which represents at least part of an actual electronic module that was manufactured in accordance with the layout design but without at least a portion of the electrical trace, is received. An error in coupling the electronic device to the substrate, relative to the layout design, is estimated based on the digital input. An actual route that corrects the estimated error, is calculated for at least the portion of the electrical trace. At least the portion of the electrical trace is formed on the substrate of the actual electronic module, along the actual route instead of the designed route.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: May 16, 2023
    Assignee: Orbotech Ltd.
    Inventors: Ram Oron, Michael Burdinov, Elad Goshen, Ronald F. Kaminsky, Gonen Raveh
  • Patent number: 11646294
    Abstract: In a method of manufacturing a semiconductor package, information with respect to a downward warpage of a reference package substrate, which may be bent with respect to a long axis and/or a short axis of the reference package substrate in applying heat to the reference package substrate to which a plurality of semiconductor chips may be attached using a die attach film (DAF), may be obtained. A package substrate, which may include a first surface to which the semiconductor chips may be attached using the DAF and a second surface opposite to the first surface, may be rotated with respect to the long axis or the short axis at an angle selected based on the information. The heat may be applied to the package substrate to cure the DAF and correct a warpage of the package substrate. Thus, warpage of the package substrate may be corrected for.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: May 9, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ungkeol Kim
  • Patent number: 11637079
    Abstract: A semiconductor package includes a supporting wiring structure including a first redistribution dielectric layer and a first redistribution conductive structure; a frame on the supporting wiring structure, having a mounting space and a through hole, and including a conductive material; a semiconductor chip in the mounting space and electrically connected to the first redistribution conductive structure; a cover wiring structure on the frame and the semiconductor chip and including a second redistribution dielectric layer and a second redistribution conductive structure; an antenna structure on the cover wiring structure; a connection structure extending in the through hole and electrically connecting the first redistribution conductive structure to the second redistribution conductive structure; and a dielectric filling member between the connection structure in the through hole and the frame and surrounding the semiconductor chip, the frame, and the connection structure.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: April 25, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yongkoon Lee, Jingu Kim, Sangkyu Lee, Seokkyu Choi
  • Patent number: 11626377
    Abstract: A semiconductor device includes a semiconductor substrate including a chip region and an edge region around the chip region, a lower insulating layer on the semiconductor substrate, a chip pad on the lower insulating layer on the chip region, an upper insulating layer provided on the lower insulating layer to cover the chip pad, the upper and different insulating layers including different materials, and a redistribution chip pad on the chip region and connected to the chip pad. The upper insulating layer includes a first portion on the chip region having a first thickness, a second portion on the edge region having a second thickness, and a third portion on the edge region, the third portion extending from the second portion, spaced from the first portion, and having a decreasing thickness away from the second portion. The second thickness is smaller than the first thickness.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: April 11, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Hoon Han, Dong-Wan Kim, Dongho Kim, Jaewon Seo
  • Patent number: 11581707
    Abstract: A method of producing a laser diode bar includes producing a plurality of emitters arranged side by side, emitters each including a semiconductor layer sequence having an active layer that generates laser radiation, a p-contact on a first main surface of the laser diode bar and an n-contact on a second main surface of the laser diode bar opposite the first main surface, testing at least one optical and/or electrical property of the emitters, wherein emitters in which the optical and/or electrical property lies within a predetermined setpoint range are assigned to a group of first emitters, and emitters in which the at least one optical and/or electrical property lies outside the predetermined setpoint range are assigned to a group of second emitters, and electrically contacting first emitters, wherein second emitters are not electrically contacted so that they are not supplied with current during operation of the laser diode bar.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: February 14, 2023
    Assignee: OSRAM OLED GmbH
    Inventors: Clemens Vierheilig, Andreas Löffler, Sven Gerhard
  • Patent number: 11545463
    Abstract: A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: January 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sheng-Yao Yang, Ling-Wei Li, Yu-Jui Wu, Cheng-Lin Huang, Chien-Chen Li, Lieh-Chuan Chen, Che-Jung Chu, Kuo-Chio Liu
  • Patent number: 11540384
    Abstract: An apparatus comprises a transceiver (Tx/Rx) printed circuit board (PCB) with a top surface and a bottom surface and a power supply PCB. The Tx/Rx PCB includes two transmitter devices, each comprising a number N of channels. A first transmitter device is arranged on the bottom surface and a second transmitter device is arranged on the top surface over the first transmitter device. One or more pins of the second transmitter device are shorted with one or more pins of the first transmitter device with the same function. An analog front end (AFE) device comprising N input channels is arranged on the top surface of the Tx/Rx PCB, and a digital signal processor is coupled to the AFE device. The power supply PCB comprises a power supply module configured to provide a plurality of supply voltages to the Tx/Rx PCB and the power supply PCB.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: December 27, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shabbir Amjhera Wala, Xiaochen Xu, Dijeesh K, Abhishek Vishwa, Shriram Devi, Aatish Chandak, Sanjay Dixit, Elisa Maddalena Granata, Jun Shen, Sandeep Oswal
  • Patent number: 11538790
    Abstract: A semiconductor package includes an interposer, a number of a first integrated circuit (IC) dies, one or more second IC dies, and one or more dummy dies. The first IC dies, the second IC dies and the dummy dies are implemented on the interposer. The dummy dies are configured to enable routing of pins of the first IC dies to selected circuits of the second IC dies while conforming to predefined routing rules.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: December 27, 2022
    Assignee: BROADCOM INTERNATIONAL PTE. LTD.
    Inventors: Mohamed Anwar Ali, Thinh Quang Tran, Tauman T. Lau
  • Patent number: 11348844
    Abstract: A semiconductor wafer includes a silicon carbide wafer and an epitaxial layer, which is disposed at a surface of the silicon carbide wafer and made of silicon carbide. The semiconductor wafer satisfies a condition that a waviness value is equal to or smaller than 1 micrometer. The waviness value is a sum of an absolute value of a value ? and an absolute value of a value ?. A highest height among respective heights of a plurality of points with reference to a surface reference plane within a light exposure area is denoted as the value ?. A lowest height among the respective heights of the points at the epitaxial layer with reference to the surface reference plane within the light exposure area is denoted as the value ?.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: May 31, 2022
    Assignee: DENSO CORPORATION
    Inventors: Shinya Takei, Shuhei Mitani, Haruhito Ichikawa, Ippei Takahashi, Yukihiro Wakasugi
  • Patent number: 11302672
    Abstract: The disclosure concerns an electronic device and methods of making an electronic device. The electronic device includes a circuit that is at least partially formed in an active region of a substrate. An electronic package is stacked on the substrate. A via extends through the circuit from the active region of the substrate to a surface of the substrate that is opposite the active region. At least one contacting element connects the via to the electronic package.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: April 12, 2022
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventor: Didier Campos
  • Patent number: 11276614
    Abstract: A pick and place LED testing apparatus, comprising: a test station operative in use to power a group of LEDs; a bondhead operative in use to pick said group of LEDs from a source wafer and place said group of LEDs on said test station for testing; and an optical sensor operative in use to measure an optical characteristic of said group of LEDs when tested, wherein at least a portion of said bondhead is translucent to provide an optical path from said group of LEDs to said optical sensor.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: March 15, 2022
    Assignee: ASM TECHNOLOGY SINGAPORE PTE LTD
    Inventors: Shun Yan Lee, Sai Kit Wong, Chi Wah Yuen, Ka Yee Mak, Gary Peter Widdowson
  • Patent number: 11222786
    Abstract: In a method of manufacture, a displacement sensor is provided over a conditioner disk. The conditioner disk is rotated to perform a conditioning process on a polishing surface of a polishing pad. A displacement of the rotating conditioner disk is detected using the displacement sensor during the conditioning process. A height of the conditioner disk is calculated from the detected displacement. An end point of the conditioning process is determined on the polishing surface based on the calculated height.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: January 11, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin Shin, Woo-Mok Son, Nam-Hoon Lee, Dong-Eog Kim, Seung-Hun Oh, Eun-Seok Lee, Young-Seok Jang
  • Patent number: 11189988
    Abstract: A device includes a substrate, a vertical cavity surface emitting laser (VCSEL) array on top of the substrate, a via through the substrate and the VCSEL array, a first electrode extended from a top of the VCSEL array to a bottom of the substrate, through the via, the first electrode electrically connected to the VCSEL array, a second electrode on the bottom of the substrate, the second electrode electrically connected to the VCSEL array, and an isolator in the via providing electrical isolation between the first electrode and the second electrode.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: November 30, 2021
    Assignee: Lumentum Operations LLC
    Inventor: Matthew Glenn Peters
  • Patent number: 11182801
    Abstract: A computer-implemented method of authenticating a product comprises receiving, from a scanner terminal, a query message including a hapto-signature of the product to be authenticated, the hapto-signature including at least one haptic characteristic of the product as scanned by a touch-sensitive surface of the scanner terminal. The method comprises comparing the received hapto-signature against a hapto-signature database comprising a plurality of reference hapto-signatures, each reference hapto-signature having an associated product, to determine whether or not the received hapto-signature matches at least one of the reference hapto-signatures, wherein a determination that the received hapto-signature matches at least one of the reference hapto-signatures indicates that the product is authentic. The method comprises generating and sending a response message indicative of whether or not the received hapto-signature matches at least one of the reference hapto-signature.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: November 23, 2021
    Assignee: International Business Machines Corporation
    Inventor: Geoffrey H Siwo
  • Patent number: 11172580
    Abstract: The proposed masking dam protects ball grid array integrated circuit components from conformal coating overflow, preventing joint breakage and thermal mismatch. The masking dam includes a frame with an integrated seal, a cover, and a fastening mechanism. The frame is sealed to a circuit board surround a component, the cover is attached to the frame, and the masking dam is secured to protect the component.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: November 9, 2021
    Assignee: Rosemount Aerospace Inc.
    Inventor: James R. Gaertner, II
  • Patent number: 11152245
    Abstract: A micro LED transfer device is provided. The micro LED transfer device includes a transfer part configured to arrange a first substrate wherein a plurality of LEDs are disposed on a lower surface relative to an upper surface of a second substrate; a memory storing characteristic information of each of the plurality of LEDs; a laser light source configured to irradiate laser light; a mask comprising a plurality of shutters configured to selectively open and close a plurality of openings of the mask, the mask being interposed between the first substrate and the laser light source; and a processor configured to identify an LED from among the plurality of LEDs to be arranged on the second substrate based on the stored characteristic information, and control the mask such that a shutter from among the plurality of shutters that corresponds to the LED is opened.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: October 19, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangmoo Park, Doyoung Kwag, Eunhye Kim, Minsub Oh, Yoonsuk Lee
  • Patent number: 11094572
    Abstract: There is provided an apparatus including a substrate holder to hold substrates including a product substrate and a dummy substrate, a transfer mechanism that loads the substrates into the substrate holder, a storage part to store a device parameter including at least the number of substrates that can be loaded on the substrate holder and the number of product substrates to be loaded on the substrate holder, and a controller to: (1) create substrate transfer data, which includes information indicating an order for transferring the substrates, transfer source information, and transfer destination information, according to the device parameter, (2) read the created substrate transfer data, (3) by transferring the substrates to the transfer mechanism based on the read substrate transfer data, transfer the dummy substrate to a substrate holding region except for a heat equalization region, and transfer the product substrate to the heat equalization region on the substrate holder.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: August 17, 2021
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Osamu Morita, Yuji Yamaoka, Shuichi Kubo, Toshiro Koshimaki, Hiroyuki Kitamoto
  • Patent number: 11056365
    Abstract: A method for fault detection in a fabrication tool is provided. The method includes processing a semiconductor wafer in a fabrication tool according to a plurality of process events of a process run. The method further includes measuring humidity in the fabrication tool in at least one of the process events. The method also includes comparing the humidity measured in one of the process events with an expected humidity associated with the process event. In addition, the method includes based on the comparison, indicating an alarm condition when a difference between the measured humidity and the expected humidity exceeds a range of acceptable values associated with the process event.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: July 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hom-Chung Lin, Jih-Churng Twu, Chin-Yun Chen, Tai-Hsiang Lin, Yu-Chi Tsai
  • Patent number: 11016399
    Abstract: A method of predicting the dominant failure mode and/or the failure rate of a plurality of features formed on a substrate, and an associated inspection apparatus. The method may include determining a placement metric for each feature, the placement metric including a measure of whether the feature is in an expected position, and comparing a distribution of the placement metric to a reference (e.g., Gaussian) distribution. The placement metric may include a boundary metric for a plurality of boundary points on a boundary defining each feature, the boundary metric including a measure of whether a boundary point is in an expected position. The dominant failure mode and/or the failure rate of the plurality of features is predicted from the comparison.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: May 25, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Marleen Kooiman, Sander Frederik Wuister
  • Patent number: 11018113
    Abstract: A memory module includes a first redistribution structure, a second redistribution structure, first semiconductor dies, second semiconductor dies, an encapsulant, through insulator vias and thermally conductive material. Second redistribution structure is stacked over first redistribution structure. First semiconductor dies are sandwiched between first redistribution structure and second redistribution structure and disposed side by side. Second semiconductor dies are disposed on the second redistribution structure. The encapsulant laterally wraps the second semiconductor dies. The through insulator vias are disposed among the first semiconductor dies, extending from the first redistribution structure to the second redistribution structure. The through insulator vias are electrically connected to the first redistribution structure and the second redistribution structure.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lipu Kris Chuang, Chung-Hao Tsai, Hsin-Yu Pan, Yi-Che Chiang, Chien-Chang Lin
  • Patent number: 11004746
    Abstract: The present disclosure provides a dehydrating chemical for dehydrating a semiconductor substrate under an ambient temperature, including a first chemical having a melting point below the ambient temperature, and a second chemical having a melting point greater than the melting point of the first chemical, wherein the dehydrating chemical has a melting point less than the ambient temperature by predetermined ?T0 degrees, and at least one of the first chemical and the second chemical has a saturated vapor pressure greater than a predetermined pressure PSV under 1 atm.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: May 11, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chung-Chieh Lee, Chi-Ming Yang, Chyi Shyuan Chern
  • Patent number: 10964655
    Abstract: A method of forming a semiconductor device includes forming a plurality of metal pads over a semiconductor substrate of a wafer, forming a passivation layer covering the plurality of metal pads, patterning the passivation layer to reveal the plurality of metal pads, forming a first polymer layer over the passivation layer, forming a plurality of redistribution lines extending into the first polymer layer and the passivation layer to connect to the plurality of metal pads, forming a second polymer layer over the first polymer layer, and patterning the second polymer layer to reveal the plurality of redistribution lines. The first polymer layer is further revealed through openings in remaining portions of the second polymer layer.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ming Chen, Ching-Tien Su
  • Patent number: 10896902
    Abstract: Systems and methods for efficient transfer of elements are disclosed. A film which supports a plurality of diced integrated device dies can be provided. The plurality of diced integrated device dies can be disposed adjacent one another along a surface of the film. The film can be positioned adjacent the support structure such that the surface of the film faces a support surface of the support structure. The film can be selectively positioned laterally relative to the support structure such that a selected first die is aligned with a first location of the support structure. A force can be applied in a direction nonparallel to the surface of the film to cause the selected first die to be directly transferred from the film to the support structure.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: January 19, 2021
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Cyprian Emeka Uzoh, Paul M. Enquist, Gaius Gillman Fountain, Jr.
  • Patent number: 10886004
    Abstract: A computer-implemented method for sorting non-volatile random access memories (NVRAMS) includes testing a failure metric for each of a plurality of NVRAMS over a plurality of testing sessions to capture failure metric data that corresponds to the plurality of NVRAMS. The method also includes determining a trend in the failure metric as a function of testing cycles for each of the plurality of NVRAMS from the failure metric data, and separating the plurality of NVRAMS into groups based on the trend in the failure metric as a function of testing cycles. A corresponding computer program product and computer system are also disclosed herein.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey W. Christensen, Phillip E. Christensen, Daniel E. Moore, Antoine G. Sater, Jung H. Yoon
  • Patent number: 10825702
    Abstract: The present invention relates to a device and method for self-assembling semiconductor light-emitting diodes. Particularly, a method for manufacturing a display device according to the present invention includes: feeding a substrate to an assembly site and putting semiconductor light-emitting diodes having a magnetic material into a fluid chamber; applying a magnetic force to the semiconductor light-emitting diodes so that the semiconductor light-emitting diodes move in one direction within the fluid chamber; and guiding the semiconductor light-emitting diodes to preset positions on the substrate by applying an electric field, so that the semiconductor light-emitting diodes are mounted at the preset positions while in the process of being moved.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: November 3, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Bongchu Shim, Dohee Kim, Changseo Park, Hyunwoo Cho
  • Patent number: 10811338
    Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Horng Chang, Jie-Cheng Deng, Tin-Hao Kuo, Ying-Yu Chen
  • Patent number: 10804433
    Abstract: An optoelectronic device and a method are disclosed.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: October 13, 2020
    Assignee: OSRAM OLED GMBH
    Inventors: Alexander F. Pfeuffer, Sophia Huppmann, Andrea Winnerl, Jens MĂĽller
  • Patent number: 10763415
    Abstract: Disclosed is a method for manufacturing a semiconductor light emitting device, the method including: providing a mask having a plurality of openings on a base; placing semiconductor light emitting chips on exposed portions of the base through the openings, respectively, by a device carrier which recognizes a shape of the mask and calibrates position for a semiconductor light emitting chip to be seated; and supplying an encapsulant to each of the openings, with the mask serving as a dam.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: September 1, 2020
    Assignee: SEMICON LIGHT CO., LTD.
    Inventors: Soo Kun Jeon, Seung Ho Baek, Da Rae Lee, Bong Hwan Kim, Dong So Jung
  • Patent number: 10748824
    Abstract: Representative implementations of devices and techniques provide a temporary access point (e.g., for testing, programming, etc.) for a targeted interconnect located among multiple finely spaced interconnects on a surface of a microelectronic component. One or more sacrificial layers are disposed on the surface of the microelectronic component, overlaying the multiple interconnects. An insulating layer is disposed between a conductive layer and the surface, and includes a conductive via through the insulating layer that electrically couples the conductive layer to the target interconnect. The sacrificial layers are configured to be removed after the target interconnect has been accessed, without damaging the surface of the microelectronic component.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: August 18, 2020
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Javier A. Delacruz, Paul M. Enquist, Gaius Gillman Fountain, Jr., Ilyas Mohammed
  • Patent number: 10741415
    Abstract: A method of making a package is disclosed. The method may include forming bond pads on a first surface of a substrate, forming leads in the substrate by etching recesses in a second surface of the substrate, the second surface being opposite the first surface, and plating at least a portion of a top surface of the leads with a layer of finish plating. The method may also include thermosonically bonding the leads to a die by thermosonically bonding the finish plating to the die and encapsulating the die and the leads in an encapsulant.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: August 11, 2020
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Mauro Mazzola, Battista Vitali, Matteo De Santa
  • Patent number: 10727112
    Abstract: A method for rewiring of semiconductor devices is provided, in which deviations of electrical connection terminals (211, 212, 221, 222, 231, 232) on a carrier (100) are calculated and corrected by forming rewiring structures on the electrical connection terminals by mask-free photolithography. A wiring layer and/or solder balls (700) is/are then formed on the rewiring structures by processing the carrier (100) in a monolithic manner using mask-based photolithography. In this way, the combined use of mask-free photolithography and mask-based photolithography allows for higher efficiency and a shorter process cycle, compared to only using mask-free photolithography.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: July 28, 2020
    Assignee: SHANGHAI MICRO ELECTRONICS EQUIPMENT (GROUP) CO., LTD.
    Inventors: Yonghui Chen, Shiyi Tang
  • Patent number: 10699977
    Abstract: A method of detecting delamination in an integrated circuit package structure, the method includes forming a plurality of through vias over a carrier substrate; placing a device die over the carrier substrate and between the through vias, wherein the device die comprises a metal pillar; forming a molding material surrounding the device die and the through vias; forming a testing metal line extending along a top surface of the molding material and past an interface between the device die and the molding material; applying a current to the testing metal line; detecting an electrical signal of the testing metal line during the applying the current to the testing metal line; and determining, based on the detected electrical signal of the testing metal line, whether a delamination occurs between the device die and the molding material.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yang-Che Chen, Tsung-Te Chou, Chen-Hua Lin, Huang-Wen Tseng, Chwen-Ming Liu
  • Patent number: 10657639
    Abstract: Systems and methods for identifying defective individual packaged modules are presented. A Printed Circuit Board (PCB) having a set of individual module substrates can be received. Further, capturing an image of the PCB and loading a PCB recipe associated with the PCB can be performed. The image of the PCB can be captured by an image capture module that can include one or more cameras. For each individual module substrate, a portion of the image corresponding to the individual module substrate can be compared to the PCB recipe. In addition, it can be determined based on the comparison whether the individual module substrate matches the PCB recipe within a degree of tolerance. In response to determining that the individual module substrate does not match the PCB recipe within the degree of tolerance, a location of the individual module substrate within a map of the PCB can be stored.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: May 19, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventors: Carlos Fabian Nava, Viviano Almonte
  • Patent number: 10573601
    Abstract: A semiconductor device may include a semiconductor die disposed within an encapsulant, the semiconductor die being misaligned with a package edge formed by the encapsulant. A total radial shift of the semiconductor die may account for the misalignment between semiconductor die and the package edge. A build-up interconnect structure may comprise two or more layers formed over the semiconductor die and the encapsulant, the two or more layers comprising at least one redistribution layer (RDL). The total radial shift may be distributed over the two or more layers of the build-up interconnect structure to form a unit specific pattern for each of the two or more layers. An average misalignment of the semiconductor die and the package edge may be greater than the average misalignment of the at least one unit specific pattern with respect to the package edge.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: February 25, 2020
    Assignee: Deca Technologies Inc.
    Inventors: Christopher M. Scanlan, Craig Bishop
  • Patent number: 10529632
    Abstract: A method, in some embodiments, comprises: providing a component having first and second electrical nodes; determining that the component lacks multiple, functional electrical couplings between said first and second nodes; damaging at least part of the component as a result of said determination; and determining, as a result of said damage, that the component is defective.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: January 7, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Darrell D. Truhitte, James P. Letterman, Jr.
  • Patent number: 10473714
    Abstract: A method for automated alignment between a plurality of electronic components and at least one testing device for receiving the electronic components for testing which includes defining a fiducial marker and positioning a moveable imaging device relative to a stationary imaging device, such that the fiducial marker is within a field of view of the moveable imaging device and within a field of view of the stationary imaging device. The moveable imaging device determines, with respect to each of the at least one testing device, a first offset between the testing device and the fidicual marker. The stationary imaging device determines, with respect to each electronic component, a second offset between the electronic component and the fidicual marker. Alignment is effected between each electronic component and the testing device in accordance with the first and second offsets.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: November 12, 2019
    Assignee: ASM TECHNOLOGY SINGAPORE PTE LTD
    Inventors: Chi Wah Cheng, Chi Hung Leung, Yu Sze Cheung, Kai Fung Lau
  • Patent number: 10459007
    Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: October 29, 2019
    Assignee: VIA Technologies, Inc.
    Inventors: Chen-Yueh Kung, Wen-Yuan Chang, Wei-Cheng Chen
  • Patent number: 10412869
    Abstract: A component mounting device performs measurement of a position of a reference section of a head and measurement of calibration data of the head, and the calibration data of the head and the position of the reference section are stored in association. The component mounting device controls operation of the head holding body in which the head is held based on the calibration data of the head and the position of the reference section. In a case where it is not necessary to generate the calibration data of the predetermined head, the component mounting device measures the position of the reference section, and controls operation of the head holding body in which the head is held based on the measured position of the reference section, the position of the reference section which is stored, and the calibration data of the head.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: September 10, 2019
    Assignee: FUJI CORPORATION
    Inventor: Ryohei Kamio
  • Patent number: 10199087
    Abstract: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: February 5, 2019
    Assignee: III HOLDINGS 2, LLC
    Inventor: Michael C. Stephens, Jr.
  • Patent number: 10170381
    Abstract: A semiconductor test system has a film frame including a tape portion with one or more openings through the tape portion. The opening is disposed in a center region of the tape portion of the film frame. The film frame may have conductive traces formed on or through the tape portion. A thin semiconductor wafer includes a conductive layer formed over a surface of the semiconductor wafer. The semiconductor wafer is mounted over the opening in the tape portion of the film frame. A wafer probe chuck includes a lower surface and raised surface. The film frame is mounted to the wafer probe chuck with the raised surface extending through the opening in the tape portion to contact the conductive layer of the semiconductor wafer. The semiconductor wafer is probe tested through the opening in the tape portion of the film frame.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: January 1, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Heng Chen Lee
  • Patent number: 10157803
    Abstract: A semiconductor device and method can comprise measuring a true position of each of a plurality of semiconductor die within an embedded die panel and determining a total radial shift of each of the plurality of semiconductor die. The total radial shift of each of the plurality of semiconductor die can be distributed to two or more layers for each of the plurality of semiconductor die by assigning a portion of the total radial shift to each of the layers according to a priority list to form a distributed radial shift for each of the layers. A transformation for each of the layers for each of the plurality of semiconductor die can be transformed using the distributed radial shift for each of the layers. A unit specific pattern can be formed over each of the plurality of semiconductor die with the transformation for each of the layers.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: December 18, 2018
    Assignee: DECA Technologies Inc.
    Inventors: Craig Bishop, Christopher M. Scanlan
  • Patent number: 10062679
    Abstract: Apparatuses and methods for forming die stacks are disclosed herein. An example method includes dispensing a temporary adhesive onto a substrate, placing a base die onto the temporary adhesive, curing the temporary adhesive, forming a die stack that includes the base die, activating a release layer disposed on the substrate, wherein the release layer is between the substrate and the temporary adhesive, removing the die stack from the substrate, and removing the temporary adhesive from the die stack.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: August 28, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Michel Koopmans