Abstract: A semiconductor package including a semiconductor chip, a conductive element disposed aside the semiconductor chip, a conductive via disposed on and electrically connected to the conductive element, an insulating encapsulation, and a first circuit structure disposed on the semiconductor chip and the conductive via is provided. A height of the conductive element is less than a height of the semiconductor chip. The insulating encapsulation encapsulates the semiconductor chip, the conductive element, and the conductive via. The conductive via is located between the first circuit structure and the conductive element, and the semiconductor chip is electrically coupled to the conductive via through the first circuit structure.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a top semiconductor die, a bottom semiconductor die, a first encapsulant, a second encapsulant, a third encapsulant, a first redistribution layer and a second redistribution layer. The top semiconductor die is stacked on the bottom semiconductor die. The bottom semiconductor die is laterally encapsulated by the third encapsulant, and the third encapsulant is laterally surrounded by the first encapsulant. The top semiconductor die is laterally encapsulated by the second encapsulant. The first redistribution layer is disposed between the top and bottom semiconductor dies. The bottom semiconductor die, the first encapsulant and the third encapsulant are located between the first and second redistribution layers.

Abstract: A semiconductor package including a semiconductor chip, a conductive element disposed adjacent to the semiconductor chip, an insulating encapsulation covering the semiconductor chip and the conductive element, a redistribution structure disposed on the semiconductor chip and the conductive element, and a first buffer layer disposed between the redistribution structure and the insulating encapsulation is provided. The semiconductor chip is electrically coupled to the conductive element through the redistribution structure. The first buffer layer covers the semiconductor chip and the conductive element. A manufacturing method of a semiconductor package is also provided.

Abstract: A semiconductor package including a semiconductor chip, a conductive element disposed aside the semiconductor chip, a conductive via disposed on and electrically connected to the conductive element, an insulating encapsulation, and a first circuit structure disposed on the semiconductor chip and the conductive via is provided. A height of the conductive element is less than a height of the semiconductor chip. The insulating encapsulation encapsulates the semiconductor chip, the conductive element, and the conductive via. The conductive via is located between the first circuit structure and the conductive element, and the semiconductor chip is electrically coupled to the conductive via through the first circuit structure.

Abstract: A package structure includes a redistribution structure, a bridge die, a plurality of conductive pillars, at least two dies, and an insulating encapsulant. The bridge die provides an electrical connection between the at least two dies. The conductive pillars provide an electrical connection between the at least two dies and the redistribution structure. The insulating encapsulant is disposed on the redistribution structure, encapsulates the bridge die and the conductive pillars, and covers each of the at least two dies. The bridge die of the package structure may be used to route signals between the at least two dies, allowing for a higher density of interconnecting routes between the at least two dies.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a bumpless die including a plurality of conductive pads, a conductive connector disposed aside the bumpless die and electrically coupled to the bumpless die, an insulating encapsulation encapsulating the bumpless die and the conductive connector, a circuit layer electrically connected to the bumpless die and the conductive connector, and a front side redistribution layer disposed on the circuit layer and including a finer line and spacing routing than the circuit layer. The circuit layer includes a conductive pattern disposed on the insulating encapsulation and extending along a thickness direction of the bumpless die to be connected to the conductive pads of the bumpless die, and a dielectric pattern disposed on the insulating encapsulation and laterally covering the conductive pattern.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a conductive casing, a semiconductor die, a conductive connector, an insulating encapsulant, a redistribution structure, and a first conductive terminal. The conductive casing has a cavity. The semiconductor die is disposed in the cavity of the conductive casing. The conductive connector is disposed on a periphery of the conductive casing. The insulating encapsulant encapsulates the conductive connector, the semiconductor die and the cavity. The redistribution structure is formed on the insulating encapsulant and is electrically connected to the conductive connector and the semiconductor die. The first conductive terminal is disposed in openings of the redistribution structure and is physically in contact with a portion of the conductive casing.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a conductive casing, a semiconductor die, a conductive connector, an insulating encapsulant, a redistribution structure, and a first conductive terminal. The conductive casing has a cavity. The semiconductor die is disposed in the cavity of the conductive casing. The conductive connector is disposed on a periphery of the conductive casing. The insulating encapsulant encapsulates the conductive connector, the semiconductor die and the cavity. The redistribution structure is formed on the insulating encapsulant and is electrically connected to the conductive connector and the semiconductor die. The first conductive terminal is disposed in openings of the redistribution structure and is physically in contact with a portion of the conductive casing.

Abstract: A semiconductor package includes a semiconductor die, a first redistribution structure, a conductive structure, and an insulating encapsulant. The first redistribution structure includes a dielectric protrusion. The first redistribution structure includes a die attach region and a peripheral region surrounding the die attach region. The semiconductor die is disposed on the first redistribution structure within the die attach region. The dielectric protrusion is disposed in the peripheral region and extends in a thickness direction of the semiconductor die. The conductive structure is disposed on the first redistribution structure within the in the peripheral region and encapsulates the semiconductor dielectric protrusion. The conductive structure is electrically coupled to the first redistribution structure and the semiconductor die. The insulator is disposed on the first redistribution structure and encapsulates the semiconductor die and the conductive structure.

Abstract: A semiconductor package including a stacked-die structure, a second encapsulant laterally encapsulating the stacked-die structure and a redistribution layer disposed on the second encapsulant and the staked-die structure is provided. The stacked-die structure includes a first semiconductor die including a first active surface, a circuit layer disposed on the first active surface, a second semiconductor die including a second active surface facing towards the first active surface, a plurality of conductive features distributed at the circuit layer and electrically connected to the first and second semiconductor die and a first encapsulant encapsulating the second semiconductor die and the conductive features. A portion of the conductive features surrounds the second semiconductor die. The redistribution layer is electrically connected to the staked-die structure. A manufacturing method of a semiconductor package is also provided.

Abstract: A semiconductor package including a redistribution layer, semiconductor devices, a semiconductor die, conductive features, an encapsulant and conductive terminals is provided. The semiconductor devices are disposed on the first surface of the redistribution layer. The semiconductor die, the conductive features, the encapsulant including openings are disposed on the second surface of the redistribution layer. The semiconductor die is embedded in the encapsulant, and the portion of the conductive features is protruded from the encapsulant. The conductive terminals including first elements disposed in the openings of the encapsulant and second elements disposed on the conductive features. A portion of the first elements and the second elements are protruded from the encapsulant, and a surface of each of the first elements opposite to the encapsulant and a surface of each of the second elements are aligned with a standoff baseline. A manufacturing method of semiconductor package is also provided.

Abstract: A semiconductor package including a stacked-die structure, a second encapsulant laterally encapsulating the stacked-die structure and a redistribution layer disposed on the second encapsulant and the staked-die structure is provided. The stacked-die structure includes a first semiconductor die including a first active surface, a circuit layer disposed on the first active surface, a second semiconductor die including a second active surface facing towards the first active surface, a plurality of conductive features distributed at the circuit layer and electrically connected to the first and second semiconductor die and a first encapsulant encapsulating the second semiconductor die and the conductive features. A portion of the conductive features surrounds the second semiconductor die. The redistribution layer is electrically connected to the staked-die structure. A manufacturing method of a semiconductor package is also provided.

Abstract: A semiconductor device package includes an encapsulation layer, a die, a stress relief layer, and a redistribution layer. The encapsulation layer has an opening, and the die is disposed in the opening of the encapsulation layer. The stress relief layer is disposed between the encapsulation layer and the die. The redistribution layer is formed on the die, the stress relief layer and the encapsulation layer.

Abstract: A first semiconductor package of a POP structure has a first body and a plurality of first solder balls. A second semiconductor package of the POP structure has a second body and a plurality of second solder balls. A stand-off mechanism is utilized to maintain a minimum gap between the first body and the second body while a reflow soldering process is performed. By performing the reflow soldering process, the first solder balls and the second solder balls are heated and engaging with one another so as to solder the first solder balls and the second solder balls to form a plurality of interposer solder balls. Each interposer solder ball has a height substantially equal to the minimum gap and a cross sectional width less than a pitch between two adjacent interposer solder balls. Thereby, the POP structure would be a fine pitch package.

Abstract: A first semiconductor package of a POP structure has a first body and a plurality of first solder balls. A second semiconductor package of the POP structure has a second body and a plurality of second solder balls. A stand-off mechanism is utilized to maintain a minimum gap between the first body and the second body while a reflow soldering process is performed. By performing the reflow soldering process, the first solder balls and the second solder balls are heated and engaging with one another so as to solder the first solder balls and the second solder balls to form a plurality of interposer solder balls. Each interposer solder ball has a height substantially equal to the minimum gap and a cross sectional width less than a pitch between two adjacent interposer solder balls. Thereby, the POP structure would be a fine pitch package.

Abstract: A semiconductor device package includes an encapsulation layer, a die, at least one trace stiffener, and a redistribution layer. The encapsulation layer has an opening. The die is disposed in the opening of the encapsulation layer. The redistribution layer is formed above the die and the encapsulation layer. The least one trace stiffener are formed on the redistribution layer above boundaries of the encapsulation layer and the die for reinforcing a structure of the redistribution layer above the boundaries of the encapsulation layer and the die.

Abstract: A semiconductor device includes a first chip, a spacer, and a second chip. The first chip and the spacer are disposed on a substrate. The second chip has a first half end portion disposed on a first half end portion of the first chip, and a second half end portion disposed on the spacer. The height of the spacer is substantially equal to the height of the first chip.

Abstract: A package includes a chip, a wire, a mold layer and a redistribution layer. The chip includes a conductive pad. The wire is bonded to the conductive pad of the chip. The mold layer surrounds the first chip and the wire. The redistribution layer is disposed on the mold layer and contacts an exposed portion of the wire.

Abstract: Disclosed is a fan-out back-to-back chip stacked package, comprising a back-to-back stack of a first chip and a second chip, an encapsulant, a plurality of vias disposed in the encapsulant, a first redistribution layer and a second redistribution layer. The encapsulant encapsulates the sides of the first chip and the sides of the second chip simultaneously and has a thickness not greater than the chip stacked height to expose a first active surface of the first chip and a second active surface of the second chip. The encapsulant has a first peripheral surface expanding from the first active surface and a second peripheral surface expanding from the second active surface. The first redistribution layer is formed on the first active surface and extended onto the first peripheral surface to electrically connect the first chip to the vias in the encapsulant.

Abstract: A package structure includes a chip, a substrate, wires and a molding compound. The chip includes an active surface, a back surface opposite to the active surface and bonding pads disposed on the active surface. The substrate includes a first solder mask, a first patterned circuit layer and a core layer having a first surface and a second surface opposite to the first surface. The first patterned circuit layer is disposed on the first surface. The first solder mask disposed on the first surface partially exposes the first patterned circuit layer. The substrate disposed on the active surface with the second surface exposes the bonding pads. The wires are connected between the first patterned circuit layer and the bonding pads. The molding compound covers the chip, the wire and the substrate. A top surface of the molding compound is coplanar with a top surface of the first solder mask.