PROCESS FOR AUTOMATIC DYNAMIC RELOADING OF DATA FLOW PROCESSORS (DFPs) AND UNITS WITH TWO- OR THREE-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES (FPGAs, DPGAs AND THE LIKE)
In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.
This application is a continuation of U.S. patent application Ser. No. 10/265,846, filed Oct. 7, 2002, which is a continuation of U.S. patent application Ser. No. 09/613,217, filed Jul. 10, 2000, now U.S. Pat. No. 6,477,643, which is a continuation of U.S. patent application Ser. No. 08/947,002 filed on Oct. 8, 1997, now U.S. Pat. No. 6,088,795, expressly incorporated herein by reference in the entirety.
FIELD OF THE INVENTIONThe present invention is directed to a process for automatic dynamic reloading of data flow processors.
BACKGROUND INFORMATIONProgrammable units presently used (DFPs, FPGAs—Field Programmable Gate Arrays) can be programmed in two different ways:
-
- one-time only, i.e., the configuration can no longer be changed after programming. All configured elements of the unit perform the same function over the entire period during which the application takes place.
- on site, i.e., the configuration can be changed after the unit has been installed by loading a configuration file when the application is started. Most units (in particular FPGA units) cannot be reconfigured during operation. For reconfigurable units, data usually cannot be further processed while the unit is being reconfigured, and the time required is very long.
Configuration data is loaded into programmable units through a hardware interface. This process is slow and usually requires hundreds of milliseconds due to the limited band width accessing the external memory where the configuration data is stored, after which the programmable unit is available for the desired/programmed function as described in the configuration file.
A configuration is obtained by entering a special bit pattern of any desired length into the configurable elements of the unit. Configurable elements can be any type of RAM cells, multiplexers, interconnecting elements or ALUs. A configuration string is stored in such an element, so that the element preserves its configuration determined by the configuration string during the period of operation.
The existing methods and options present a series of problems, such as:
-
- If a configuration in a DFP (see German Patent Application No. DE 44 16 881 A1) or an FPGA is to be modified, a complete configuration file must always be transmitted to the unit to be programmed, even if only a very small part of the configuration is to be modified.
- As a new configuration is being loaded, the unit can only continue to process data to a limited extent or not at all.
- With the increasing number of configurable elements in each unit (in particular in FPGA units), the configuration files of these units also become increasingly large (several hundred Kbytes on average). Therefore it takes a very long time to configure a large unit and often makes it impossible to do it during operation or affects the function of the unit.
- When a unit is partially configured during operation, a central logic entity is always used, through which all reconfigurations are managed. This requires considerable communication and synchronization resources.
The present invention makes it possible to reconfigure a programmable unit considerably more rapidly. The present invention allows different configurations of a programmable unit to be used in a flexible manner during operation without affecting or stopping the operability of the programmable unit. Unit configuration changes are performed simultaneously, so they are rapidly available without need for additional configuration data to be occasionally transmitted. The method can be used with all types of configurable elements of a configurable unit and with all types of configuration data, regardless of the purpose for which they are provided within the unit.
The present invention makes it possible to overcome the static limitations of conventional units and to improve the utilization of existing configurable elements. By introducing a buffer storage device, a plurality of different functions can be performed on the same data.
In a programmable unit, there is a plurality of ring memories, i.e., memories with a dedicated address control, which, upon reaching the end of the memory, continues at the starting point, thus forming a ring. These ring memories have read-write access to configuration registers, i.e., the circuits that receive the configuration data, of the elements to be configured. Such a ring memory has a certain number of records, which are loaded with configuration data by a PLU as described in German Patent Application No. 44 16 881 A1. The architecture of the records is selected so that their data format corresponds to the configurable element(s) connected to the ring memory and allows a valid configuration to be set.
Furthermore, there is a read position pointer, which selects one of the ring memory records as the current read record. The read position pointer can be moved to any desired position/record within the ring memory using a controller. Furthermore there is a write position pointer, which selects one of the ring memory records as the current write record. The write position pointer can be moved to any desired position/record within the ring memory using a controller.
At run time, to perform reconfiguration, a configuration string can be transmitted into the element to be configured without the data requiring management by a central logic or transmission. By using a plurality of ring memories, several configurable elements can be configured simultaneously.
Since a ring memory with its complete controller can switch configurable cells between several configuration modes, it is referred to as a switching table.
There is a plurality of ring memories in a programmable unit or connected externally to said unit. The one or more ring memories have one or more controllers controlling the one or more ring memories. These controllers are part of the PLU named in German Patent Application No. DE 44 16 881 A1. The ring memories contain configuration strings for the configurable elements of one or a plurality of configurable units; the configurable elements can also be expressly used for interconnecting function groups and they can be crossbar circuits or multiplexers for interconnecting bus architectures, which are conventional.
Ring memories and ring memory controllers can be either directly hardware-implemented or first obtained by configuring one or more configurable cells of a configurable unit (e.g., FPGA).
Conventional ring memories can be used as ring memories, in particular ring memories and/or controllers with the following properties:
-
- where not all records are used, and which have the capability of providing a position where the read and/or write position pointer of the ring memory is set to the beginning or the end of the ring memory. This can be implemented, for example, by using command strings (STOP, GOTO, etc.), counters, or registers storing the start and stop positions;
- which make it possible to divide the ring memory into independent sections, and the controller of the ring memory can be set, for example, via the events listed below as examples, so that it works on one of these sections;
- which make it possible to divide the ring memory into independent sections and there is a plurality of controllers, each one working on one section; a plurality of controllers may work on the same section. This can be implemented via arbiter switching, in which case certain processing cycles are lost. Registers can also be used instead of RAMs;
- each controller has one or more read position pointers and/or one or more write position pointers;
- this position pointer can be moved forward and/or backward;
- this position pointer can be set to the start, end, or a given position on the basis of one or more events;
- the controller has a mask register with which a subset can be selected from the set of all possible events by entering a data string. Only this subset of results is relayed to the controller as an event and triggers the forwarding of the position pointer(s);
- controllers working with a multiple of the actual system clock rate (oversampling) to allow the processing of several records within a system cycle.
The switching table controller is implemented using a regular state machine. In addition to simple controllers required by a conventional ring memory, controllers with the following properties are best suited for performing or possibly expanding the control of the switching tables of a programmable unit (in particular also of FPGAs and DPGAs (Dynamically Programmable Gate Arrays, a new subgroup of FPGAs)) according to the present invention:
-
- controllers capable of recognizing specific command strings. A command string is distinguished by the fact that it has an identifier, which allows the controller to recognize the data of a ring memory record as a command string rather than a data string;
- controllers capable of executing specific command strings; specifically commands that change the sequence of the state machine and/or modify records of the ring memory through a data processing function;
- controllers capable of recognizing an identifier and of processing additional records of the ring memory through the internal, higher-speed cycle (oversampling) on the basis of this identifier, until an end identifier is reached, or the next cycle of the clock that controls the oversampling cycle is reached.
In particular the following commands or a subset of those commands can be used as command strings for the appropriate control of a switching table requiring command string control. The command strings concerning position pointers can be used on the read position pointer(s) or on the write position pointer(s). Possible command strings include:
-
- a WAIT command.
- The WAIT command causes the controller to wait until the next event or (possibly several) events occur. During this state, the read/write position pointer(s) is(are) not moved. If the event(s) occur(s), the read/write position pointer(s) is (are) positioned on the next record.
- a SKIP command.
- The SKIP command causes a given number of ring memory records to be skipped by one of the following two methods:
- The SKIP1 command is executed fully in a single processing cycle. If, for example, SKIP 5 is issued, the pointer jumps to the record located five records before (after) the current read/write record in a processing cycle.
- The SKIP2 command is only executed after a number of processing cycles. It is conceivable, for example, that the SKIP 5 command is executed only after five processing cycles. Here again five records are skipped counting from the current record. The parameter (in this case the 5) is thus used twice.
The indication of the direction of jump can end either in a forward movement or in a backward movement of the position pointer with the use of a positive or negative number.
-
- A SWAP command.
- The SWAP command swaps the data of two given records.
- RESET command.
- The RESET command sets the read/write position pointer(s) to the start and/or a given record position within the ring memory.
- A WAIT-GOTO command.
- The WAIT-GOTO command waits like the above-described WAIT command for one or more specific events and then positions the read/write position pointer to a specific start state within one or more processing cycles.
- A NOP command.
- The NOP command executes no action. No data is transmitted from the ring memory to the element(s) to be configured, neither are the position pointers modified. Thus the NOP command identifies a record as non-relevant. However, this record is addressed and evaluated by the ring memory controller it requires using one or more processing cycles.
- A GOTO command.
- The GOTO command positions the read/write position pointer(s) on the given record position.
- A MASK command.
- The MASK command writes a new data string into the multiplexer, which selects the different events. Therefore, this command allows the events to which the controller responds to be changed.
- An LLBACK command.
- The LLBACK command generates a feedback to the PLU (as described in German Patent Application No. DE 44 16 881 A1). The switching table can cause greater regions of the unit to be reloaded, in particular it can cause the switching table itself to be reloaded.
- A command triggering a read/modify/write cycle. The command triggers the reading of commands or data in another record, for example, by the controller, the PLU or an element located outside the switching table. This data is then processed in any desired fashion and written into the same or another position of the switching table ring memory. This can take place during one processing cycle of the switching table. The sequence is then terminated before a position pointer is repositioned.
The ring memory record architecture has the following format:
The first bit identifies a record as a command or a data string. The controller of the switching table thus decides whether the bit string in the data portion of the record should be treated as a command or as configuration data.
The second bit identifies whether the controller should proceed immediately even without the occurrence of another event, should proceed with the next record, or wait for the next event. If an oversampling process is used and the RUN bit is set, the subsequent records will be processed with the help of this oversampling cycle. This continues until a record without a RUN bit set has been reached or the number or records that can be processed at the oversampling cycle rate within one system cycle has been reached.
If an oversampling process is used, the normal system cycle and the RUN bit set cause commutation to take place. Events occurring during the execution of a command sequence marked with the RUN bit are analyzed and the trigger signal is stored in a flip-flop. The controller then analyzes this flip-flop again when a record without a RUN bit set is reached.
The rest of a record contains, depending on the type (data or command), all the necessary information, so that the controller can fully perform its function.
The size of the ring memory can be implemented according to the application; this is true in particular for programmable units, where the ring memory is obtained by configuring one or more configurable cells.
A ring memory is connected to an element to be configured (or a group of elements to be configured), so that a selected configuration string (in the ring memory) is entered in the configuration register of the element to be configured or group of elements to be configured.
Thus a valid and operational configuration of the element or group to be configured is obtained.
Each ring memory has one controller or a plurality of controllers, which control the positioning of the read position pointer and/or the write position pointer.
Using the feedback channels described in German Patent Application DE 44 16 881 A1, the controller can respond to events of other elements of the unit or to external events that are transmitted into the unit (e.g., interrupt, IO protocols, etc.) and, in response to these internal or external events, moves the read position pointer and/or the write position pointer to another record.
The following events are conceivable, for example:
-
- clock signal of a CPU,
- internal or external interrupt signal,
- trigger signal of other elements within the unit,
- comparison of a data stream and/or a command stream with a value,
- input/output events,
- counter run, overrun, reset,
- evaluation of a comparison.
If a unit has several ring memories, the controller of each ring memory can respond to different events.
After each time the pointer is moved to a new record, the configuration string in this record is transferred to the configurable element(s) connected to the ring memory.
This transfer takes place so that the operation of the unit parts that are not affected by the reconfiguration remains unchanged.
The ring memory(ies) may be located either in a unit or connected to the unit from the outside via an external interface.
Each unit may have a plurality of independent ring memories, which can be concentrated in a region of the unit, but can also be distributed in a reasonable manner on the surface of the unit.
The configuration data is loaded by a PLU, such as described in German Patent Application No. DE 44 16 881 A1, or by other internal cells of the unit into the memory of the switching table. The configuration data can also be simultaneously transferred by the PLU or other internal cells of the unit to several different switching tables in order to allow the switching tables to load simultaneously.
The configuration data can also be in the main memory of a data processing system and be transferred by known methods, such as DMA or other processor-controlled data transfer, instead of the PLU.
After the PLU has loaded the ring memory of the switching table, the controller of the switching table is set to a start status, which establishes a valid configuration of the complete unit or parts of the unit. The control of the switching table starts now with repositioning of the read position pointer and/or the write position pointer as a response to events taking place.
In order to cause new data to be loaded into the switching table or a number of switching tables, the controller can return a signal to the PLU, as described in German Patent Application No. DE 44 16 881 A1, or other parts of the unit that are responsible for loading new data into the ring memory of the switching table. Such a feedback can be triggered by the analysis of a special command, a counter status, or from the outside (the State-Back UNIT described in Patent Application PACT02).
The PLU or other internal cells of the unit analyze this signal, respond to the signal by executing a program possibly in a modified form, and transfer new or different configuration data to the ring memory(ies). Only the data of each ring memory that is involved in a data transfer as determined by the signal analysis, rather than the configuration data of a complete unit, must be transferred.
Buffer: A memory can be connected to individual configurable elements or groups thereof (hereinafter referred to as functional elements). Several known procedures can be used to configure this memory; FIFOs are well-known, in particular. The data generated by the functional elements are stored in the memory until a data packet with the same operation to be performed is processed or until the memory is full. Thereafter the configuration elements are reconfigured through switching tables, i.e., the functions of the elements are changed. FullFlag showing that the memory is full can be used as a trigger signal for the switching tables. In order to freely determine the amount of data, the position of the FullFlag is configurable, i.e., the memory can also be configured through the switching table. The data in the memory is sent to the input of the configuration elements, and a new operation is performed on the data; the data is the operand for the new computation. The data can be processed from the memory only, or additional data can be requested from the outside (outside the unit or other functional elements) for this purpose. As the data is processed, it (the result of the operation) can be forwarded to the next configuration elements or written into the memory again. In order to provide both read and write access to the memory, the memory can have two memory arrays, which are processed alternately, or separate read and write position pointers can exist in the same memory.
One particular configuration option is the connection of a plurality of memories as described above, which allows several results to be stored in separate memories; then, at a given time, several memory regions are sent to the input of a functional element and processed in order to execute a given function.
Architecture of a ring memory record: One possible structure of the records in a switching table ring memory, used in a data processing system as described in German Patent Application No. DE 44 16 881 A1 is described below. The following tables show the command architecture using the individual bits of a command string.
Thus, if a record is a data record, bit number 0 has the value 0, so the bits from position two have the following meanings:
If the record is a command, bit number 0 has the value 1, and the bits from position two have the following meanings:
In the following table, bits 2-6 and 8-n are shown for each of the commands listed. The overall bit length of a data string depends on the unit where the switching table is used. The bit length must be chosen so as to code all data needed for the commands in the bits starting from position 8.
Reconfiguring ALUs: One or more switching tables can be used for controlling an ALU. The present invention can be used, for example, to improve on Patent PACT02, where the switching table is connected to the M/F PLUREG registers or the M/F PLUREG registers are fully replaced by a switching table.
In addition to the configuration of the ring memory by the PLU, the ring memory can also be set as follows: Configurable element 0903 is wired so that it generates, alone or as the last element of a group of elements, records for ring memory 0906. It generates a trigger pulse, which advances the write position pointer in the ring memory. In this mode, multiplexer 0904 switches the data from 0903 through to the ring memory, while with a configuration by the PLU the data are switched through by the PLU. It would, of course, be conceivable that additional permanently implemented functional units might serve as sources of the configuration signals.
-
- If it is a SKIP command, state machine 1011 sends a pulse to adder/subtractor 1006 so it can add/subtract the bit 8-n command string data to/from the data sent by counters 1004, 1005 via multiplexer 1003. Depending on bit 7, multiplexer 1003 selects the counter of write position pointer 1004 or the counter of read position pointer 1005. After the data has been added/subtracted, state machine 1011 activates gate 1010 and sends a receive signal to counter 1004, 1005. Thus the selected position pointer points as many positions forward or backward as set forth in the data of the SKIP command.
- Upon a GOTO command, gate 1007 is activated by state machine 1011 so that the data goes to read position pointer 1005 or write position pointer 1004 and is received there.
- Upon a MASK command, the data is received in a latch 1008 and stored there. This data is then available to the controller described in FIGS. 7/7a via line A (1013) where it masks all the trigger inputs which should receive no trigger pulse.
- Upon a WAIT command, an event is waited for as often as set forth in the data bits. If this command is registered by state machine 1011, it sends a pulse to wait cycle counter 1009 which receives the data. The wait cycle counter then counts one position downward for each event relayed by state machine 1011. As soon as it has counted to zero, the carry flag is set and sent to state machine 1011 (1023). The state machine then continues to operate due to the carry flag.
- Upon a WAIT-GOTO command, the data providing the number of wait events is received in the wait cycle counters. After receipt of the number of events given in the data, the state machine activates gate 1007 and relays the jump position data to the selected counter.
- The SWAP command is used for swapping two records between two positions of the ring memory. The address of the first record to be swapped is stored in latch 1017; the address of the second record is stored in latch 1018. The addresses are sent to multiplexers 1015 and 1016 of the read/write pointer. Initially, record 1 is selected via 1016 and stored in latch 1019; then record 2 is selected via 1016 and stored in 1020. The write pointer is first positioned on the first record via 1015, and the data formerly of the second record is stored via gate 1022. Then the write pointer is positioned on the second record via 1015 and the data formerly of the first record is stored via gate 1021.
- State machine 1011 sends feedback to the PLU via 1014 (e.g., via a State-Back UNIT, see PACT02). The state machine sends a signal via this connection as soon as an LLBack command is registered.
- Bit 1, used as a run flag, is sent to the controller for generating a clock signal, which is described in
FIG. 8 . - The NOP command is registered in the state machine, but no operation is performed.
- ALU Arithmetic Logic Unit. Basic unit for data processing. The unit can perform arithmetic operations such as addition, subtraction, and occasionally also multiplication, division, expansions of series, etc. The unit can be configured as an integer unit of a floating-point unit. The unit can also perform logic operations such as AND, OR, as well as comparisons.
- data string A data string is a series of bits, of any length. This series of bits represents a processing unit for a system. Both commands for processors or similar components and data can be coded in a data string.
- DFP Data flow processor according to German Patent No. DE 44 16 881.
- DPGA Dynamically Configurable FPGAs. Related art.
- D Flip-Flop Memory element, which stores a signal at the rising edge of a cycle.
- EALU Expanded Arithmetic Logic Unit, ALU which has been expanded to perform special functions needed or convenient for the operation of a data processing device according to German Patent Application No. DE 441 16 881 A1. These are, in particular, counters.
- Elements Generic concept for all enclosed units used as a part in an electronic unit. Thus, the following are defined as elements:
- configurable cells of all types
- clusters
- RAM blocks
- logics
- arithmetic units
- registers
- multiplexers
- I/O pins of a chip
- Event An event can be analyzed by a hardware element in any manner suitable for the application and trigger an action as a response to this analysis. Thus, for example, the following are defined as events:
- clock pulse of a CPU
- internal or external interrupt signal
- trigger signal from other elements within the unit
- comparison of a data stream and/or a command stream with a value
- input/output events
- run, overrun, reset of a counter
- analysis of a comparison
- flag Status bit in a register showing a status.
- FPGA Programmable logic unit. Related art.
- gate Group of transistors that performs a basic logic function. Basic functions include NAND, NOR. Transmission gates.
- configurable element A configurable element represents a component of a logic unit, which can be set for a special function using a configuration string. Configurable elements are therefore all types of RAM cells, multiplexers, arithmetic logic units, registers, and all types of internal and external interconnecting units, etc.
- configure Setting the function and interconnections of a logic unit, an FPGA cell or a PAE (see reconfigure).
- configuration data Any set of configuration strings.
- configuration memory The configuration memory contains one or more configuration strings.
- configuration string A configuration string consists of a series of bits, of any length. This bit series represents a valid setting for the element to be configured, so that an operable unit is obtained.
- PLU Unit for configuring and reconfiguring the PAE. Constituted by a microcontroller designed specifically for this purpose.
- latch Memory element that usually relays a signal transparently during the H level and stores it during the L level. Latches where the level function is reversed are used in some PAEs. Here an inverter is normally connected before the cycle of a normal latch.
- read position pointer Address of the current record for read access within a FIFO or a ring memory.
- logic cells Cells used in DFPs, FPGAs, and DPGAs, performing simple logic and arithmetic functions, depending on their configuration.
- oversampling A clock runs with a frequency that is a multiple of the base clock, synchronously with the same. The faster clock is usually generated by a PLL.
- PLL Phase Locked Loop. Unit for generating a multiple of a clock frequency on the basis of a base clock.
- PLU Units for configuring and reconfiguring the PAE. Constituted by a microcontroller specifically designed for this purpose.
- ring memory Memory with its own read/write position pointer, which—upon reaching the end of the memory—is positioned at the beginning of the memory. An endless ring-shaped memory is thus obtained.
- RS flip-flop Reset/Set flip-flop. Memory element that can be switched by two signals.
- write position pointer Address of the current record for write access within a FIFO or ring memory.
- State-Back unit Unit that controls the feedback of status signals to the PLU, comprising a multiplexer and an open-collector bus driver element.
- switching table A switching table is a ring memory, which is addressed by a controller. The records of a switching table may contain any configuration strings. The controller can execute commands. The switching table responds to trigger signals and reconfigures configurable elements using a record in a ring memory.
- gate Switch that forwards or blocks a signal. Simple comparison: relay.
- reconfigure New configuration of any number of PAEs, while any remaining number of PAEs continue their functions (see configure).
- processing cycle A processing cycle describes the time required by a unit to go from a specific and/or valid state into the next specific and/or valid state.
- state machine Logic that can assume different states. The transition between the states depends on different input parameters. These machines are used for controlling complex functions and correspond to the related art.
unit—UNIT
mode—MODE
multiplexer—MUX
negated signal not-
register visible to PLU—PLUREG
internal register—REG
shift register—sft
shift registersft
AND function &
OR function#
NOT function!
GATE functionG
Claims
1. A field programmable gate array integrated circuit comprising:
- a high level configuration load unit; and
- a plurality of cells configurable by the high level configuration load unit, at least some of the configurable cells being dynamically configurable at runtime by others of the configurable cells;
- wherein at least one intermediate level configuration unit of the field programmable gate array integrated circuit is located between the high level configuration load unit and the at least some of the configurable cells, the at least one intermediate level configuration unit being adapted for configuring, dynamically at runtime, the at least some of the configurable cells.
2. The field programmable gate array integrated circuit according to claim 1, wherein the field programmable gate array includes a memory arrangement for the at least one intermediate level configuration unit for receiving configuration strings from the high level configuration load unit.
3. The field programmable gate array integrated circuit according to claim 2, wherein the intermediate level configuration unit comprises a controller for selecting from the memory arrangement a configuration string to be dynamically loaded into the at least some of the configurable cells.
4. The field programmable gate array integrated circuit according to claim 3, wherein the controller is controlled by at least one event signal.
5. The field programmable gate array integrated circuit according to claim 3, wherein the controller comprises at least one pointer into said memory arrangement for selecting from the memory arrangement a configuration string to be dynamically loaded into the at least some of the configurable cells.
6. The field programmable gate array integrated circuit according to claim 5, wherein the pointer is controlled by at least one event signal.
7. The field programmable gate array integrated circuit according to any one of claims 4 and 6, wherein at least one of the at least one event signal is generated by at least one of the configurable cells.
8. The field programmable gate array integrated circuit according to any one of claims 4 and 6, wherein at least one of the at least one event signal is a clock signal.
9. The field programmable gate array integrated circuit according to any one of claims 1, 2, 3, and 5, wherein the intermediate level configuration unit dynamically configures a subset of the at least some of the configurable cells.
10. The field programmable gate array integrated circuit according to any one of claims 1, 2, 3, and 5, wherein the intermediate level configuration unit is hardwired into the field programmable gate array integrated circuit.
11. The field programmable gate array integrated circuit according to any one of claims 1, 2, 3, and 5, wherein the intermediate level configuration unit is configured into cells of the field programmable gate array integrated circuit.
12. An intermediate level configuration unit for implementation in a field programmable gate array integrated circuit, wherein the intermediate level configuration unit is located between a high level configuration load unit and at least some of configurable cells that are dynamically configurable at runtime by other cells of the field programmable gate array integrated circuit, the intermediate level configuration unit comprising:
- memory for receiving configuration strings from the high level configuration load unit; and
- a controller including at least one pointer into the memory for selecting from the memory a configuration string to be dynamically loaded into the at least some of the configurable cells.
13. The intermediate level configuration unit according to claim 12, wherein each entry in said memory pointed to by said at least one pointer contains at least one configuration string for one of the configurable cells.
14. The intermediate level configuration unit according to claim 12, wherein each entry in said memory pointed to by said at least one pointer contains at least one configuration string for a subset of the configurable cells.
15. The intermediate level configuration unit according to any one of claims 12, 13, and 14, wherein the controller is controlled by at least one event signal.
16. The intermediate level configuration unit according to claim 15, wherein at least one of the at least one event signal is generated by at least one of the configurable cells.
17. The intermediate level configuration unit according to claim 15, wherein at least one of the at least one event signal is a clock signal.
18. The intermediate level configuration unit according to any one of claims 12, 13, and 14, wherein the pointer is controlled by at least one event signal.
19. The intermediate level configuration unit according to any one of claims 12, 13, and 14, wherein the intermediate level configuration unit is hardwired into the field programmable gate array integrated circuit.
20. The intermediate level configuration unit according to any one of claims 12, 13, and 14, wherein the intermediate level configuration unit is configured into cells of the field programmable gate array integrated circuit.
21. A field programmable gate array integrated circuit comprising:
- a high level configuration load unit; and
- a plurality of configurable cells, at least some of the configurable cells being dynamically configurable at runtime by other cells of the plurality of configurable cells, and at least some of the configurable cells being adapted to operate as local memory cells.
22. The field programmable gate array integrated circuit according to claim 21, wherein at least some of the local memory cells operate in a FIFO mode.
23. The field programmable gate array integrated circuit according to claim 21, wherein at least some of the local memory cells are adapted for locally storing configuration strings for dynamically configuring the at least some of the configurable cells being dynamically configurable at runtime by other cells of the field programmable gate array.
24. The field programmable gate array integrated circuit according to claim 21, wherein at least some of the local memory cells are adapted for at least one of transmitting data to and receiving data from the at least some of the configurable cells being dynamically configurable at runtime by other cells of the field programmable gate array.
25. The field programmable gate array integrated circuit according to claim 21, wherein at least some of the local memory cells are adapted for simultaneously transmitting data to and receiving data from at least one of the configurable cells being dynamically configurable at runtime by other cells of the field programmable gate array.
26. A runtime reconfigurable processing integrated circuit comprising:
- a plurality of cells configurable by a high level configuration load unit, at least some of the configurable cells being dynamically configurable at runtime by others of the configurable cells;
- wherein at least one intermediate level configuration unit of the runtime reconfigurable processing integrated circuit is located between the high level configuration load unit and the at least some of the configurable cells, and is adapted for configuring the at least some of the configurable cells.
27. The runtime reconfigurable processing integrated circuit according to claim 26, wherein a memory arrangement is provided for the at least one intermediate level configuration unit for receiving configuration strings from the high level configuration load unit.
28. The runtime reconfigurable processing integrated circuit according to claim 27, wherein the intermediate level configuration unit comprises a controller for selecting from the memory arrangement a configuration string to be dynamically loaded into the at least some of the configurable cells.
29. The runtime reconfigurable processing integrated circuit according to claim 28, wherein the controller comprises at least one pointer into said memory for selecting from the configuration memory a configuration string to be dynamically loaded into the at least some of the configurable cells.
30. The runtime reconfigurable processing integrated circuit according to claim 29, wherein the pointer is controlled by at least one event signal.
31. The runtime reconfigurable processing integrated circuit according to claim 28, wherein the controller is controlled by at least one event signal.
32. The runtime reconfigurable processing integrated circuit according to any one of claims 30 and 31, wherein at least one of the at least one event signal is generated by at least one of the configurable cells.
33. The runtime reconfigurable processing integrated circuit according to any one of claims 30 and 31, wherein at least one of the at least one event signal is a clock signal.
34. The runtime reconfigurable processing integrated circuit according to any one of claims 26, 27, 28, and 29, wherein the intermediate level configuration unit dynamically configures a subset of the at least some of the configurable cells.
35. The runtime reconfigurable processing integrated circuit according to any one of claims 26, 27, 28, and 29, wherein the at least one intermediate level configuration unit is hardwired into the runtime reconfigurable processing integrated circuit.
36. The runtime reconfigurable processing integrated circuit according to any one of claims 26, 27, 28, and 29, wherein the at least one intermediate level configuration unit is configured into cells of the runtime reconfigurable processing integrated circuit.
37. An intermediate level configuration unit for implementation in a runtime reconfigurable processing integrated circuit, wherein the intermediate level configuration unit is located between a high level configuration load unit and at least some of configurable cells that are dynamically configurable at runtime by other cells of the runtime reconfigurable processing integrated circuit, the intermediate level configuration unit comprising:
- memory for receiving configuration strings from the high level configuration load unit; and
- a controller including at least one pointer into the memory for selecting from the memory a configuration string to be dynamically loaded into the at least some of the configurable cells.
38. The intermediate level configuration unit according to claim 37, wherein each entry in said memory pointed to by said pointer contains at least one configuration string for one of the configurable cells.
39. The intermediate level configuration unit according to claim 37, wherein each entry in said memory pointed to by said pointer contains at least one configuration string for a subset of the configurable cells.
40. The intermediate level configuration unit according to any one of claims 37, 38, and 39, wherein the controller is controlled by at least one event signal.
41. The intermediate level configuration unit according to claim 40, wherein at least one of the at least one event signal is generated by at least one of the configurable cells.
42. The intermediate level configuration unit according to claim 40, wherein at least one of the at least one event signal is a clock signal.
43. The intermediate level configuration unit according to any one of claims 37, 38, and 39, wherein the pointer is controlled by at least one event signal.
44. The intermediate level configuration unit according to any one of claims 37, 38, and 39, wherein the intermediate level configuration unit is hardwired into the runtime reconfigurable processing integrated circuit.
45. The intermediate level configuration unit according to any one of claims 37, 38, and 39, wherein the intermediate level configuration unit is configured into cells of the runtime reconfigurable processing integrated circuit.
Type: Application
Filed: Feb 19, 2009
Publication Date: Jun 18, 2009
Inventors: Martin VORBACH (KARLSRUHE), Robert MUNCH (KARLSRUHE)
Application Number: 12/389,155
International Classification: H03K 19/173 (20060101); H03K 19/177 (20060101);