Having Details Of Setting Or Programming Of Interconnections Or Logic Functions Patents (Class 326/38)
  • Patent number: 11916552
    Abstract: Techniques and apparatus for dynamically modifying a kernel (and associated user-specified circuitry) for a dynamic region of a programmable integrated circuit (IC) without affecting (e.g., while allowing) operation of other kernels ((and other associated user-specified circuitry) in the programmable IC. Dynamically modifying a kernel may include, for example, unloading an existing kernel, loading a new kernel, or replacing a first kernel with a second kernel). In the case of networking (e.g., in a data center application) where the programmable IC may be part of a hardware acceleration card (e.g., a network interface card (NIC)), the kernel may be user code referred to as a “plugin.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: February 27, 2024
    Assignee: XILINX, INC.
    Inventors: Ellery Cochell, Ripduman Singh Sohan, Kieran Mansley
  • Patent number: 11915742
    Abstract: A wafer-on-wafer formed memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of a genetic sequence from the memory die and through a wafer-on-wafer bond. The logic die can also perform a genome annotation lotic operation to attach biological information to the genetic sequence. An annotated genetic sequence can be provided as an output.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: February 27, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Sean S. Eilert, Kunal R. Parekh, Aliasger T. Zaidy, Glen E. Hush
  • Patent number: 11900995
    Abstract: Various implementations described herein are related to a method for accessing a bitcell in an array of bitcells with a wordline and a bitline. The method may perform a precharge operation on the bitline that precharges the bitline after a read cycle and before a write cycle. Also, the method may extend precharge time of the precharge operation between the read cycle and the write cycle, e.g., by modulating a wordline signal on the wordline with early cut-off of the wordline signal on the wordline during the read cycle.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: February 13, 2024
    Assignee: Arm Limited
    Inventors: Rajiv Kumar Sisodia, Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Ayush Kulshrestha, Munish Kumar
  • Patent number: 11881853
    Abstract: A true complement dynamic circuit for combining, in particular comparing, binary data on dynamic first and second input signals to third and fourth input signals, comprising at least a 1-bit compare circuit, wherein the dynamic first and second input signals are complementary signals during an evaluation phase, wherein a logical behavior is determined by the third and fourth input signals. A method for operating a true complement dynamic circuit for combining, in particular comparing, binary data on dynamic first and second input signals to third and fourth input signals, comprising operating at least a 1-bit compare circuit, wherein the dynamic first and second input signals are complementary signals during an evaluation phase, determining a logical behavior by the third and fourth input signals.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: January 23, 2024
    Assignee: International Business Machines Corporation
    Inventors: Michael Berthold Kugel, Rolf Sautter, Amira Rozenfeld, Harry Barowski
  • Patent number: 11862373
    Abstract: Memory stacks, memory devices and method of forming the same are provided. A memory stack includes a spin-orbit torque layer, a magnetic bias layer and a free layer. The magnetic bias layer is in physical contact with the spin-orbit torque layer and has a first magnetic anisotropy. The free layer is disposed adjacent to the spin-orbit torque layer and has a second magnetic anisotropy perpendicular to the first magnetic anisotropy.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shy-Jay Lin, Wilman Tsai, Ming-Yuan Song
  • Patent number: 11824046
    Abstract: The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: November 21, 2023
    Assignee: Invensas LLC
    Inventors: Javier A. DeLaCruz, Belgacem Haba, Rajesh Katkar
  • Patent number: 11815551
    Abstract: An I/O sensor including: a programmable delay line; a delayed clocked receiver having the following inputs: (a) a data signal and a reference voltage that also serve as inputs to a reference clocked receiver that is configured to sample the data signal received from an interconnect lane between two integrated circuits (ICs) of a multi-IC module, and (b) a delayed clock signal received from the programmable delay line, wherein the delayed clock signal is a delayed version of a clock signal that clocks the reference clocked receiver; a comparison circuits configured to compare a data signal output of the delayed clocked receiver and a data signal output of the reference clocked receiver; and a controller configured, based on a comparison result of the comparison circuit and on the amount of delay that caused it, to estimate a quality of connectivity between the two ICs over the interconnect lane.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: November 14, 2023
    Assignee: PROTEANTECS LTD.
    Inventors: Eyal Fayneh, Guy Redler, Evelyn Landman
  • Patent number: 11816253
    Abstract: An apparatus to facilitate enabling secure communication via attestation of multi-tenant configuration on accelerator devices is disclosed. The apparatus includes a processor to: verify a base bitstream of an accelerator device, the base bitstream published by a cloud service provider (CSP); verify partial reconfiguration (PR) boundary setups and PR isolation of an accelerator device, the PR boundary setups and PR isolation published by the CSP; generate PR bitstream to fit within at least one PR region of the PR boundary setups of the accelerator device; inspect accelerator device attestation received from a secure device manager (SDM) of the accelerator device; and responsive to successful inspection of the accelerator device attestation, provide the PR bitstream to the CSP for PR reconfiguration of the accelerator device.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: November 14, 2023
    Assignee: INTEL CORPORATION
    Inventors: Alpa Trivedi, Steffen Schulz, Patrick Koeberl
  • Patent number: 11817767
    Abstract: Proposed is a submodule of an MMC converter configured to stably supply power to a submodule controller controlling the submodule of an MMC converter. The submodule includes: an energy storage part storing electric energy therein; a plurality of switching elements connected in parallel to the energy storage part to have a shape of a bridge; a plurality of serially-connected resistors connected in parallel to the energy storage part; a plurality of DC-DC converters connected in parallel to a resistor of the plurality of resistors; a power switching part operating to select and output one voltage of voltages output from the plurality of DC-DC converters and a plurality of voltages input from outside; and a submodule controller operating with the voltage output by the power switching part so as to control switching operations of the plurality of switching elements.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: November 14, 2023
    Assignee: HYOSUNG HEAVY INDUSTRIES CORPORATION
    Inventors: Yong Hee Park, Sung Min Oh, Doo Young Lee, Hong Ju Jung
  • Patent number: 11809563
    Abstract: A system and method of protecting against control-flow attacks provides two complementary, transparent, and strong security policies for the RTL design at a hardware level. The approach performs static analysis of controller, followed by lightweight instrumentation, such that CFI is enforced in-place and at runtime. The modified controller follows conservative CFG with the help of a monitor.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: November 7, 2023
    Assignee: University of South Florida
    Inventors: Srinivas Katkoori, Sheikh Ariful Islam
  • Patent number: 11803394
    Abstract: An apparatus (10; 14; 16; 18) for programming an electronic device (12), in particular for ISP, ICP or PP programming, comprises electronic processing means (20; 45) suitable for processing and managing at least a programming algorithm of said electronic device (12); programming means (11) connected to said processing means (20; 45) and to said electronic device (12) for receiving from said processing means (20; 45) the programming data and for sending them to said electronic device (12) through a predetermined communication protocol; interface means (25) associated with said processing means (20; 45) and with said electronic device (12); and non-volatile electronic storage means (23; 22) adapted to exchange data with said electronic processing means (20; 45) by means of at least one bidirectional data communication line (32, 31).
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: October 31, 2023
    Inventors: Claudio Stefani, Ivan Rinaldi
  • Patent number: 11797531
    Abstract: The present disclosure includes apparatuses, methods, and systems for acceleration of data queries in memory. An example host apparatus includes a controller configured to generate a search key, generate a query for particular data stored in an array of memory cells in a memory device, and send the query to the memory device. The query includes a command to search for the particular data. The query also includes a number of data fields for the particular data including a logical block address (LBA) for the particular data, an LBA offset for the particular data, and a parameter for an amount of bits in data stored in the memory device that do not match corresponding bits in the search key that would result in data not being sent to the host.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: October 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Mark A. Helm, Joseph T. Pawlowski
  • Patent number: 11791823
    Abstract: Methods and apparatuses to provide FPGA inter-tile control signal sharing are described. In one embodiment, the FPGA inter-tile muxing for control signals is added in a separate tile. In another embodiment, the control signal muxing is distributed among FPGA tiles and shared using a cascaded configuration.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: October 17, 2023
    Assignee: EFINIX, INC.
    Inventors: Marcel Gort, Brett Grady
  • Patent number: 11784794
    Abstract: A system may include a host processor, an interposer having memory elements, a coprocessor mounted on the interposer for accelerating tasks received from the host processor, and an auxiliary chip. The coprocessor, interposer, and auxiliary chip may be part of an integrated circuit package. The memory elements on the interposer may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor. The interposer may be connected to a package substrate of the integrated circuit package using through-silicon vias, such that an active surface of the interposer faces an active surface of the coprocessor. Each logic sector may include one or more data registers that are loaded with configuration data from the memory elements. In some instances, the auxiliary chip may include a secondary memory for storing additional configuration bit streams for configuring the logic sectors of the coprocessor.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: October 10, 2023
    Assignee: INTEL CORPORATION
    Inventors: Peter John McElheny, Aravind Dasu
  • Patent number: 11777503
    Abstract: An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: October 3, 2023
    Assignee: XILINX, INC.
    Inventors: John Edward McGrath, Woon Wong, John O'Dwyer, Paul Newson, Brendan Farley
  • Patent number: 11768798
    Abstract: Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: September 26, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Harold B Noyes, David R. Brown
  • Patent number: 11763043
    Abstract: An apparatus to facilitate enabling late-binding of security features via configuration security controller for accelerator devices is disclosed. The apparatus includes a security controller to initialize as part of a secure boot and attestation chain of trust; receive configuration data for portions of the security controller, the portions comprising components of the security controller capable of re-programming; verify and validate the configuration data to as originating from a secure and trusted source; and responsive to successful verification and validation of the configuration data, re-program the portions of the security controller based on the configuration data.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: September 19, 2023
    Assignee: INTEL CORPORATION
    Inventors: Alpa Trivedi, Steffen Schulz, Patrick Koeberl
  • Patent number: 11756622
    Abstract: In some aspects of the present disclosure, a memory circuit is disclosed. In some aspects, the memory circuit includes a first memory cell including a first resistor; and a first transistor coupled to the first resistor, wherein a first bulk port of the first transistor is biased at a first voltage level; a second memory cell coupled to the first memory cell, the second memory cell including a second resistor; and a second transistor coupled to the second memory cell, wherein a second bulk port of the second transistor is biased at a second voltage level, wherein the second voltage level is less than the first voltage level.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Sheng Chang, Chia-En Huang
  • Patent number: 11748025
    Abstract: A nonvolatile memory device may include: a memory cell array operated by a first voltage, and including a plurality of memory cells; a peripheral circuit operated by the first voltage, and configured to store data in the memory cell array or read data from the memory cell array; an operation recorder operated by a second voltage, and configured to record information on an operation being performed in the nonvolatile memory device; and a control logic operated by the first voltage, and configured to control the peripheral circuit such that the nonvolatile memory device performs an operation corresponding to a command received from an external device, and control the operation recorder to store the information on the operation being performed in the nonvolatile memory device.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: September 5, 2023
    Assignee: SK hynix Inc.
    Inventor: Jee Yul Kim
  • Patent number: 11750189
    Abstract: Devices and/or computer-implemented methods to facilitate a programmable and/or reprogrammable quantum circuit are provided. According to an embodiment, a device can comprise a superconducting coupler device having a superconducting fuse device that is used to alter the coupling of a first quantum computing element and a second quantum computing element.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: September 5, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Elbert Emin Huang, Charles Thomas Rettner, Michael Justin Beckley, Russell A. Budd, Vivekananda P. Adiga, David C. Mckay, Sarah Elizabeth Sheldon
  • Patent number: 11736095
    Abstract: A clock driver circuit for low powered clock driving may include: a multiple phase divider; a buffer supplying at least one of multiple phases to the multiple phase divider at a center frequency that is an integer multiple of an input frequency; and wherein the multiple phase divider and the buffer share a same current from a supply rail.
    Type: Grant
    Filed: November 15, 2022
    Date of Patent: August 22, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel Ramirez, Sudipto Chakraborty
  • Patent number: 11722142
    Abstract: In described examples, a charge pump includes an output, first and second transistors, a control circuit, a multiplexer, and a calibration circuit. The first transistor's drain is coupled to the output. The second transistor's drain is part of a current path separate from a current path that includes the first transistor's drain. The control circuit generates a control signal in response to voltages at the gates of the first and second transistors. First and second inputs of the multiplexer are respectively coupled to sources of the first and second transistors. A control input of the multiplexer is coupled to receive the control signal. A first input of the calibration circuit is coupled to an output of the multiplexer. A second input of the calibration circuit receives a reference voltage. First and second outputs of the calibration circuit are respectively coupled to body terminals of the first and second transistors.
    Type: Grant
    Filed: June 25, 2022
    Date of Patent: August 8, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Jagannathan Venkataraman, Ani Xavier, Shyam Subramanian
  • Patent number: 11709795
    Abstract: Disclosed is an electronic device which includes a main processor, and a systolic array processor, and the systolic array processor includes processing elements, a kernel data memory that provides a kernel data set to the processing elements, a data memory that provides an input data set to the processing elements, and a controller that provides commands to the processing elements. The main processor translates source codes associated with the systolic array processor into commands of the systolic array processor, calculates a switching activity value based on the commands, and stores the translated commands and the switching activity value to a machine learning module, which is based on the systolic array processor.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: July 25, 2023
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventor: Jaehoon Chung
  • Patent number: 11698883
    Abstract: A method of recording tile identifiers in each of a plurality of tiles of a multitile processor is described. Tiles are arranged in columns, each column having a plurality of processing circuits, each processing circuit comprising one or more tiles, wherein a base processing circuit in each column is connected to a set of processing circuit identifier wires. A base value is generated on each of the set of processing circuit identifier wires for the base processing circuit in each column. At the base processing circuit, the base value on the set of processing circuit identifier wires is read and incremented by one. The incremented value is propagated to a next processing circuit in the column, and at the next processing circuit a unique identifier is recorded by concatenating an identifier of the column and the incremented value.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: July 11, 2023
    Assignee: GRAPHCORE LIMITED
    Inventors: Stephen Felix, Jonathan Mangnall
  • Patent number: 11693056
    Abstract: A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: July 4, 2023
    Assignee: Ceremorphic, Inc.
    Inventors: Robert F. Wiser, Shakti Singh, Neelam Surana
  • Patent number: 11694193
    Abstract: The invention presents a solution in which blockchain Transactions are created to implement the functionality of a logic gate. The invention may be implemented on the Bitcoin platform or an alternative blockchain platform. The transaction includes a locking script which comprises instructions selected so as to implement the functionality of a logic gate, such as the XOR gate. When the script is executed (because a second transaction is attempting to spend the output associated with the locking script) the inputs will be processed by the conditional instructions to provide an output of TRUE or FALSE. The inputs are pre-processed by one or more computing agents so that they are evaluated to TRUE or FASLE prior to being used as inputs to the script. The second transaction is transmitted to the blockchain network for validation and, if determined to be valid, it will be written to the blockchain. Validation of the second transaction can be interpreted as a TRUE output.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: July 4, 2023
    Assignee: nChain Licensing AG
    Inventors: Craig Steven Wright, Stephane Savanah
  • Patent number: 11677329
    Abstract: A drive system (300) includes a plurality of power cells (312) supplying power to one or more output phases (A, B, C), each power cell (312) having multiple switching devices (315a-d) incorporating semiconductor switches, and a control system (400) in communication with the plurality of power cells (312) and controlling operation of the plurality of power cells (312), wherein the control system (400) includes a system on chip (410) with one or more central processing units (412, 414) and a field programmable gate array (416) in communication with the one or more central processing units (412, 414).
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: June 13, 2023
    Assignee: Siemens Aktiengesellschaft
    Inventors: Paolo Malapelle, James A. Buckey, Shelby Chun, Alan Wright, Grigoriy Puchkarev
  • Patent number: 11677662
    Abstract: A configurable directional 2D router for Networks on Chips (NOCs) is disclosed. The router, which may be bufferless, is designed for implementation in programmable logic in FPGAs, and achieves theoretical lower bounds on FPGA resource consumption for various applications. The router employs an FPGA router switch design that consumes only one 6-LUT or 8-input ALM logic cell per router per bit of router link width. A NOC comprising a plurality of routers may be configured as a directional 2D torus, or in diverse ways, network sizes and topologies, data widths, routing functions, performance-energy tradeoffs, and other options. The router and NOC enable feasible FPGA implementation of large integrated systems on chips, interconnecting hundreds of client cores over high bandwidth links, including compute and accelerator cores, industry standard IP cores, DRAM/HBM/HMC channels, PCI Express channels, and 10G/25G/40G/100G/400G networks.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: June 13, 2023
    Assignee: Gray Research LLC
    Inventor: Jan Stephen Gray
  • Patent number: 11664806
    Abstract: A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: May 30, 2023
    Assignee: GOWIN SEMICONDUCTOR CORPORATION
    Inventors: Grant Thomas Jennings, Jinghui Zhu
  • Patent number: 11665979
    Abstract: A method for providing a magnetic device and the magnetic device so provided are described. The magnetic device includes a magnetic layer having a surface. In some aspects, the magnetic layer is a free layer, a reference layer, or a top layer thereof. A tunneling barrier layer is deposited on the magnetic layer. At least a portion of the tunneling barrier layer adjacent to the magnetic layer is deposited at a deposition angle of at least thirty degrees from a normal to the surface of the magnetic layer. In some aspects, the deposition angle is at least fifty degrees.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: May 30, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaewoo Jeong, Mahesh G. Samant, Yari Ferrante, Panagiotis Charilaos Filippou, Chirag Garg, Stuart Stephen Papworth Parkin
  • Patent number: 11657868
    Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: May 23, 2023
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, Ming Li
  • Patent number: 11646063
    Abstract: It is an object of the disclosed technique to provide a novel method and system for shared concurrent access to a memory cell. In accordance with the disclosed technique, there is thus provided a system for shared concurrent access to a memory cell, which includes at least one shared memory cell, an evaluator and a plurality of processing agents coupled to the input of the evaluator. The evaluator is further coupled with the at least one memory cell. The evaluator is configured to evaluate an expression for performing multiple concurrent composite assignments on the at least one shared memory cell. The evaluator further allows each of the plurality of processing agents to perform concurrent composite assignments on the at least one shared memory cell. The composite assignments do not include a read operation of the at least one shared memory cell by the plurality of processing agents.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: May 9, 2023
    Assignee: JERUSALEM COLLEGE OF TECHNOLOGY
    Inventors: Shimon Mizrahi, Raphael Berakhael Yehezkael, Ruben Attia, Erez Lax, Devora Berlowitz, Moshe Goldstein, David Dayan
  • Patent number: 11640835
    Abstract: A memory device with built-in flexible redundancy is provided according to various aspects of the present disclosure. In certain aspects, a memory device includes a first sense amplifier, a second sense amplifier, a first comparator, a second comparator, a reference circuit, and a logic gate. During a redundant read operation, the first sense amplifier, the first comparator, and the reference circuit are used to read one copy of a redundant bit stored in the memory device, and the second sense amplifier, the second comparator, and the reference circuit are used to read another copy of the redundant bit stored in the memory device. The logic gate may then determine a bit value based on the bit values of the read copies of the redundant bit (e.g., determine a bit value of one if the bit value of at least one of the read copies of the redundant bit is one).
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: May 2, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Anil Chowdary Kota, Hochul Lee
  • Patent number: 11637556
    Abstract: A programmable integrated circuit device able to be selectively programmed to perform one or more logic functions includes multiple configurable logic blocks (“LBs”), routing fabric, and a nonvolatile memory (“NVM”). While the configurable LBs are able to be selectively programmed to perform one or more logic functions, the routing fabric selectively routes information between the configurable LBs and input/output ports based on a routing configuration signals. The NVM, such as magnetoresistive random access memory (“MRAM”), phase-change memory, or ferroelectric RAM (“FeRAM”), is flexibly organized to contain a configuration NVM storage and a user NVM storage, wherein the user NVM storage is a word addressable memory capable of facilitating random memory access.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: April 25, 2023
    Assignee: GOWIN SEMICONDUCTOR CORPORATION
    Inventor: Jinghui Zhu
  • Patent number: 11621051
    Abstract: A device includes a first switch, a first irreversibly programmable memory point, and a second irreversibly programmable memory point coupled in parallel with the first irreversibly programmable memory point. The first switch and the parallel combination of the first and second irreversibly programmable memory points are coupled in series between a first node and a second node.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: April 4, 2023
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Stephane Denorme, Philippe Candelier, Joel Damiens, Fabrice Marinet
  • Patent number: 11599498
    Abstract: A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying operation of a first kernel of a first subset of the DPEs of the array of DPEs, reconfiguration of a second subset of the DPEs of the array of DPEs.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: March 7, 2023
    Assignee: XILINX, INC.
    Inventors: Juan J. Noguera Serra, Sneha Bhalchandra Date, Jan Langer, Baris Ozgul, Goran Hk Bilski
  • Patent number: 11600310
    Abstract: A lateral transfer path within an adjustable-width signaling interface of an integrated circuit component is formed by a chain of logic segments that may be intercoupled in different groups to effect the lateral data transfer required in different interface width configurations, avoiding the need for a dedicated transfer path per width configuration and thereby substantially reducing number of interconnects (and thus the area) required to implement the lateral transfer structure.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: March 7, 2023
    Assignee: Rambus Inc.
    Inventor: Frederick A. Ware
  • Patent number: 11593022
    Abstract: Embodiments of the present invention provide a system, a method, and an electronic device for the cloud-based configuration of FPGA configuration data. The system includes a control module internal to an FPGA and a storage module external to the FPGA. The storage module is configured to store configuration data transmitted from a cloud, and the control module is configured to retrieve the configuration data from the storage module and to configure a corresponding processing unit of the FPGA according to the configuration data. In the embodiments of the present invention, the control module internal to the FPGA is provided, and configuration data is retrieved from the storage module external to the FPGA to configure the corresponding processing unit of the FPGA. Accordingly, during FPGA data migration, the configuration data stored in the external storage module can be directly migrated by using a general data migration method, thereby implementing live migration of FPGA data.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: February 28, 2023
    Assignee: ALIBABA GROUP HOLDING LIMITED
    Inventors: Xiang Liu, Xin Long
  • Patent number: 11579894
    Abstract: A device includes a plurality of reconfigurable resources, a bus, and a configurator. The bus interconnects the plurality of reconfigurable resources. The configurator is configured to deterministically compute a segmented interconnect configuration for the bus based on operational parameters associated with the device and operational constraints associated with program modules to be executed by the plurality of reconfigurable resources.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: February 14, 2023
    Assignee: Nokia Solutions and Networks Oy
    Inventors: Andrea Enrici, Bogdan Uscumlic
  • Patent number: 11573623
    Abstract: Described herein are mechanisms and methods for blocking the propagation of signals to Integrated Circuit (IC) components that have been power gated, rather than simply suffering from leakage through signals that might not be parked in a low state. In some embodiments, switches that block the flow of current in such signals may enable turning off power to any IC component and not just to circuits on an IC component that make sole use of protocols that are friendly to power gating. This may advantageously increase power savings, by permitting more portions of a system in an idle state to be power gated, or by reducing or eliminating leakage in signals on boundaries of blocks being power gated, or both.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: February 7, 2023
    Assignee: Shenzhen Chipuller Chip Technology Co., LTD
    Inventor: Mathew Salazar
  • Patent number: 11569820
    Abstract: An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: January 31, 2023
    Assignee: XILINX, INC.
    Inventors: John Edward McGrath, Woon Wong, John O'Dwyer, Paul Newson, Brendan Farley
  • Patent number: 11567780
    Abstract: The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: January 31, 2023
    Assignee: Movidius Limited
    Inventors: David Moloney, Cormac Brick, Ovidiu Andrei Vesa, Brendan Barry
  • Patent number: 11563435
    Abstract: An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: January 24, 2023
    Assignee: XILINX, INC.
    Inventors: John Edward McGrath, Woon Wong, John O'Dwyer, Paul Newson, Brendan Farley
  • Patent number: 11550494
    Abstract: A method provides the capability to maintain a configuration settings data image stored by a non-volatile memory device. The configuration settings data image can be multiple times programmed (MTP) without sacrificing reliability of the semiconductor device in the event of spurious power fluctuations, intermittent or bad memory storage blocks storing the configuration settings data image.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: January 10, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Shuo-Nan Hung
  • Patent number: 11544208
    Abstract: A wave pipeline includes a data path and a clock path. The data path includes a plurality of wave pipeline data stages and a synchronous data stage. The synchronous data stage includes a first data latch to latch the data from the synchronous data stage. The synchronous data stage is between a first wave pipeline data stage of the plurality of wave pipeline data stages and a second wave pipeline data stage of the plurality of wave pipeline data stages. The clock path corresponds to the plurality of wave pipeline data stages. The first data latch latches the data from the synchronous data stage in response to a clock signal on the clock path.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: January 3, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kaveh Shakeri, Ali Feiz Zarrin Ghalam
  • Patent number: 11531551
    Abstract: To preferentially execute an instruction with higher priority in a case of the CNC being unable to respond due to being an unresponsive timing, load on the bus or the like. A PLC device includes: a special instruction control unit that sets a priority degree indicating a degree of priority for executing predetermined processing to a special instruction for performing the predetermined processing in a control device that controls an industrial machine, and transmits the special instruction in which the priority degree is set to the control device; an instruction storage determining unit that determines whether or not to queue the special instruction according to an operation state of the control device; and an instruction storage unit that sequentially stores the special instruction received, on the basis of a determination result of the instruction storage determining unit.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: December 20, 2022
    Assignee: FANUC CORPORATION
    Inventor: Nao Onose
  • Patent number: 11533187
    Abstract: A device identification is generated for a programmable device. A security key is generated to protect a content of the programmable device. A device birth certificate is generated with the device identification and the security key. The programmable device is programmed with the device birth certificate at time of manufacture of the programmable device.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: December 20, 2022
    Assignee: Data I/O Corporation
    Inventors: Rajeev Gulati, Anthony Ambrose
  • Patent number: 11509312
    Abstract: An apparatus and a method for synchronizing output clock signals across a plurality of phase-locked loops (PLLs). The apparatus coupled within each PLL comprises: a local counter configured to provide a count when receiving a reference clock signal; a comparator configured to compare the count from the local counter with a predetermined or preconfigured value; wherein a multiplexor connected to the local counter and counters of adjacent PLLs, configured to select the count from the local counter or a count from the counters of the adjacent PLLs; wherein the selected count from the multiplexor is incremented and directed to the local counter; wherein an output clock divider enable is asserted to the PLL to start an output clock divider to generate the output clock signal when the count from the local counter reaches the predetermined or preconfigured value.
    Type: Grant
    Filed: December 24, 2021
    Date of Patent: November 22, 2022
    Assignee: SKYECHIP SDN BHD
    Inventors: Chee Hak Teh, Soon Chieh Lim, Ging Yeon Mark Wong, How Hwan Wong
  • Patent number: 11494520
    Abstract: An embodiment of an electronic processing system may include a processor, persistent storage media communicatively coupled to the processor, a reconfigurable device communicatively coupled to the processor over a physically isolated trusted communication channel, a secure provisioner communicatively coupled to the processor and the reconfigurable device to provision a secure storage area and to securely store a remotely generated bitstream security key in the provisioned secure storage area, and a device configurer to configure the reconfigurable device with a remotely generated bitstream and the remotely generated bitstream security key. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: November 8, 2022
    Assignee: Intel Corporation
    Inventors: Changzheng Wei, Weigang Li, Cunming Liang
  • Patent number: 11495289
    Abstract: Connection weight coefficients to be used in a neural network computation are stored in a memory array. A word line drive circuit drives a word line corresponding to input data of a neural network. A column selection circuit connects to a computation circuit bit lines to which a connection weight coefficient to be computed is connected. The computation circuit determines the sum of cell currents flowing in the bit lines. A result of the determination made by the computation circuit is stored in an output holding circuit, and is set as an input of a neural network in the next layer, to the word line drive circuit. A control circuit instructs the word line drive circuit and the column selection circuit to select the word line and the bit line to be used in the neural network computation, based on information held in a network configuration information holding circuit.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: November 8, 2022
    Assignee: PANASONIC HOLDINGS CORPORATION
    Inventors: Yuriko Hayata, Kazuyuki Kouno, Masayoshi Nakayama, Reiji Mochida, Takashi Ono, Hitoshi Suwa