Having Details Of Setting Or Programming Of Interconnections Or Logic Functions Patents (Class 326/38)
  • Patent number: 10810119
    Abstract: A process for wear-leveling in a memory subsystem where references to invalidated chunks and a write count for each of the invalidated chunks of a memory subsystem are received by a wear-leveling manager. The wear-leveling manager orders the received references to the invalidated chunks of the memory subsystem in a tracking structure based on the write count of each of the invalidated chunks, and provides a reference to at least one of the invalidated chunks based on the ordering from the tracking structure to a write scheduler to service a write request, wherein the memory subsystem is wear-leveled by biasing the order of the invalidated chunks to prioritize low write count chunks.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: October 20, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Justin Eno, Samuel E. Bradshaw
  • Patent number: 10804885
    Abstract: A standard cell layout for a data storage circuit includes a latch and an initialization circuit. Metallization levels over the standard cell layout support circuit interconnections. At least one metallization level is provided for metal programming of an initialization configuration of the data storage circuit. The at least one metallization level may have: a first wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in reset device (assertion of an initialization signal causing the data storage circuit data output to be reset), or a second wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in set device (assertion of the initialization signal causing the data storage circuit data output to be set).
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: October 13, 2020
    Assignee: STMicroelectronics SA
    Inventors: Sylvain Engels, Alain Aurand, Etienne Maurin
  • Patent number: 10797705
    Abstract: A circuit device includes first and second output signal lines from which first and second output signals constituting differential output signals are output, and first to n-th output drivers coupled to the first and second output signal lines. In a first mode, i number of output drivers of the first to n-th output drivers drive the first and second output signal lines based on first and second input signals constituting differential input signals. In a second mode, j number of output drivers of the first to n-th output drivers drive the first and second output signal lines based on the first and second input signals.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: October 6, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Fumikazu Komatsu, Minoru Kozaki
  • Patent number: 10778228
    Abstract: An integrated circuit including an FPGA, configurable to process data via a plurality of data processing operations, and an ASIC, electrically coupled to logic circuitry of the FPGA via switch interconnect network thereof. In one embodiment, the ASIC includes a plurality of circuit blocks, each circuit block configurable to process data via a data processing operation, and selection circuitry, coupled to the logic circuitry of the FPGA and the plurality of circuit blocks of the ASIC, configurable to connect one or more of the plurality of circuit blocks of the ASIC and the logic circuitry of the FPGA into a first circuit configuration to perform a first data processing operation, and in situ, connect one or more of the plurality of circuit blocks of the ASIC and the logic circuitry of the FPGA into a second circuit configuration to perform a second data processing operation.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: September 15, 2020
    Assignee: Flex Logix Technologies, Inc.
    Inventor: Valentin Ossman
  • Patent number: 10778162
    Abstract: Systems and methods for sensing an analog signal through digital input/output (I/O) pins are provided. Aspects include an analog to digital (ADC) circuit configured to generate a digital signal based on observations of the analog signal obtained from an analog circuit, where the ADC circuit includes a difference amplifier, a comparator, a divideby2 counter and two AND gates. Aspects also include a controller including a pin configured to receive the digital signal. The controller is configured to count pulses within the digital signal and determine values corresponding to the analog signal based on the counted pulses.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: September 15, 2020
    Assignee: ROSEMOUNT AEROSPACE, INC.
    Inventors: Rajkumar Sengodan, Saravanan Munusamy
  • Patent number: 10778225
    Abstract: An integrated circuit system includes: a storage element which stores in advance a plurality of pieces of circuit information and startup control circuit information used to configure a startup control logic circuit for selecting circuit information that has not failed in configuring a logic circuit; and an integrated circuit which, at the time of startup or when configuration of the logic circuit based on any of the plurality of pieces of circuit information has failed, configures the startup control logic circuit by reading the startup control circuit information from the storage element, causes the configured startup control logic circuit to select the circuit information that has not failed in configuring the logic circuit, reads the circuit information selected by the startup control logic circuit from the storage element, and configures the logic circuit according to the circuit information.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: September 15, 2020
    Assignee: NEC CORPORATION
    Inventor: Katsuhisa Ikeuchi
  • Patent number: 10770398
    Abstract: A semiconductor device assembly that includes a second side of an interposer being connected to a first side of a substrate. A plurality of interconnects may be connected to a second side of the substrate. First and second semiconductor devices are connected directly to the first side of the interposer. The interposer is configured to enable the first semiconductor device and the second semiconductor device to communicate with each other through the interposer. The interposer may be a silicon interposer that includes complementary metal-oxide-semiconductor circuits. The first semiconductor device may be a processing unit and the second semiconductor device may be a memory device, which may be a high bandwidth memory device. A method of making a semiconductor device assembly includes attaching both a memory device and a processing unit directly to a first side of an interposer and connecting a second side of the interposer to a substrate.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: September 8, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Chan H. Yoo, Owen R. Fay
  • Patent number: 10768231
    Abstract: “Shoot-through” timing failures in a scan chain of a defective semiconductor integrated circuit corrupt test pattern data used to perform failure analysis. Methods and procedures are provided to detect “shoot-through” conditions, determine the number of shoot-through scan cells, and to determine the location of the shoot-through cells within a scan chain. Reset test pattern results can be analyzed to identify candidate locations of shoot-through cells and when combined with candidate cell locations from analysis of physical clock distribution trees and potential clock-skew issues, the exact location of all shoot-through cells can be determined. Methods are also provided to use shoot-through cell locations to identify the defective clock net containing the physical defect causing the clock skew conditions needed to produce shoot-through timing failures.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: September 8, 2020
    Assignee: TESEDA CORPORATION
    Inventor: Theodore Clifton Bernard
  • Patent number: 10768244
    Abstract: A power loss protection integrated circuit includes a storage capacitor terminal (STR), an autonomous capacitor health check circuit, and a capacitor fault terminal (CF). The capacitor health check circuit autonomously performs periodic capacitor check operations. In a check operation, current is sinked from the STR terminal for a predetermined time and in a predetermined way. If during this time the voltage on the STR terminal STR drops below a predetermined voltage, then a digital signal CF is asserted onto the CF terminal. Immediately following each capacitor check, a charging voltage is driven onto the STR terminal to recharge the external capacitors coupled to the STR terminal. In one example, the integrated circuit further includes a current switch circuit (eFuse) and a buck/boost controller. The capacitor health check circuit is only enabled during normal mode operation of the integrated circuit, and the check circuit disables boost operation during capacitor checks.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: September 8, 2020
    Assignee: Active-Semi, Inc.
    Inventors: John H. Carpenter, Jr., Brett E. Smith
  • Patent number: 10761503
    Abstract: A device programming system, and a method of operation thereof, includes: a field programmable gate array unit configured using a programming driver retrieved based on a device type of a first programmable device; and a second programmable device and the first programmable device configured simultaneously using a master image and the field programmable gate array unit.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: September 1, 2020
    Assignee: Data I/O Corporation
    Inventors: Andrew B. Caley, Derek P. Steffey
  • Patent number: 10763862
    Abstract: Examples described herein provide for a boundary logic interface (BLI) to a programmable logic region in an integrated circuit (IC), and methods for operating such IC. An example IC includes a programmable logic region and boundary logic interfaces. The programmable logic region includes columns of interconnect elements disposed between columns of logic elements. The boundary logic interfaces are at respective ends of and communicatively connected to the columns of interconnect elements. The boundary logic interfaces are outside of a boundary of the programmable logic region. A first boundary logic interface (BLI) of the boundary logic interfaces is configured to be communicatively connected to an exterior circuit. The first BLI includes an interface configured to communicate a signal between the exterior circuit and the programmable logic region.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: September 1, 2020
    Assignee: XILINX, INC.
    Inventors: Rafael C. Camarota, Ui S. Han, Weiguang Lu
  • Patent number: 10755019
    Abstract: In accordance with a first aspect of the present disclosure, a method of designing an integrated circuit is conceived, comprising: placing integrated circuit cells that include supply pins in a plurality of predefined rows; determining blocked areas for supply pin extensions; extending the supply pins outside said blocked areas. A corresponding integrated circuit is also provided.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: August 25, 2020
    Assignee: NXP B.V.
    Inventors: Sven Trester, Claus Dieter Grzyb
  • Patent number: 10754666
    Abstract: A device comprising: at least one partially reconfigurable FPGA; a Network-on-Chip (NoC) comprised in the FPGA; and at least one area on the at least one FPGA operable to house a hardware micro-service (HMS); wherein an HMS image may be loaded onto the area of the at least one FPGA via partial reconfiguration to form a new HMS, and the NoC is operable to forward information to and from the new HMS without the NoC being reloaded.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: August 25, 2020
    Assignee: Rad Data Communications Ltd.
    Inventors: Yzhak Sorani, Yaakov Stein
  • Patent number: 10754817
    Abstract: An information processing apparatus having a reconfigurable circuit capable of rewriting a logic circuit includes, a process determination circuit that determines which of a plurality of processes is to be executed, a standby buffer circuit that holds process data to be used in a process waiting for execution among processes determined by the process determination circuit, and a rewrite control circuit that rewrites the current logic circuit written in the reconfigurable circuit to a logic circuit that executes one of the plurality of processes waiting for execution using each of a plurality of process data held in the standby buffer circuit when the amount of process data held in the standby buffer circuit exceeds a first predetermined amount.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: August 25, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Toshiyuki Ichiba
  • Patent number: 10740435
    Abstract: Provided is a programmable logic integrated circuit wherein even if a failure occurs in any resistance-variable element, remedy would be possible and hence the improvement of reliability has been achieved. In a programmable logic integrated circuit comprising resistance-variable elements, when the states of the resistance-variable elements are to be changed according to externally inputted configuration information, a control means uses a reading means to read the states of the respective resistance-variable elements, and then uses a writing means to change only the states of resistance-changing elements that are different from a state indicated by the configuration information.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: August 11, 2020
    Assignee: NEC CORPORATION
    Inventors: Noboru Sakimura, Yukihide Tsuji, Ayuka Tada, Xu Bai, Makoto Miyamura, Ryusuke Nebashi
  • Patent number: 10735002
    Abstract: A programmable semiconductor device capable of being selectively programmed to perform one or more logic functions includes a first region, second region, first regional power control (“RPC”), and second-to-first power control connection. The first region, in one embodiment, contains first configurable logic blocks (“CLBs”) able to be selectively programmed to perform a first logic function. The second region includes a group of second CLBs configured to be selectively programmed to perform a second logic function. The first RPC port or inter-chip port which is coupled between the first and second regions facilitates dynamic power supply to the first region in response to the data in the second region. The second-to-first power control connection is used to allow the second region to facilitate and/or control power to the first region.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: August 4, 2020
    Assignee: Gowin Semiconductor Corporation
    Inventors: Jinghui Zhu, Jianhua Liu, Ning Song
  • Patent number: 10735020
    Abstract: A voltage detector circuit including a ladder selector that includes a first node, a second node and a selector node. The voltage detector circuit also includes a first resistive ladder that includes a first string of resistors coupled between a sensing input node and the first node of the ladder selector and a first set of transistors. An input node of each transistor in the first set of transistors is coupled to a respective intermediate node between two resistors in a subset of resistors in the first string of resistors and an output node of each transistor in the first set of transistors is coupled to a sensing output node. The voltage detector circuit also includes a second resistive ladder that includes a second string of resistors coupled between the sensing input node and the second node of the ladder selector and a second set of transistors.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: August 4, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Santhosh Kumar Gowdhaman, Divya Kaur
  • Patent number: 10725873
    Abstract: The present techniques generally relate to a method of monitoring for a fault event in a lockstep processing system having a plurality of cores configured to operate in lockstep, the method having: power gating, for a period of time, a subset of cores of the plurality of cores from a first power source and providing power to the subset of cores from a second power source for the period of time; processing, at each of the cores of the plurality of cores, one or more instructions; providing an output from each core of the plurality of cores to error detection circuitry to monitor for the fault event, the output from each core based on or in response to processing the one or more instructions during the period of time.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: July 28, 2020
    Assignee: Arm Limited
    Inventors: Milosch Meriac, Shidhartha Das
  • Patent number: 10720926
    Abstract: An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: July 21, 2020
    Assignee: XILINX, INC.
    Inventors: John McGrath, Woon Wong, John O'Dwyer, Paul Newson, Brendan Farley
  • Patent number: 10719470
    Abstract: Techniques are disclosed for data manipulation. Data is obtained from a first switching element where the first switching element is controlled by a first circular buffer. Data is sent to a second switching element where the second switching element is controlled by a second circular buffer. Data is controlled by a third switching element that is controlled by a third circular buffer. The third switching element hierarchically controls the first switching element and the second switching element. Data is routed through a fourth switching element that is controlled by a fourth circular buffer. The circular buffers are statically scheduled. The obtaining data from a first switching element and the sending the data to a second switching element includes a direct memory access (DMA). The switching elements can operate as a master controller or as a slave device. The switching elements can comprise clusters within an asynchronous reconfigurable fabric.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: July 21, 2020
    Assignee: Wave Computing, Inc.
    Inventor: Christopher John Nicol
  • Patent number: 10719079
    Abstract: A hybrid of initial time consuming phase of a Single Directional Dijkstra's Algorithm is embodied on an unclocked CMOS logic chip using a parallelized approach with Asynchronous Digital Logic (ADL). The chip includes a a plurality of addressable configurable cells arranged as a multidimensional orthogonal array. The cell array only executes mathematical operations based on a communication between immediately adjacent cells.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: July 21, 2020
    Assignee: NOKOMIS, INC.
    Inventor: T. Eric Chornenky
  • Patent number: 10715148
    Abstract: Various implementations described herein are directed to an integrated circuit with logic circuitry having one or more components. The integrated circuit may include performance sensing circuitry that provides a performance sensing output associated with detecting variation of switching delays of the one or more components forming the logic circuitry. The integrated circuit may include transient sensing circuitry that receives the performance sensing output and provides a transient sensing output for determining stability of operating conditions of the performance sensing circuitry during one or more sampling periods. The transient sensing circuitry may use a finite state machine (FSM) to sense and classify changes in temporal behavior of the transient sensing output.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: July 14, 2020
    Assignee: Arm Limited
    Inventors: Rainer Herberholz, Amit Chhabra, Yannis Jallamion-Grive
  • Patent number: 10714207
    Abstract: A scannable-latch random access memory (SLRAM) is disclosed. The SLRAM includes two rows of memory cells. The SLRAM includes a functional data input, a scan data input, a first and second functional data outputs, a scan data output, and a scan enable. The functional data input is connected to a first memory cell in a first and second rows of memory cells. The scan data input is connected to the first memory cell in the first or second row of memory cells. The first and second functional data outputs are connected to a last memory cell in the first and second row of memory cells, respectively. The scan data output is connected to the last memory cell in the first or second row of memory cells. The scan enable allows data to be output from the scan data output or the first and second functional data outputs.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 14, 2020
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: David D Moser, Michael J. Frack, Jason F. Ross, Kevin Linger
  • Patent number: 10708036
    Abstract: An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: July 7, 2020
    Assignee: Rambus Inc.
    Inventor: Jared L. Zerbe
  • Patent number: 10705995
    Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: July 7, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Asif Khan, Islam Mohamed Hatem Abdulfattah Mohamed Atta, Robert Michael Johnson, Mark Bradley Davis, Christopher Joseph Pettey, Nafea Bshara, Erez Izenberg
  • Patent number: 10691856
    Abstract: A computer-implemented design flow can include, within a circuit design for an integrated circuit, determining a portion of the circuit design that is a candidate for implementation as a runtime customizable circuit and determining implementation options for the runtime customizable circuit. The design flow can also include generating, using computer hardware, a description of the circuit design using the runtime customizable circuit to implement the portion of the circuit design and generating, using the computer hardware, program code for an embedded processor coupled to an implementation of the runtime customizable circuit within the integrated circuit. The program code is usable by the embedded processor to parameterize the runtime customizable circuit to create a specific instance of the runtime customizable circuit.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: June 23, 2020
    Assignee: Xilinx, Inc.
    Inventors: Patrick Lysaght, Graham F. Schelle
  • Patent number: 10693469
    Abstract: An integrated circuit comprising a plurality of multiply-accumulator circuitry interconnected in a concatenation architecture. Each multiply-accumulator circuitry includes first and second MAC circuits and a load-store register. The first MAC circuit includes a multiplier to multiply first data by a first multiplier weight data and generate a first product data, and an accumulator to add first input data and the first product data to generate first sum data. The second MAC circuit includes a multiplier to multiply second data by a second multiplier weight data and generate a second product data, and an accumulator, coupled to the multiplier of the second MAC circuit and the accumulator of the first MAC circuit, to add the first sum data and the second product data to generate second sum data. The load-store register is coupled to the accumulator of the second MAC circuit to temporarily store the second sum data.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: June 23, 2020
    Assignee: Flex Logic Technologies, Inc.
    Inventor: Cheng C. Wang
  • Patent number: 10684983
    Abstract: Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: June 16, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Harold B Noyes, David R. Brown
  • Patent number: 10680615
    Abstract: A circuit for configuring function blocks of an integrated circuit device is described. The circuit comprises a processing system; a peripheral interface bus coupled to the processing system; and a function block coupled to the peripheral interface bus, the function block having programming registers and a function block core; wherein the programming registers store data determining a functionality of the function block core and comprise programming control registers enabling a configuration of the function block core using the data. A method of configuring function blocks of an integrated circuit device is also described.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: June 9, 2020
    Assignee: XILINX, INC.
    Inventors: David P. Schultz, Ian A. Swarbrick, Nagendra Donepudi
  • Patent number: 10672757
    Abstract: A multiphase parallel digital current (DC) to DC converter (DCDC) circuit includes a loop operational amplifier (EA) unit, N output-stage circuit units, and M drive units, where a drive unit corresponds to at least one output-stage circuit unit including a comparator (COMP) and a power stage circuit, an output end of the loop operational amplifier EA unit is connected to an input end of the drive unit, an output end of the drive unit is connected to an input end of a COMP in a corresponding output-stage circuit unit, and an output end of the COMP is connected to an input end of a power stage circuit in the same output-stage circuit unit, and an input end of the loop operational amplifier EA unit is connected to output ends of all the power stage circuits.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: June 2, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jiake Wang, Yue Chen, Qiang Xie
  • Patent number: 10671429
    Abstract: An information processing apparatus includes: a reconfiguration device which can change a circuit configuration through a dynamic partial reconfiguration; and a controller which controls a circuit arrangement in the reconfiguration device, in which when a processing circuit related to a new task is arranged in the reconfiguration device, the controller determines a circuit assignment of a processing circuit related to an existing task in execution and the processing circuit related to the new task with respect to an area as a result of combining an area used for the processing circuit related to the existing task in execution and a space area, based on a predicted end time of the processing of the respective tasks, and arranges the processing circuits related to the respective tasks in the reconfiguration device in accordance with the determined circuit assignment.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: June 2, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Kentaro Katayama
  • Patent number: 10673440
    Abstract: Examples generally relate a programmable device having a unified programmable computational memory (PCM) and configuration network. In an example, a programmable device includes a die that includes a PCM integrated circuit having a PCM tile. The PCM tile includes a configuration memory (CM) and combinational logic (CL). The CM is capable of storing configuration data received via a node in the PCM tile. The CL is configured to receive internal control signal(s) and first and second input signals and to output a result signal. The CL is capable of outputting the result signal resulting from a logic function that is responsive to the internal control signal(s) and a signal of a group of signals including the first and second input signals. The CL is configured to receive the first input signal via the node in the PCM tile.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: June 2, 2020
    Assignee: XILINX, INC.
    Inventor: Rafael C. Camarota
  • Patent number: 10666266
    Abstract: Apparatus and method relate generally to a configuration engine. In one such configuration engine for a programmable circuit, a frame counter includes a cascade of frame incrementer circuits associated with columns for a row of circuit blocks. Each frame incrementer circuit is configured to provide frame sums for frames associated with the circuit blocks. The frame counter is configured to sequentially add the frame sums for the columns to provide corresponding frame totals respectively for circuit types of the circuit blocks. A termination circuit is configured to multiplex the frame totals onto a data bus. A row controller is configured to initiate the frame counter and to selectively access the frame totals provided to the data bus.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: May 26, 2020
    Assignee: XILINX, INC.
    Inventors: Karthy Rajasekharan, Weiguang Lu
  • Patent number: 10656915
    Abstract: In some example embodiments a logical block comprising twelve inputs and two six-input lookup tables (LUTs) is provided, wherein four of the twelve inputs are provided as inputs to both of the six-input lookup tables. This configuration supports efficient field programmable gate array (FPGA) implementation of multipliers. Each six-input LUT comprises two five-input lookup tables (LUT5s) that are used to form Booth encoding multiplier building blocks. The five inputs to each LUT5 are two bits from a multiplier and three Booth-encoded bits from a multiplicand. By assembling building blocks, multipliers of arbitrary size may be formed.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: May 19, 2020
    Assignee: Achronix Semiconductor Corporation
    Inventors: Daniel Pugh, Raymond Nijssen
  • Patent number: 10657216
    Abstract: The disclosed technology concerns methods, apparatus, and systems for designing and generating networks-on-chip (“NoCs”), as well as to hardware architectures for implementing such NoCs. The disclosed NoCs can be used, for instance, to interconnect cores of a chip multiprocessor (aka a “multi-core processor”). In one example implementation, a wire-based routerless NoC design is disclosed that uses deterministically specified wire loops to connect the cores of the chip multiprocessor. The disclosed technology also comprises network interface architectures for use in an NoC. For example, a core can be equipped with a low-area-cost interface that is deadlock-free, uses buffering sharing, and provides low latency.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: May 19, 2020
    Assignee: Oregon State University
    Inventors: Lizhong Chen, Fawaz M. Alazemi, Bella Bose
  • Patent number: 10649731
    Abstract: Integrated circuits with specialized processing blocks are provided. A specialized processing block may include one real addition stage and one real multiplier stage. The multiplier stage may simultaneously feed its output to the addition stage and directly to an adjacent specialized processing block. The addition stage may also produce sum and difference outputs in parallel. A group of four such specialized processing blocks may be connected in a chain to implement a radix-2 fast Fourier transform (FFT) butterfly. Multiple radix-2 butterflies may be stacked to form yet higher order radix butterflies. If desired, the specialized processing block may also be used to implement a complex multiply operation. Three or four specialized processing blocks may be chained together and along with one or more adders outside the specialized processing blocks, real and imaginary portions of a complex product can be generated.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: May 12, 2020
    Assignee: Altera Corporation
    Inventor: Martin Langhammer
  • Patent number: 10651853
    Abstract: A device includes a platform implemented in programmable circuitry of the device. The platform is configured to communicate with a host data processing system. The device includes a first partial reconfiguration region implemented in the programmable circuitry and coupled to the platform. The first partial reconfiguration region is reserved for implementing user-specified circuitry. The device includes timing insulation circuitry implemented in the programmable circuitry and configured to isolate timing of signals passing between the platform and the first partial reconfiguration region.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: May 12, 2020
    Assignee: Xilinx, Inc.
    Inventors: Raymond Kong, Hao Yu
  • Patent number: 10642541
    Abstract: A circuit that includes a plurality of array cores, each array core of the plurality of array cores comprising: a plurality of distinct data processing circuits; and a data queue register file; a plurality of border cores, each border core of the plurality of border cores comprising: at least a register file, wherein: [i] at least a subset of the plurality of border cores encompasses a periphery of a first subset of the plurality of array cores; and [ii] a combination of the plurality of array cores and the plurality of border cores define an integrated circuit array.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: May 5, 2020
    Assignee: quadric.io, Inc.
    Inventors: Nigel Drego, Aman Sikka, Mrinalini Ravichandran, Ananth Durbha, Robert Daniel Firu, Veerbhan Kheterpal
  • Patent number: 10635631
    Abstract: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: April 28, 2020
    Assignee: Altera Corporation
    Inventors: Michael D. Hutton, Anargyros Krikelis
  • Patent number: 10628064
    Abstract: In some examples of the disclosure, a parameter override mechanism may include a variable length configuration data table with entries for specific models of memory devices. The configuration data table entries may include override parameters for different memory devices and may be dynamically updated with new entries and modifications of existing entries. The parameter override mechanism may be configured to automatically detect a model of memory device and select a corresponding configuration data table entry based on the detected model of memory device or restrict the use of a configuration data table entry based on the detected model of memory device.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: April 21, 2020
    Assignee: Qualcomm Incorporated
    Inventors: James Hudson, Behnam Dashtipour
  • Patent number: 10628356
    Abstract: A transmission apparatus includes a logic circuit for performing a predetermined process, and outputting a logic output signal depending on the process, an open-drain signal generation circuit, connectable at an input terminal to the logic circuit and at an output terminal to a pull-up resistor, and a transmission path failure determination circuit for determining whether there is a failure in a transmission path which transmits a signal outputted from the logic circuit via the open-drain signal generation circuit, wherein the transmission path failure determination circuit includes an edge waveform information obtaining circuit for obtaining edge waveform information indicating a waveform of at least one of a rising edge and a falling edge of an application signal, and a failure determination circuit for determining whether the edge waveform information satisfies a predetermined condition, and outputting a failure signal indicating that there is a failure in the transmission path.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: April 21, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Kenichi Miyama, Masato Hori
  • Patent number: 10628169
    Abstract: The present invention is directed to a method for booting a system-on-chip (SoC) including the steps of directly executing a boot software from an on-chip magnetic random access memory (MRAM) residing on a same semiconductor as the SoC; storing an operating system (OS) software and an application software on an external MRAM; directly executing the operating system software from the external MRAM by the SoC without loading the operating system into a volatile memory; directly executing the application software from the external MRAM by the SoC, wherein the external MRAM is coupled to the SoC and is configured for permanently storing the operating system software and the application software.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: April 21, 2020
    Assignee: Avalanche Technology, Inc.
    Inventors: Ngon Van Le, Ravishankar Tadepalli
  • Patent number: 10627798
    Abstract: In an embodiment of the invention, an apparatus comprises: a non-volatile memory device; a complex programmable logic device (CPLD) coupled to the non-volatile memory device; a field programmable gate array (FPGA) coupled to the CPLD; and a host coupled to the FPGA; wherein the apparatus triggers a switch of an FPGA image in the FPGA to another FPGA image. In another embodiment of the invention, a method comprises: triggering, by an apparatus, a switch of an FPGA image in a field programmable gate array (FPGA) to another FPGA image; herein the apparatus comprises: a non-volatile memory device; a complex programmable logic device (CPLD) coupled to the non-volatile memory device; the field programmable gate array (FPGA) coupled to the CPLD; and a host coupled to the FPGA.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 21, 2020
    Assignee: BiTMICRO Networks, Inc.
    Inventors: Federico Sambilay, Jr., Bharadwaj Pudipeddi, Richard A. Cantong, Joevanni Parairo
  • Patent number: 10615800
    Abstract: A method of configuring a programmable integrated circuit device. A channel source within the virtual fabric is configured to receive input data from a first kernel outside of the virtual fabric and on the programmable integrated circuit device, and a channel sink within the virtual fabric is configured to transmit output data to the first kernel. The configuring of the channel source is modified such that the channel source receives input data from a second kernel in response to detecting a change in operation of the programmable integrated circuit device.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: April 7, 2020
    Assignee: Altera Corporation
    Inventors: Doris Tzu Lang Chen, Deshanand Singh
  • Patent number: 10615955
    Abstract: Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include rate detection circuitry, receiver circuitry, and configuration circuitry. The receiver circuitry may receive a data stream with an arbitrary data rate. The rate detection circuitry may receive a reference clock signal that is associated with the received data stream. The rate detection circuitry determines the frequency of the reference clock signal such that an appropriate clock signal may be generated for the receiver circuitry. The receiver clock signal may be generated by clock generation circuitry that is coupled to the rate detection circuitry. The configuration circuitry may accordingly configure the receiver circuitry based at least on the determined frequency of the reference clock signal so that the receiver circuitry may operate at the arbitrary data rate.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: April 7, 2020
    Assignee: Altera Corporation
    Inventors: Boon Hong Oh, Chee Seng Tan, Chau Perng Chin
  • Patent number: 10606520
    Abstract: A disclosed apparatus to access a nonvolatile memory includes a physical geometry selector to select a first assumed physical geometry of a nonvolatile memory from among a plurality of assumed physical geometries supported by a memory controller, an information supplier to supply information about the first physical geometry to a set of registers, and a boot up controller to cause the memory controller to access data in the nonvolatile memory. The memory controller to access data in the nonvolatile memory uses the information supplied to the set of registers. Example disclosed apparatus further include a feedback input to receive feedback from the memory controller.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: March 31, 2020
    Assignee: Intel IP Corporation
    Inventor: Sachin Thakur
  • Patent number: 10607674
    Abstract: A two-terminal stochastic switch is disclosed. The switch includes a magnetic tunnel junction (MTJ) stack, an access switch controlled by a first terminal and coupled to the MTJ stack, such that when the access switch is on, electrical current flows from a first source coupled to the MTJ stack, through the MTJ stack, and through the access switch to a second source, and a digital buffer coupled to the MTJ stack and the access switch which is configured to transform an analog signal associated with a voltage division across the MTJ stack and the access switch to a digital signal, output of the digital buffer forming a second terminal.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: March 31, 2020
    Assignees: Purdue Research Foundation, THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Kerem Yunus Camsari, Supriyo Datta, Sayeef Salahuddin
  • Patent number: 10601425
    Abstract: A system and apparatus can include a first port configured to support a first link width; a second port configured to support a second link width, the second link width different from the first link width; and physical layer logic to receive from the first port a first data block arranged according to the first link width and frequency; create at least one second data block arranged according the second link width and frequency, the at least one second data block including data bytes from the first data block arranged sequentially in the at least one second data block; and transmit the at least one second data block to the second port.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventor: Debendra Das Sharma
  • Patent number: 10592440
    Abstract: Systems and methods for adding a logic layer between FPGA I/O and the core logic of the FPGA. With the extra layer, users can monitor and/or modify the I/O to the FPGA. In addition, users can monitor and/or modify input/output to the core logics of the FPGA, thereby filtering both I/O to the FPGA and the logic blocks of the FPGA. With the filtering in place, a non-intrusive digital scope can be implemented which can, in turn, be used to create a “black box” regarding FPGA I/O during the occurrence of the catastrophic events within the system.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: March 17, 2020
    Assignee: Oracle International Corporation
    Inventors: Xianda Ma, Michael David Derbish, Cornelia Luise Edeltraut Koch-Stoschek, Rambabu Lolabattu, Simon yiu hoi Poon, Cheng Yang
  • Patent number: RE47945
    Abstract: Systems and methods provide an extensible, multi-stage, realtime application program processing load adaptive, manycore data processing architecture shared dynamically among instances of parallelized and pipelined application software programs, according to processing load variations of said programs and their tasks and instances, as well as contractual policies. The invented techniques provide, at the same time, both application software development productivity, through presenting for software a simple, virtual static view of the actually dynamically allocated and assigned processing hardware resources, together with high program runtime performance, through scalable pipelined and parallelized program execution with minimized overhead, as well as high resource efficiency, through adaptively optimized processing resource allocation.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: April 14, 2020
    Assignee: ThroughPuter, Inc.
    Inventor: Mark Henrik Sandstrom