Method of Producing and Operating a Low Power Junction Field Effect Transistor
A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth is provided. The method includes having an input capacitance for said CJFET inverter to be less than the corresponding input capacitance of a CMOS inverter of similar linewidth. The CJFET operates at a power supply with a lesser value than the voltage drop across a forward-biased diode having a reduced switching power as compared to said CMOS inverter and having a propagation delay for said CJFET inverter that is at least comparable to the corresponding delay of said CMOS inverter.
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The present application is a continuation of U.S. patent application Ser. No. 11/635,004, filed Dec. 7, 2006, which claims priority under 35 U.S.C. §119 to U.S. Provisional Application No. 60/748,089, filed Dec. 7, 2005, the entire contents of which are hereby incorporated by reference in their entirety.
TECHNICAL FIELD OF THE INVENTIONIntegrated circuits and devices, and methods of producing and/or using such, are disclosed, such as MOS transistors and Junction Field Effect Transistors (JFETs) and circuits.
BACKGROUND OF THE INVENTIONVery Large Scale Integrated Circuits are being scaled to smaller dimensions to gain greater packing density and faster speed in a continuation of the trend of the past thirty years. Currently, CMOS technology is being manufactured with sub-100 nanometer (nm) minimum dimensions in 2005. Scaling CMOS with the minimum line width below 100 nm presents numerous problems to designers of integrated circuits. A few of the problems of the scaled CMOS transistors below 100 nm are highlighted below;
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- 1. Power dissipation in CMOS is a big problem due to the high switching load caused by the increase in gate capacitance per unit area as the thickness of the gate dielectric is scaled.
- 2. The thickness of the gate dielectric used in the MOS transistor has been scaled down to less than 20 angstroms. Thinning of the gate dielectric has resulted in a significant amount of current through the gate dielectric as voltage is applied to the gate electrode. This current is termed the gate leakage.
- 3. The transistors conduct a finite current between the drain and source even when the gate voltage is reduced to zero. This current is termed the source drain leakage.
- 4. The result of the effects described above is CMOS circuits which conduct a significant amount of current even when there is no activity (static current); this undermines a key advantage of CMOS. Because of the static current, the static power, or the power dissipated by the CMOS chip when there is no activity, has become quite large, and at temperatures close to 100 degrees centigrade, the static power dissipation can become nearly equal to the dynamic power dissipation in CMOS circuits. As the CMOS technology is scaled to 65 nm, the problem of leakage is becoming more severe. This trend continues as the technology is scaled further to line widths of 45 nm and below.
- 5. The lateral scaling of CMOS design rules has not been accompanied by vertical scaling of feature sizes, resulting in three dimensional structures with extreme aspect ratios. For instance, the height of the polysilicon gate has decreased only 50% while the lateral dimension of the polysilicon gate has been reduced by over 90%. Dimensions of the “spacer” (a component of a CMOS transistor which separates the gate from the heavily doped source and drain regions) are dependent upon the height of the polysilicon, so it does not scale in proportion to the lateral dimensions. Process steps which are becoming difficult with scaling of vertical dimensions include formation of shallow source and drain regions, their silicidation without causing junction leakage, and etching and filling of contact holes to the source and drain regions
- 6. It is well known to those skilled in the art to measure power supply leakage current as an effective screen for detecting defects introduced in the fabrication of the device. This method is sometimes referred to as the Iddq test by those skilled in the art. This method is effective for CMOS with the minimum line width above 350 nm. Scaling CMOS with the minimum line width below 350 nm increases the inherent leakage current to levels comparable to defect induced leakage current, rendering the Iddq test ineffective. Biasing the well voltage of the MOS device to eliminate the inherent leakage current introduces new elements of leakage such as gate leakage, junction tunneling leakage, etc.
The prior art in junction field effect transistors dates back to the 1950s when they were first reported. Since then, they have been covered in numerous texts such as “Physics of Semiconductor Devices” by Simon Sze and “Physics and Technology of Semiconductor Devices” by Andy Grove. Junction field effect devices were reported in both elemental and compound semiconductors. Numerous circuits with junction field effect transistors have been reported, as follows; such as:
Nanver and Goudena, “Design considerations for Integrated High-Frequency p-Channel JFET's”, IEEE Transactions Electron Devices, vol. 35, No. 11, 1988, pp. 1924-1933.
O. Ozawa, “Electrical Properties of a Triode Like Silicon Vertical Channel JFET”, IEEE Transcations Electron Devices vol. ED-27, No. 11, 1980, pp. 2115-2123.
H. Takanagi and G. Kano, “Complementary JFET Negative-Resistance Devices”, IEEE Journal of Solid State Circuits, vol. SC-10, No. 6, December 1975, pp. 509-515.
A. Hamade and J. Albarran, “A JFET/Bipolar Eight-Channel Analog Multiplexer”. IEEE Journal of Solid State Circuits, vol. SC-16, No. 6, December 1978.
K. Lehovec and R. Zuleeg, “Analysis of GaAs FET's for Integrated Logic”, IEEE Transaction on Electron Devices, vol. ED-27, No. 6, June 1980.
In addition, a report published by R. Zuleeg titled “Complementary GaAs Logic” dated 4 August, 1985 is cited as prior art. The authors have also published the material in Electron Device Letters in 1984 in a paper titled “Double Implanted GaAs Complementary JFET's”.
A representative structure of a conventional n-channel JFET is shown in
A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth is provided. The method includes having an input capacitance for said CJFET inverter to be less than the corresponding input capacitance of a CMOS inverter of similar linewidth. The CJFET operates at a power supply with a lesser value than the voltage drop across a forward-biased diode having a reduced switching power as compared to said CMOS inverter and having a propagation delay for said CJFET inverter that is at least comparable to the corresponding delay of said CMOS inverter.
So that the manner in which the above recited features, advantages and objects are attained and can be understood in detail, a more particular description, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings.
It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting as other equally effective embodiments will be apparent to those skilled in the art.
A method of building complementary logic circuits is disclosed using Junction Field Effect Transistors (JFETs) in silicon. an exemplary method is suited for deep submicron dimensions, such as below 65 nm.
A system of semiconductor devices having, for example, minimum feature sizes of 65 nm and below, is also disclosed. Methods and structures disclosed herein can build semiconductor devices and circuits which are similar to those used for CMOS devices. As such, exemplary embodiments can be inserted in an existing VLSI design and fabrication flow without any significant change in the overall system for designing and fabricating VLSI circuits. Exemplary attributes are as follows;
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- 1. It allows significant reduction in the power dissipation of the circuit.
- 2. It allows significant reduction in the gate capacitance.
- 3. It allows significant reduction in the leakage current at the gate.
- 4. It allows significant reduction in the leakage current between source and drain.
- 5. It allows significant simplification of the VLSI manufacturing process.
- 6. It leverages the design infrastructure developed for CMOS technology. It is contemplated that all complex logic functions available in prior art CMOS cell library can be implemented with the devices disclosed herein. These complex logic functions include but not limited to inverter, nand, nor, latch, flip-flop, counter, multiplexer, encoder, decoder, multiplier, arithmetic logic unit, programmable cell, memory cell, micro-controller, JPEG decoder, and MPEG decoder.
- 7. It leverages the existing manufacturing and test infrastructure used for CMOS.
- 8. It allows the method of measuring power supply leakage current as an effective screen for detecting defects introduced in the fabrication of the device.
A complementary Junction Field Effect Transistor (JFET) disclosed herein is operated in the enhancement mode. As is known to those skilled in the art, enhancement mode, implies that the transistor is in the “OFF” state when the potential between the gate and the source terminals is zero. In this state, there is little or no current flow between drain and source when a positive (negative) bias is applied at the drain terminal of the n-channel (p-channel) JFET. As the potential at the gate is increased (decreased), the n-channel (p-channel) JFET enters the high conduction regime. In this mode, a finite current flows between the drain and the source upon application of positive (negative) bias at the drain. A limitation of known enhancement mode JFET devices is that their current drive is limited by the maximum gate voltage, which is less than one diode drop. A gate voltage in excess of one diode drop (the built-in potential) turns on the gate-channel diode which is an undesirable mode of operation for the JFET. This limitation can be resolved by, for example, limiting the biasing voltage, VDD, to less than one diode drop. The problem of low current drive of the JFET is addressed by scaling the channel length of the JFET to sub-100 nanometer dimensions. When the JFET gate length is less than 70 nanometers and the power supply voltage is 0.5 V, the current output of the complementary JFET devices and the switching speed of the inverters made with the complementary JFET devices compare favorably with known CMOS devices.
It should be noted that although the speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions, the maximum power supply voltage for the JFETs can still be limited to below a diode drop. To satisfy certain applications which require an interface to an external circuit driven to higher voltage levels, structures and methods to build CMOS devices are also disclosed. The CMOS devices described herein differ from known CMOS along the following points;
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- 1. CMOS is integrated with complementary JFETs.
- 2. In one embodiment, CMOS is built without any “spacer”.
- 3. Contacts to the CMOS terminals can be planar, or at the same level, which can improve the manufacturability of the devices.
- 4. Other salient features of exemplary CMOS devices described herein.
An exemplary circuit diagram of an inverter is shown in
The operation of the circuit shown in
JFETs operate by applying a control signal at the gate, which controls the conduction characteristics of the channel between the source and the drain. The gate forms a p-n junction with the channel. The voltage at the gate with respect to the source controls the width of the depletion region of the gate-to-channel junction. The undepleted part of the channel is available for conduction. Thus, the channel is turned ON and OFF by applying appropriate voltages at the gate and source terminals of the JFET transistor. Current will flow between the source and the drain when the channel is turned ON and the appropriate voltage is applied to the drain.
The JFET transistors FT1 and FT2 in the JFET inverter can function in a manner very similar to the MOS transistors in a CMOS inverter. The operation of a CMOS inverter is well known to those skilled in the art. The p-channel JFET (FT1) is connected to the power supply at its source terminal. The n-channel JFET (FT2) is connected to the ground at its source terminal. The drain terminals of the two transistors are connected together and to the output terminal of the gate. The gate of the p-channel JFET FT1 and the gate of n-channel JFET FT2 are connected together and to the input terminal of the gate, as shown in
The functioning of the inverter is explained in greater detail here in order to reveal an exemplary full implementation. This is accomplished by first explaining the voltages at the source and the drain terminals of the transistor, which are shown in Table 2. In an exemplary and non-limiting illustration, the power supply voltage is fixed at 0.5V.
The gate of the p-channel JFET is made of n-type silicon and the channel is doped p-type. The doping profile of the p-channel JFET is designed to turn off conduction through the channel when the voltage on the gate terminal is at zero volts relative to the source terminal. This device is an enhancement mode device. This attribute of the p-channel JFET is due to the built-in potential at the p-n junction between the gate (p-type) and the channel (n-type). Since the source of the FT1 is tied to VDD at 0.5V, the external bias between the n-type channel and p-type gate is 0.0V when the gate of the FT1 is also at 0.5 V. This represents the FT1 in the OFF condition. As the bias at the gate of the p-channel transistor is decreased to 0.0V, the negative voltage between the gate and the source terminals changes to −0.5V, which causes the depletion layer to collapse and allows the flow of current from source to drain. This represents the FT1 in the ON condition.
Exemplary embodiments can limit gate current when FT1 is in the ON condition. The channel-to-gate diode is forward biased at 0.5 V under this condition, so there is a finite leakage current which flows through the gate of the transistor. It is termed the gate leakage. The magnitude of the gate leakage is controlled by the built-in potential across the gate-channel junction. The built-in potential limits the gate leakage current to a very small amount when this CFET inverter is operated with supply voltages (VDD) at or below 0.5V for silicon-based circuits. Thus, the CFET inverter works in a manner similar to the CMOS inverter in both design and operating characteristics. The limit for supply voltages may be different for other materials because of differences in the built-in potential. Similarly, the bias voltages for the n-channel JFET are reversed; the transistor is turned “OFF” when the gate-source bias is reduced to zero and it is turned on when the gate-source bias is equal to the supply voltage VDD, which is limited to 0.5V in order to restrict the gate current. The gate current of a typical gate-channel junction is projected in the range of 1 uA/cm2 to 100 mA/cm2. In contrast, for an MOS transistor made with 45 nanometer lithography and appropriately scaled gate dielectric thickness, the gate current is projected to be in excess of 1000 A/cm2.
The input capacitance of the JFET transistor is the junction capacitance of the diode formed by the gate-channel terminals. The capacitance of this diode is in the range of 10−8 F/cm2 to 10−6 F/cm2, determined by the thickness of the depletion layer width of the junction, which is in the range of 100 angstroms to 3000 angstroms. The input capacitance of an MOS transistor made with 45 nanometer design rules and 10 angstrom thick oxide is an order of magnitude higher than the corresponding input capacitance of the JFET. This feature makes the JFET extremely attractive from the perspective of low power operation.
The JFET transistors also have a fourth electrical terminal, namely the well. One embodiment of the invention is described here with the well connected to the source terminal for both the JFETs, as shown in
A doping profile of the transistor at varying depths from the silicon surface through the gate (370) and channel (350) is shown in
Other methods for forming the p-type gate junction, such as ion-implantation are encompassed herein. Other methods to dope the gate, such as plasma immersion implant, as is well known to those skilled in the art, are also encompassed.
In
The ohmic contact to the well is made by the well tap marked as object 368. The contacts to the four terminals of the JFET, namely well, source, gate, and drain are shown in
The doping types are reversed for the p-channel JFET in relation to those described in
An alternate embodiment of the JFET is shown in
In an alternate embodiment of the JFET, as shown in
In an alternate embodiment, the top surface of the silicon substrate is formed by epitaxial deposition of silicon-germanium alloy, which is doped appropriately to form the channel and the gate, shown in
Another embodiment, shown in
An exemplary embodiment teaches the use of a silicon-carbide layer near the surface of the silicon to a depth ranging from 10 Å to 1000 Å, followed by deposition of polysilicon to a depth of 10 Å to 2500 Å. The composition of the polycrystalline layer is varied to facilitate accurate monitoring of the etching process, in which the polycrystalline material is etched fast until the composition marking the bottom of the layer is detected and then slowly with a selective etching process until all the polycrystalline material is etched. Detailed explanation of the fabrication process using polycrystalline silicon carbide is explained later in this document.
Next, an exemplary but non-limiting method of building the complementary JFET structure as shown in
Next, a layer of polysilicon is deposited over the whole wafer, as shown in
The p-JFET is formed with regions 1324 and 1320 acting as the source and drain contacts (p type), respectively, region 1322 as the gate (n type), and region 1326 as the contact to the well tap (n type). Regions 1320 and 1324 are doped with a heavy concentration of boron atoms to a dose ranging between 1×1013/cm2 and 1×1016/cm2 and are designed to act as the source and drain contacts of the pJFET respectively. Similarly, regions 1322 and 1326 are doped heavily n-type and are designed to act as gate and well contacts of pJFET. In an alternate embodiment, a layer of oxide is deposited on top of the polysilicon layer before doing the ion implantation. The thickness of this layer varies between 20 Å and 500 Å. In another embodiment, layers of oxide and nitride are deposited on top of the polysilicon prior to ion implantation, with the thickness of the oxide and nitride films varying between 10 Å and 500 Å.
After diffusion of the various regions of the JFETs into the silicon, the gate patterning process takes place. Using an optical lithographic process, a layer of an anti-reflective coating, followed by a layer of photoresist are coated on the wafer. The thickness of these layers depends upon the selection of the photoresist, as is known to those skilled in the art. The photoresist layer is exposed and various terminals are delineated in the photoresist, marked as 1510 in
The next process step consists of depositing a dielectric (oxide) layer, etching contact holes in the oxide layer, and forming contact holes for the source, drain, gate and well tap terminals, and continuing with the conventional metal interconnect formation process as practiced in the formation of semiconductor chips. A cross section of the wafer after dielectric deposition and contact hole etch is shown in
This process can be adapted for making MOS transistors along with JFETs. One application of this adaptation is to include CMOS-compatible I/Os on the chip. The process to make MOS transistors is described next.
Next, a layer of polysilicon is deposited on the wafer as shown in
The next step is the definition of the gate and the remaining electrodes on polysilicon, as shown in
The complete flow for forming JFETs and MOSFETs on the same wafer is shown in
Known MOS transistors have a spacer which is used to separate the highly doped source/drain regions from the gate. The dimensions of the spacer are dependent upon the vertical polysilicon dimension and other processing parameters, and are not laterally scalable. The current embodiment of the MOS transistor uses lithography to separate the source/drain and the gate region, making this structure laterally scalable.
Known MOS transistors have a lightly doped source and drain region under the spacer, which limits the injection efficiency of the source, or the maximum current which can be controlled by the transistor. The current embodiment of the MOS transistor uses the link region as the source and drain junctions and it allows the doping of this region to be controlled independently.
Known MOS transistors have symmetrical source and drain regions. This embodiment allows asymmetrical source and drain junctions to be formed by spacing the source and drain polysilicon contacts from the gate asymmetrically.
Known MOS transistors have varying contact depths to the source/drain and the gate terminals; the contacts to the source/drain terminals are made directly to silicon while the contact to the gate terminal is made to polysilicon which is elevated from the source/drain junctions. This embodiment of MOS transistors etches all the contact holes to the polysilicon, keeping the depth of all the holes the same.
Known MOS transistors compromise the short channel performance due to limitations imposed by a shallow source/drain junction and the silicide formation on top of these junctions. This embodiment of the MOS transistors removes this limitation by placing the silicide on top of the polysilicon for all the junctions. Also, the shallow source/drain junction in the silicon is formed by diffusion of dopants from the polysilicon, which is a slower and more controllable process.
This method to build JFETs and MOSFETs allows a planar surface to exist prior to contact hole etch. It also insures that the amount of polysilicon removed is limited, which can be important in achieving a uniform plasma etch. It is well known that the variation in the density of the polysilicon pattern on the silicon wafer is responsible for variation in the etch rate of polysilicon. In this method, this problem can be overcome by the fact that the pattern density of polysilicon is much higher than in conventional process technology. Also, the contacts to the various junctions are separated by the polysilicon layer, which makes it extremely convenient to form shallow source and drain junctions.
Steps in
The gate electrodes of the JFET and the MOS transistors are implanted with appropriate dopants. The gate regions of the NMOS transistor and the pJFET are doped heavily n-type with arsenic, phosphorus, or antimony. The gate electrode regions of the PMOS and the nJFET are implanted with p-type dopants, namely boron. The gate electrode regions are implanted with a heavy dose of the dopants in the range of 1×1014/cm2 to 1×1016/cm2. An alternate embodiment of the invention includes multiple implant steps for forming the gate electrode region of the MOS and JFET transistors. The wafer is heated to distribute the dopants throughout the polysilicon layer.
A photomask is put on the wafer and the layer of polysilicon is etched to define the gate electrodes for the transistors, as is shown in
Exemplary embodiments provide numerous advantages described herein. For example, compatibility with MOS can be achieved in accordance with exemplary embodiments. An exemplary comparison of NFET and NMOS is shown below. This is based upon TOX of 10 Å for MOS; and Tdepletion of 720 Å for JFET (with corresponding channel doping 1×1018/cm2). This result in significant in input capacitance and related performance specifications, as shown in Table 1.
The gate region can have an impurity concentration doped from the gate electrode region.
In comparison to fabricating a MOS structure, the JFET structure can be manufactured with fewer processing steps. In addition to the elimination of the gate dielectric, the gate in a JFET can be fabricated by diffusing the dopants from polysilicon. Using a single critical masking step and simplified contact hole etch process (i.e., drop down to the same level), process complexity can be reduced. Furthermore, electron mobility enhancing technology developed for CMOS (e.g., strained lattice) can be applicable to the JFET devices disclosed herein.
In exemplary embodiments, the thickness of the depletion layer can be between about 100 Å to about 3000 Å during the application of the second voltage. The gate region can have a line-width of about 45 nm.
In an exemplary embodiment, a first JFET can be configured adjacent to a second JFET, wherein the channel region of the first JFET is n-type and the channel region of the second JFET is p-type.
Various devices currently utilize CMOS technology, for example, static logic gates, dynamic logic gates, pass logic gates and memories. These devices can be fabricated by incorporating JFET technology as described herein. The JFET can be incorporated into any number of circuits and/or devices including, but not limited to a memory device such as an SRAM.
In general, JFET devices with lower junction capacitance can reduce the propagation delay, in comparison to their CMOS counterparts. Propagation delay, Td, can be computed from the following expression:
By setting dTd/h=0 and dTd/dk=0, yields:
Td=7.6√{square root over ((R0RintC0Cint))}
or
Td=Const.√{square root over (R0C0)}
In other words, the R0C0 value for CFET exhibits an approximately ten-fold decrease or about a three-fold decrease in propagation delay.
Furthermore, assuming:
and by substituting the expression for k and h into the expression describing power yields:
Power=½*Cint*Vdd2+½√{square root over (2.3)}*Cint*Vdd2
Thus, at optimal values of k and h, power is a function of Cint only. In other words, power is independent of C0. The above expressions are also described, by H. B. Bakoglu, PhD. Dissertation, Stanford University 1986, pp. 43-46, incorporated by reference in its entirety.
The following Table illustrates exemplary parameters of a CFET device versus those of a CMOS device for use in the exemplary
In alternate embodiments, where a plurality of JFET devices are configured in a repeater chain, a propagation delay is inversely proportional to a number of devices in the requester chain. In one example, the propagation delay can be less than 20 nanoseconds. Such a feature is illustrated in the
In alternate embodiments of a JFET device described herein, the channel region can include at least a layer of strained material. For example, the strained material can be a strained silicon.
The semiconductor substrate can be formed of at least one of Si, GaAs, InP or any III-V material.
An advantage of an NFET device as described herein is reduced leakage current, in comparison to its NMOS counterpart, as illustrated in
Transistors as described herein can, for example, be suitable for next generation telephone/PDA handsets having exemplary specifications as follows:
Power=0.1 W (idle)/5 W (active)
Chip area=1 cm2
Gate count=100 M
Clock=1 GHz
10% of the gates active at any time
Power per gate=500 nW
50% of the power dissipated as active power
Active power=250 nW=½CV2
Fabrication of handsets with CMOS devices involve the following exemplary characteristics: Vdd=1.0 V, C=0.5 fF/gate and Cgate=1.5 fF/μm (state of the art). In contrast, exemplary fabrication of handsets with CFET, can be implemented with the following exemplary characteristics: Vdd=0.5 V, C=2.0 fF/gate and Cgate=0.06 fF/μm (state of the art).
The following illustrates exemplary parameters of a next generation handset:
Chip area=1 cm2
Gate count=100 M
Clock=1 GHz
10% of the gates active at any time
-
- Active power=½CV2·f·N·a, with f is as clock frequency, N as total number of gates, and a is activity factor
Ctotal/gate=3·co+8·H·cint
-
- H is the cell height (=20 F, feature size)
- Co is the input gate capacitance
- Cint is the wire capacitance/micron (0.15 fF/μm)
100M gates as configured with JFET transistors described herein can occupy 1 cm2, where 1 gate occupies 1 um2, the feature size=0.045 nm and cell height H=22 F. Applying these parameters, a CMOS chip with Vdd=1.0 V, Ctotal=4.79 fF consumes 24.0 W of power. In contrast, a JFET chip as described herein with Vdd=0.5 V, Ctotal=1.63 fF consumes 2.0 W of power or exhibits a ten-fold decrease in power consumption. This beneficial characteristic can result in lower power dissipation and low chip/package temperature effects, and low leakage.
As illustrated in
It will be appreciated by those skilled in the art that the present invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The presently disclosed embodiments are therefore considered in all respects to be illustrative and not restricted. The scope of the invention is indicated by the appended claims rather than the foregoing description and all changes that come within the meaning and range and equivalence thereof are intended to be embraced therein.
Claims
1. (canceled)
2. A complementary field effect transistor (CFET) inverter circuit, comprising: and
- a p-channel junction field effect transistor (JFET) comprising:
- a source terminal coupled to a power supply voltage;
- a gate terminal coupled to an input voltage; and
- a drain terminal coupled to an output voltage;
- an n-channel JFET comprising:
- a source terminal coupled to a reference voltage;
- a drain terminal coupled to the drain terminal of the p-channel JFET and to the output voltage; and
- a gate terminal coupled to the gate terminal of the p-channel JFET and to the input voltage.
3. The CFET inverter of claim 2, wherein the reference voltage comprises ground.
4. The CFET inverter of claim 2, wherein the power supply voltage comprises 0.5 volts.
5. The CFET inverter of claim 2, wherein the p-channel JFET is turned ON and the n-channel JFET is turned OFF, the input voltage is 0 volts and the output voltage is the power supply voltage.
6. The CFET inverter of claim 2, wherein the p-channel JFET is turned OFF and the n-channel JFET is turned ON, the input voltage is power supply voltage and the output voltage is 0 volts.
7. The CFET inverter of claim 2, wherein the p-channel JFET comprises an enhancement mode device.
8. The CFET inverter of claim 2, having at least one of the following:
- the p-channel JFET further comprises a well terminal coupled to the source terminal of the p-channel JFET; and
- the n-channel JFET further comprises a well terminal coupled to the source terminal of the n-channel JFET.
9. The CFET inverter of claim 2, having at least one of the following:
- the p-channel JFET further comprises a well terminal coupled to the gate terminal of the p-channel JFET; and
- the n-channel JFET further comprises a well terminal coupled to the gate terminal of the n-channel JFET.
10. The CFET inverter of claim 2, having at least one of the following:
- the p-channel JFET further comprises a well terminal to which an external voltage is applied; and
- the n-channel JFET further comprises a well terminal to which an external voltage is applied.
11. The CFET inverter of claim 2, having at least one of the following:
- the p-channel JFET further comprises a well terminal that remains floating; and
- the n-channel JFET further comprises a well terminal that remains floating.
12. The CFET inverter of claim 2, wherein at least one of the p-channel JFET and the n-channel JFET has a sub-70 nanometer linewidth and an input capacitance that is less than the corresponding input capacitance of a CMOS transistor of similar linewidth.
13. The CFET inverter of claim 2, wherein at least one of the p-channel JFET and the n-channel JFET operates at a power supply with a lesser value than the voltage drop across a forward-biased diode.
14. The CFET inverter of claim 2, wherein at least one of the p-channel JFET and the n-channel JFET has a sub-70 nanometer linewidth and a reduced switching power as compared to a CMOS transistor of similar linewidth.
15. The CFET inverter of claim 2, wherein at least one of the p-channel JFET and the n-channel JFET has a sub-70 nanometer linewidth and a propagation delay that is at least comparable to the corresponding delay of a CMOS transistor of similar linewidth.
16. A complementary field effect transistor (CFET) inverter circuit, comprising: and wherein:
- a p-channel junction field effect transistor (JFET) comprising:
- a source terminal coupled to a power supply voltage;
- a gate terminal coupled to an input voltage; and
- a drain terminal coupled to an output voltage;
- an n-channel JFET comprising:
- a source terminal coupled to a reference voltage;
- a drain terminal coupled to the drain terminal of the p-channel JFET and to the output voltage; and
- a gate terminal coupled to the gate terminal of the p-channel JFET and to the input voltage;
- at least one of the p-channel JFET and the n-channel JFET has a sub-70 nanometer linewidth and an input capacitance that is less than the corresponding input capacitance of a CMOS transistor of similar linewidth;
- wherein at least one of the p-channel JFET and the n-channel JFET operates at a power supply with a lesser value than the voltage drop across a forward-biased diode;
- wherein at least one of the p-channel JFET and the n-channel JFET has a sub-70 nanometer linewidth and a reduced switching power as compared to a CMOS transistor of similar linewidth; and
- wherein at least one of the p-channel JFET and the n-channel JFET has a sub-70 nanometer linewidth and a propagation delay that is at least comparable to the corresponding delay of a CMOS transistor of similar linewidth.
17. A complementary field effect transistor (CFET) inverter circuit, comprising: and
- an n-channel junction field effect transistor (JFET) comprising:
- a source terminal coupled to a power supply voltage;
- a gate terminal coupled to an input voltage; and
- a drain terminal coupled to an output voltage;
- a p-channel JFET comprising:
- a source terminal coupled to a reference voltage;
- a drain terminal coupled to the drain terminal of the n-channel JFET and to the output voltage; and
- a gate terminal coupled to the gate terminal of the n-channel JFET and to the input voltage.
Type: Application
Filed: Jan 6, 2009
Publication Date: Jul 23, 2009
Applicant: DSM Solutions, Inc. (Los Gatos, CA)
Inventor: Ashok Kumar Kapoor (Palo Alto, CA)
Application Number: 12/349,350
International Classification: H03K 19/20 (20060101); H03K 19/094 (20060101);