SCRIBE BASED BOND PADS FOR INTEGRATED CIRCUITS

Abstract

An apparatus including a semiconductor substrate is disclosed. A first semiconductor die is disposed on the semiconductor substrate. A first bond out pad is disposed on the semiconductor substrate adjacent to the first semiconductor die. A first sawn semiconductor die is disposed on the semiconductor substrate adjacent to the first semiconductor die and the first bond out pad.

Description

RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No. 11/607,564, filed on Dec. 1, 2006, which is incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

The present invention relates generally to semiconductor devices and specifically to a method of separating product and test die from a semiconductor wafer.

BACKGROUND OF THE INVENTION

Many microcontrollers and microprocessors contain embedded memories such as ROM. Typically, it is not possible to modify the memory of embedded ROM after manufacture. In the case of Write Once Memory, it is only possible to modify the memory once.

It is standard in the industry to develop software applications for embedded processors. In order to develop and test software on real-time (or full speed) silicon it is necessary to bond out the read only memory on externally accessible bond out pads. The internal memory is isolated and replaced by external memory connected to the bond out pads.

Currently, manufacturers use bond out memory in development silicon. However, the standard approach requires that the provision of bond out pads occupy a significant amount of silicon area, resulting in a significant increase in product cost. Manufacturers have addressed this issue by either absorbing the costs or by manufacturing two variants of silicon, one for development purposes that includes bond out pads and a production version that does not include bond out pads. Both approaches lead to an increase cost of production.

Accordingly, what is desired is a cost-efficient method of manufacturing semiconductor wafers that can be used for both product and development purposes. The present invention addresses this need.

BRIEF SUMMARY OF THE INVENTION

A method and system for utilizing a semiconductor wafer is disclosed. The wafer comprises a plurality of semiconductor die and a plurality of scribe areas interspersed between. The method and system comprises forming bond out pads in the scribe areas such that the bond out pads are disposed on the semiconductor wafer between the plurality of semiconductor die. Additionally, the method and system comprises separating the semiconductor wafer into individual die such that when the semiconductor wafer is separated in a first manner at least one product die is provided. Furthermore, when the semiconductor wafer is separated in a second manner at least one test die is provided.

An apparatus including a semiconductor substrate is disclosed. A first semiconductor die is disposed on the semiconductor substrate. A first bond out pad is disposed on the semiconductor substrate adjacent to the first semiconductor die. A first sawn semiconductor die is disposed on the semiconductor substrate adjacent to the first semiconductor die and the first bond out pad.

Accordingly, it is an advantage of the present invention to provide separation methods that provide either a plurality of product die or a plurality of test die from a semiconductor wafer.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which:

FIG. 1 shows a top version of a semiconductor wafer which features a plurality of semiconductor die, represented by small squares.

FIG. 2 shows a magnified area of a 3×3 semiconductor die cluster and bond out pad circuitry in a scribe area on a semiconductor wafer.

FIG. 3 shows a magnified area of a 3×3 semiconductor die cluster, saw lines on semiconductor dice adjacent to a test/emulation die, and corresponding bond out pads.

FIG. 4 shows a sawn semiconductor wafer structure featuring an emulation/test die with corresponding bond out pads, test circuitry, and adjacent, sawn-semiconductor dice.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates generally to semiconductor devices and specifically to a method of separating product and test die from a semiconductor wafer. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.

FIG. 1 shows a top view of a semiconductor wafer 100 that features a plurality of semiconductor die 101, denoted by small squares. Semiconductor 100 also features bond out pads and test circuitry (shown in subsequent figures). A semiconductor wafer 100 may be designated as a product or test/development wafer. In the event semiconductor wafer 100 is designated for product, the semiconductor die is subsequently separated into individual semiconductor die, which includes destructively removing the test circuitry and bond out pads disposed in the scribe area. Alternatively, in the event that a semiconductor wafer is designated for testing, test dice are separated by sawing through adjacent semiconductor dice while maintaining the integrity of the test circuitry and bond out pads.

According to an embodiment, the term “separating” (and other verb tenses of the term) refers to a process of partitioning a semiconductor wafer into individual, semiconductor die or dice. The term may also be referred to as singulating, dividing, or severing.

For an embodiment, each semiconductor die 101 disposed on semiconductor wafer 100 are identical and each contain memory circuitry for storing data securely. For the embodiment, semiconductor die 101 is a microcontroller and the memory circuit is provided in the form of read-only memory (ROM). For alternative embodiments, semiconductor die 101 is a microprocessor.

For an embodiment, semiconductor wafer 100 is processed using conventional semiconductor fabrication techniques to form semiconductor die 101 thereon. During the fabrication of semiconductor die 101, test circuitry and bond out pads are also formed, according to an embodiment.

As stated previously, a semiconductor wafer may be designated as a product or test/development wafer. In the event a semiconductor wafer is designated for product, the semiconductor die is subsequently separated into individual semiconductor die, which includes destructively removing the test circuitry and bond out pads disposed in the scribe areas.

FIG. 2 shows an example layout of a 3.times.3 semiconductor die cluster 210 when a semiconductor wafer is designated for product. Those having ordinary skill in the art will appreciate that this layout is not limited to a 3.times.3 semiconductor die cluster and that a semiconductor die cluster may incorporate more or less semiconductor dice thereon. For the embodiment when a semiconductor wafer is designated for product, the semiconductor wafer is separated into individual semiconductor dice 201. Separating a semiconductor wafer into individual semiconductor dice 201 may be achieved by use of a sawing technique, laser obliteration, diamond scribe or additional wafer processing techniques such as selective chemical etching. For an embodiment, a sawing technique is used to separate a semiconductor wafer into individual semiconductor dice for product.

For the embodiment when a sawing technique is used, a first sawing procedure is made along a set of scribe lines 203 in scribe area 209. For embodiments, scribe area 209 has a width of approximately 70 microns. In other words, the space between adjacent semiconductor die disposed on a semiconductor wafer is at least approximately 70 microns. In the first sawing procedure, a saw blade having a width less than the width of scribe area 209 is used to cut a shallow depth sufficient to cut into the surface of a semiconductor wafer, but not so deep as to cut completely through the semiconductor wafer. For the embodiment, this sawing procedure destructively removes the test circuitry and bond out pads 202 in scribe area 209.

Next, according to an embodiment, a semiconductor wafer is subjected to a second sawing procedure such that a second cut is made along the path made by the first saw cut within scribe area 209. For an embodiment, a saw blade having a narrow width is used to cut completely through the semiconductor wafer. The second sawing procedure thus completely severs and separates the wafer into individual semiconductor dice, which provides enhancing security against unauthorized access.

It will be appreciated that since the test circuitry and bond out pads 202 have been removed from their respective device dies, at this point no further testing of the device is ordinarily possible. It will be further appreciated that since the test circuitry and bond out pads 202 are destroyed in their removal, their visual inspection or reverse engineering is made practically impossible, further enhancing security of the devices against access by a hacker. It will also be appreciated that any remaining fragments of test circuitry and bond out pads cannot now be used to probe electrical activity or features of the devices since these fragments of inoperable test circuitry and bond out pads are rendered and remain isolated in the absence of the enabling signals from the test circuitry which was present but which has now been destroyed.

It will be appreciated that although in the above described embodiment features in the form of test circuitry and bond out pads are destructively removed to enhance the security of the finished device, the security of the finished device could be alternatively or additionally enhanced by the destructive removal of other features such as expanded test mode circuitry or circuitry for unscrambling (otherwise scrambled) access to the devices' bus, central processing unit or memory.

For an embodiment, a semiconductor wafer may be designated for testing or emulation. FIG. 3 shows a magnified area of a 3×3 semiconductor die cluster 310, saw lines 305 projected on semiconductor dice 301 adjacent to a test/emulation die 304, and corresponding bond out pads 302. For an embodiment, a semiconductor wafer designated for test or emulation undergoes a separation process relative to the separation process used to separate die disposed on product wafers, as described above.

For an embodiment when a semiconductor wafer is designated a test or emulation wafer, a subsequent separation procedure is in accordance with the following: a first sawing procedure along saw lines 305 projected on semiconductor dice 301 to a pre-determined depth such that grooves are cut in adjacent semiconductor dice 301; a second sawing procedure along the grooves formed by the first sawing procedure such that the adjacent semiconductor dice 301 are severed in halves, fourths, or any fraction of the original size of semiconductor dice 301.

FIG. 4 shows a sawn-semiconductor wafer structure 411 featuring an emulation/test die 404 with corresponding bond out pads 402, test circuitry 413, and adjacent, sawn-semiconductor dice 412. As shown, emulation/test die 404 is separated from its parent semiconductor wafer, while the structural integrity of bond out pads 402 and test circuitry 413 remain intact. Additionally, FIG. 4 shows a jagged edge 414, which signifies the aforementioned sawing procedure. For an embodiment, a “jagged edge” is defined as any uneven surface. For example, adjacent, sawn-semiconductor dice 412 may have jagged edges due to the saw-cutting method described above.

It will be further appreciated that the bond out pads may be manufactured such that electrostatic damage (ESD) is minimized. ESD is typically caused by charge build-up in interconnects within semiconductor devices. Often, charges are introduced within semiconductor devices during fabrication processes, such as, but not limited to chemical mechanical polishing, interlayer dielectric etch, and plasma deposition or etch. For an embodiment, ESD protection may be achieved by forming a salicide layer on drain regions and embedding antenna diodes within the bond out pad device.

Typically, devices are conventionally manufactured with ESD protection for human handling (approximately 6 kV), or machine model (approximately 200V). This is necessary for protection/yield reason. For the scribe bond pad application, there is limited available space in the scribe area for placement of bond pads, buffer circuit, and ESD protection circuitry. For semiconductor wafers that have been designated for emulation, the size of ESD protection circuitry can be reduced to allow more space for bond pads and complementary circuitry (buffer and ESD protection circuitry) within the scribe area. For an embodiment, the ESD protection circuitry may be lowered below a level that is acceptable for production devices. However, for embodiments, a reduction in ESD protection is a less critical for emulation (test die) as the volumes of die for testing is small relative to the large volume of production die.

For various embodiments, ESD protection circuitry may be disposed adjacent to or under the bond out pads such that ESD protection is provided.

Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.

Claims

1. An apparatus comprising:

a semiconductor substrate;

a first semiconductor die disposed on the semiconductor substrate;

a first bond out pad disposed on the semiconductor substrate adjacent to the first semiconductor die; and

a first sawn semiconductor die disposed on the semiconductor substrate adjacent to the first semiconductor die and the first bond out pad.

2. The apparatus of claim 1, wherein the first semiconductor die includes a test die.

3. The apparatus of claim 1, wherein the first semiconductor die includes an emulation die.

4. The apparatus of claim 1, wherein the bond out pad is disposed between the first semiconductor die and the first sawn semiconductor die.

5. The apparatus of claim 1, wherein the first bond out pad is disposed along a first scribe line of the semiconductor substrate and completely within a scribe area of the semiconductor substrate.

6. The apparatus of claim 1, comprising a second sawn semiconductor die disposed on the semiconductor substrate adjacent to the first semiconductor die.

7. The apparatus of claim 6, comprising a second bond out pad disposed on the semiconductor substrate between the first semiconductor die and the second sawn semiconductor die.

8. The apparatus of claim 6, wherein the second bond out pad is disposed along a second scribe line of the semiconductor substrate and completely within a scribe area of the semiconductor substrate.

9. The apparatus of claim 1, comprising test circuitry disposed on the semiconductor substrate outside the first semiconductor die.

10. The apparatus of claim 1, wherein the first semiconductor die includes a microprocessor.

11. The apparatus of claim 1, wherein the first semiconductor die includes read only memory.

12. The apparatus of claim 1, comprising electrostatic damage protection circuitry disposed under the first bond out pad.

13. An apparatus comprising:

a portion of a semiconductor wafer;

a first semiconductor die disposed on the portion of the semiconductor wafer;

a first bond out pad disposed adjacent to the first semiconductor die on the portion of the semiconductor wafer; and

a first sawn semiconductor die disposed adjacent to the first bond out pad and at a first edge of the portion of the semiconductor wafer, wherein a part of the first sawn semiconductor die forms at least a portion of the first edge.

14. The apparatus of claim 13, wherein the first semiconductor die includes a test die.

15. The apparatus of claim 13, comprising a second sawn semiconductor die disposed adjacent to the first semiconductor die and at a second edge of the portion of the semiconductor wafer, wherein a part of the second sawn semiconductor die forms at least a portion of the second edge.

16. The apparatus of claim 15, comprising a second bond out pad disposed between the first semiconductor die and the second sawn semiconductor die.

17. The apparatus of claim 13, comprising test circuitry disposed on the portion of a semiconductor wafer and adjacent the first semiconductor die.

18. A sawn semiconductor wafer structure comprising:

a first sawn edge and a second sawn edge;

a test die disposed between the first and second sawn edges;

a first bond out pad disposed adjacent to the test die; and

a first sawn semiconductor die disposed adjacent to the first bond out pad and at the first sawn edge, wherein at least a portion of the first sawn edge is a part of the first sawn semiconductor die.

19. The sawn semiconductor wafer structure of claim 18, comprising a second sawn semiconductor die disposed adjacent to the test die and at the second sawn edge, wherein at least a portion of the second sawn edge is a part of the second sawn semiconductor die.

20. The sawn semiconductor wafer structure of claim 19, comprising a second bond out pad disposed between the test die and the second sawn semiconductor die.