MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH SELF-ALIGNED AIR GAPS BETWEEN CLOSELY SPACED METAL LINES
Air gaps may be provided in a self-aligned manner with sub-lithography resolution between closely spaced metal lines of sophisticated metallization systems of semiconductor devices by recessing the dielectric material in the vicinity of the metal lines and forming respective sidewall spacer elements. Thereafter, the spacer elements may be used as an etch mask so as to define the lateral dimension of a gap on the basis of the corresponding air gaps, which may then be obtained by depositing a further dielectric material.
1. Field of the Invention
Generally, the subject matter of the present disclosure relates to microstructure devices, such as integrated circuits, and, more particularly, to the metallization layers including highly conductive metals, such as copper, embedded into a dielectric material of reduced permittivity.
2. Description of the Related Art
In modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby steadily increasing performance of these circuits in terms of speed and/or power consumption and/or diversity of circuit functions. As the size of the individual circuit elements is significantly reduced, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines and the spaces between the metal lines have to be reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per unit area.
In integrated circuits having minimum dimensions of approximately 0.35 μm and less, a limiting factor of device performance is the signal propagation delay caused by the switching speed of the transistor elements. As the channel length of these transistor elements has now reached 50 nm and less, the signal propagation delay is no longer limited by the field effect transistors, but is limited, owing to the increased circuit density, by the interconnect lines, since the line-to-line capacitance (C) is increased and the resistance (R) of the lines is also increased due to their reduced cross-sectional area. The parasitic RC time constants and the capacitive coupling between neighboring metal lines therefore require the introduction of a new type of material for forming the metallization layer.
Traditionally, metallization layers, i.e., the wiring layers including metal lines and vias for providing the electrical connection of the circuit elements according to a specified circuit layout, are formed by a dielectric layer stack including, for example, silicon dioxide and/or silicon nitride, with aluminum as the typical metal. Since aluminum suffers from significant electromigration at the higher current densities that may be necessary in integrated circuits having extremely scaled feature sizes, aluminum is being replaced by, for instance, copper, which has a significantly lower electrical resistance and a higher resistivity against electromigration. For highly sophisticated applications, in addition to using copper and/or copper alloys, the well-established and well-known dielectric materials silicon dioxide (k≈4.2) and silicon nitride (k>7) may increasingly be replaced by so-called low-k dielectric materials having a relative permittivity of approximately 3.0 and less. However, the transition from the well-known and well-established aluminum/silicon dioxide metallization layer to a copper-based metallization layer, possibly in combination with a low-k dielectric material, is associated with a plurality of issues to be dealt with.
For example, copper may not be deposited in relatively high amounts in an efficient manner by well-established deposition methods, such as chemical and physical vapor deposition. Moreover, copper may not be efficiently patterned by well-established anisotropic etch processes. Therefore, the so-called damascene or inlaid technique is frequently employed in forming metallization layers including copper lines and vias. Typically, in the damascene technique, the dielectric layer is deposited and then patterned for receiving trenches and via openings that are subsequently filled with copper or alloys thereof by plating methods, such as electroplating or electroless plating. Moreover, since copper readily diffuses in a plurality of dielectrics, such as silicon dioxide, and in many low-k dielectrics, the formation of a diffusion barrier layer at interfaces with the neighboring dielectric material may be required. Moreover, the diffusion of moisture and oxygen into the copper-based metal has to be suppressed as copper readily reacts to form oxidized portions, thereby possibly deteriorating the characteristics of the copper-based metal line with respect to adhesion, conductivity and the resistance against electromigration.
During the filling in of a conductive material, such as copper, into the trenches and via openings, a significant degree of overfill has to be provided in order to reliably fill the corresponding openings from bottom to top without voids and other deposition-related irregularities. Consequently, after the metal deposition process, excess material may have to be removed and the resulting surface topography is to be planarized, for instance, by using electrochemical etch techniques, chemical mechanical polishing (CMP) and the like. For example, during CMP processes, a significant degree of mechanical stress may be applied to the metallization levels formed so far, which may cause structural damage to a certain degree, in particular when sophisticated dielectric materials of reduced permittivity are used. As previously explained, the capacitive coupling between neighboring metal lines may have a significant influence on the overall performance of the semiconductor device, in particular in metallization levels, which are substantially “capacitance driven,” i.e., in which a plurality of closely spaced metal lines have to be provided in accordance with device requirements, thereby possibly causing signal propagation delay and signal interference between neighboring metal lines. For this reason, so-called low-k dielectric materials or ultra low-k materials may be used, which may provide a dielectric constant of 3.0 and significantly less, in order to enhance the overall electrical performance of the metallization levels. On the other hand, typically, a reduced permittivity of the dielectric material is associated with a reduced mechanical stability, which may require sophisticated patterning regimes so as to not unduly deteriorate reliability of the metallization system.
The continuous reduction of the feature sizes, with gate lengths of approximately 40 nm and less, may demand even more reduced dielectric constants of the corresponding dielectric materials, which may increasingly contribute to yield loss due to, for instance, insufficient mechanical stability of respective ultra low-k materials. For this reason, it has been proposed to introduce “air gaps,” at least at critical device areas, since air or similar gases may have a dielectric constant of approximately 1.0, thereby providing a reduced overall permittivity, while nevertheless allowing the usage of less critical dielectric materials. Hence, by introducing appropriately positioned air gaps, the overall permittivity may be reduced while, nevertheless, the mechanical stability of the dielectric material may be superior compared to conventional ultra low-k dielectrics. For example, it has been proposed to introduce nano holes into appropriate dielectric materials which may be randomly distributed in the dielectric material to significantly reduce the density of the dielectric material. However, the creation and distribution of the respective nano holes may require a plurality of sophisticated process steps for creating the holes with a desired density, while at the same time the overall characteristics of the dielectric material may be changed in view of the further processing, for instance with respect to planarizing surface areas, depositing further materials and the like.
In other approaches, advanced lithography processes are additionally introduced to create appropriate etch masks for forming gaps near respective metal lines with a position and size as defined by the lithographically formed etch mask. In this case, however, additional cost-intensive lithography steps may be required, wherein the positioning and the dimensioning of the corresponding air gaps may also be restricted by the capabilities of the respective lithography processes. Since typically in critical metallization levels the lateral dimensions of metal lines and the spacing between adjacent metal lines may be defined by critical lithography steps, an appropriate and reliable manufacturing sequence for providing intermediate air gaps may be difficult to be achieved on the basis of the available lithography techniques.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the present disclosure relates to methods and devices in which air gaps may be positioned between closely spaced metal regions with sub-lithography resolution, thereby enabling the reduction of the overall permittivity in a reliable and reproducible manner while avoiding cost-intensive sophisticated lithography processes. For this purpose, a positioning and dimensioning of the respective air gaps to be formed in a dielectric material of a metallization level may be accomplished on the basis of deposition and etch processing without applying critical lithography techniques, while also providing a high degree of flexibility in varying the size of the air gaps. In some illustrative aspects disclosed herein, critical device areas in the metallization level may be selected for receiving air gaps, while other device areas may be covered by an appropriate mask, which may, however, be formed on the basis of uncritical process conditions. Consequently, appropriate dielectric materials providing the desired characteristics may be used, while the reliable and reproducible formation of the air gaps at critical device areas in the metallization level may enable an adjustment of the overall permittivity in accordance with device requirements. For example, the metallization levels of integrated circuits including circuit elements of critical dimensions of 40 nm and less may be manufactured with a reduced permittivity, at least locally, while, in total, the mechanical integrity of the metallization level may be enhanced by avoiding extremely sophisticated and critical low-k dielectric materials.
One illustrative method disclosed herein comprises forming a recess in a dielectric material of a metallization layer of a semiconductor device, wherein the recess extends between two neighboring metal regions formed in the dielectric material. Furthermore, a spacer element is formed on sidewalls of the recess and a gap is formed between the two neighboring metal regions by using the spacer element as an etch mask.
A further illustrative method disclosed herein comprises forming a recess between a first metal line and a second metal line, wherein the first and second metal lines are formed in a dielectric material of a metallization layer of a microstructure device. The method further comprises defining a reduced width of the recess by depositing a spacer layer in the recess. Finally, the method comprises forming a gap between the first and second metal lines on the basis of the reduced width.
One illustrative microstructure device disclosed herein comprises a first metal line formed in a dielectric material of a metallization layer and a second metal line formed in the dielectric material of the metallization layer laterally adjacent to the first metal line. The device further comprises an air gap located in the dielectric material between the first and second metal lines. Furthermore, a first spacer element is formed on a portion of a first sidewall of the first metal line, wherein the first sidewall faces a second sidewall of the second metal line. Finally, the device comprises a second spacer element that is formed at a portion of the second sidewall of the second metal line.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.DETAILED DESCRIPTION
Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
Generally, the present disclosure provides techniques and microstructure devices, for instance, integrated circuits, in which the electrical performance of a metallization system may be enhanced by providing air gaps in the vicinity of critical metal regions, such as metal lines, without requiring sophisticated lithography techniques. That is, the positioning and the dimensioning of the air gaps may be accomplished on the basis of deposition and etch processes without additional lithography masks so that the size of the air gaps may be selected without being restricted by the lithography capabilities. The corresponding air gaps may thus be provided as self-aligned areas in the vicinity of metal lines, thereby reducing the overall permittivity of a space between metal regions, which may therefore enhance electrical performance of the metallization system even for extremely reduced device dimensions, as may be required in technology standards with critical dimensions in the transistor level of 40 nm and significantly less. In some illustrative embodiments, the self-aligned manufacturing sequence may be restricted to desired critical device areas by providing an appropriate mask, which may be formed on the basis of a non-critical lithography process. Consequently, a reliable and reproducible positioning and dimensioning of air gaps may be accomplished, at least in critical device areas, while nevertheless reducing yield loss that may conventionally be associated with critical material characteristics of ultra low-k dielectric materials.
In some illustrative aspects disclosed herein, the positioning and dimensioning of the air gaps may be accomplished by forming a recess adjacent to metal lines in a dielectric material and subsequently creating spacer elements on exposed sidewall portions of the recess, which may then be used as an etch mask, thereby substantially determining the lateral size of corresponding gaps that may be formed between closely spaced metal regions. Consequently, the dimension and the position of the air gaps may be defined on the basis of the process sequence for forming the sidewall spacer elements, thereby enabling the positioning and dimensioning with a degree of accuracy as provided by the associated deposition and etch processes. Hence, even lateral dimensions with sub-lithography resolution may be obtained in a reliable and reproducible manner, thereby providing substantially uniform electrical performance of the corresponding metallization levels. By locally varying the process conditions during the above-described sequence, the characteristics of the air gaps and thus of the electrical behavior may be varied in accordance with device requirements, wherein even a creation of air gaps may be suppressed in certain device levels, if desired. In other illustrative aspects disclosed herein, the surface topography created after the recessing of the dielectric material and the subsequent deposition of a spacer layer may be used in order to form a desired gap between neighboring metal regions, wherein the creation of distinct sidewall spacers may not be necessary. Furthermore, the techniques disclosed herein provide a high degree of flexibility in specifically adjusting the characteristics of the air gaps, for instance, by varying the depth of the recesses, selecting an appropriate thickness of the spacer layer, varying the depth of the gap etched by using the sidewall spacer elements as etch mask and the like. In other illustrative embodiments, an enhanced degree of uniformity and accuracy may be accomplished by providing one or more etch stop or etch control layers at appropriate height levels within the dielectric material in order to precisely determine a depth of the recess and/or a depth of the subsequently formed gap, without significantly contributing to overall process complexity. In still other illustrative embodiments, the overall characteristics of the metal lines may be modified by providing at least a portion of the spacer layer in the form of a conductive material, which may thus contribute to an overall enhancement of the electrical performance of the metal lines, for instance, with respect to conductivity, resistance against electromigration and the like.
Since the present disclosure relates to techniques which may enable the positioning and dimensioning of air gaps with sub-lithographical resolution, the principles disclosed herein may be highly advantageously applied to sophisticated semiconductor devices including transistor elements of the 45 nm technology or the 22 nm technology and beyond. The principles disclosed herein, however, may also be applied to less critical microstructure devices so that the present disclosure should not be considered as being restricted to specific critical device dimensions unless such restrictions are explicitly set forth in the appended claims.
As previously explained, typically, one or more electrical connections may be associated with each of the circuit elements 103, which may thus require a plurality of metallization layers for establishing the electrical connections corresponding to the circuit layout under consideration wherein, for convenience, a portion of a single metallization layer may be illustrated as the metallization system 150. It should be appreciated, however, that below and/or above the metallization layer 150 one or more additional metallization layers may be provided, depending on the overall complexity of the device 100. For any of these additional metallization layers, the same criteria may apply as will be described later on with reference to the metallization layer 150. The metallization layer 150 may comprise a dielectric material 151 which may be provided in the form of any appropriate material or material composition to obtain the desired electrical and mechanical characteristics. For example, the dielectric material 151 may comprise a material having a moderately low permittivity while also providing sufficient mechanical robustness in view of the further processing of the device 100, as previously explained. Since the final permittivity of the metallization layer 150 may be adjusted, at least locally, on the basis of air gaps to be formed in certain locations, the selection of an appropriate dielectric material may preferably be based on the compatibility in view of the subsequent processing rather than a minimum dielectric constant. For instance, a plurality of well-established dielectric materials with a moderately low dielectric constant in the range of approximately 4.0-2.5 may be used in combination with the metallization layer 150. For example, doped silicon dioxide, silicon carbide, a plurality of silicon, oxygen, carbon and hydrogen-containing materials and the like, may be used. Also, appropriate polymer materials may be used for the metallization layer 150, as long as the desired compatibility with the further processing may be achieved. It should be appreciated that the dielectric material 151 may comprise a plurality of different materials, depending on the overall device and process requirements. The metallization layer 150 may further comprise a plurality of metal regions 152A, 152B, 152C which may, for instance, represent metal lines including a highly conductive metal, such as copper and the like, when enhanced performance with respect to conductivity, resistance against electromigration and the like is required. In other cases, other metals, such as aluminum, copper alloys, silver and the like, may be used if compatible with the device characteristics. The metal regions 152A, 152B, 152C, which may also collectively be referred to as metal regions 152, may comprise a barrier layer 153 which may contain, in some illustrative embodiments, two or more sub-layers so as to provide enhanced metal confinement and integrity of the metal with respect to a reaction with reactive components, which may be present in minute amounts within the dielectric material 151.
As previously explained, reactive metals such as copper may require appropriate barrier materials in order to maintain integrity of the copper material and also suppress undue out-diffusion of copper into the surrounding dielectric material 151. In other cases, the barrier material 153 may be omitted if a direct contact of the highly conductive metal with the dielectric material 151 is considered appropriate. For example, the barrier material 153 may comprise a copper alloy, well-established metals and metal compounds, such as tantalum, tantalum nitride and the like, which may also provide enhanced electromigration behavior and mechanical robustness of the metal regions 152 during the further processing. In some illustrative embodiments, the metal regions or metal lines 152A, 152B, 152C may be considered as “closely spaced” metal regions, wherein a lateral dimension of the individual metal lines 152 may be comparable to the lateral distance between two neighboring metal lines, such as the metal lines 152A, 152B or 152B, 152C. For example, the metallization layer 150 may comprise metal lines of a width of several hundred nanometers and significantly less, such as 100 nm and less, while also spacing between neighboring metal lines may be in the same order of magnitude. For example, the metal lines 152 may have critical dimensions, i.e., dimensions that may represent the minimum lateral dimensions that may be reliably and reproducibly obtained by the corresponding lithography process in combination with associated patterning regimes. Thus, as previously indicated, the positioning and dimensioning of any air gaps between adjacent metal lines 152 may be difficult on the basis of lithography techniques.
The device 100 as shown in
Thus, based on the spacer elements 155S, a reduced width 154W may be obtained for the previously formed recesses 154, wherein the resulting width 154W may thus determine the lateral dimension of a gap to be formed between adjacent metal lines 152.
In some illustrative embodiments, the etch processes 112 and 113 may be performed as a combined etch process without requiring pronounced etch selectivity between the spacer elements 155S and the material of the layer 151. That is, the spacer layer 155 (
After the deposition of the layer 157, the further processing may be continued, for instance, by planarizing the surface topography, if required, which may be accomplished by CMP and the like, wherein a top surface of the metal lines 152 may act as a stop layer, or wherein a certain amount of the layer 157 may be maintained so as to act as a cap layer and etch stop material for the further processing, for instance, for forming further metallization levels above the metallization layer 150. In still other illustrative embodiments, a CMP stop layer may be included into the cap layer 157, for instance, by first depositing a respective material, such as silicon nitride, silicon dioxide and the like, followed by a desired dielectric material, such as a material as used in the layer 151, or any other appropriate material. During the corresponding deposition sequence, the air gaps 156A may not necessarily be entirely closed by the deposition of the CMP stop material, but may remain open and may then be completely closed by the further deposition step.
Consequently, in the embodiment shown, the metal lines 152A, 152B, 152C may comprise the spacer elements 155S at an upper portion thereof, which may be formed on a fin comprised of material of the layer 151, wherein the spacers 155 S, in combination with the fin 151F, and together with material of the layer 157, may define the air gaps 156A. In some illustrative embodiments, the spacer elements 155S may be comprised of a dielectric material, such as silicon nitride, silicon dioxide and the like, as previously indicated, while, in other cases, the spacers 155S may comprise a conductive material, such as tantalum, tantalum nitride, titanium, tungsten, aluminum and the like, thereby enhancing the overall conductivity of the metal regions 152A, 152B, 152C. Providing a conductive barrier material may thus result in enhanced integrity of the metal lines if a certain degree of etch damage may have occurred during the exposure of upper sidewall portions of the metal lines 152. In some illustrative embodiments, the previously provided barrier material 153 may intentionally be removed during the process for forming the recesses 254 (see
With reference to
With reference to
With reference to
With reference to
As a result, the present disclosure provides techniques and microstructure devices in which the permittivity of a dielectric material of a metallization layer may be adjusted on the basis of air gaps, which may be provided in a self-aligned manner without requiring lithography processes for defining the position and adjusting the finally obtained size of the air gaps. Consequently, appropriate dielectric materials may be used, while nevertheless providing a reduced overall permittivity, at least within critical device regions, so that the overall handling of the metallization layer during the various manufacturing processes may be enhanced, while at the same time providing a desired low permittivity. The positioning and dimensioning of the air gaps may be accomplished on the basis of deposition and etch processes, wherein the lateral size of the air gaps may be beyond the capabilities of respective lithography techniques used for forming the microstructure device under consideration. For example, a reliable and reproducible adjustment of the overall permittivity between closely spaced metal lines of semiconductor devices may be accomplished in which transistor elements may be provided in the device level having critical dimensions of 50 nm and significantly less, such as 30 nm and less.
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
1. A method, comprising:
- forming a recess in a dielectric material of a metallization layer of a semiconductor device, said recess extending between two neighboring metal regions formed in said dielectric material;
- forming a spacer element on sidewalls of said recess; and
- forming a gap between said two neighboring metal regions by using said spacer element as an etch mask.
2. The method of claim 1, further comprising forming a cap layer above said gap so as to maintain at least a portion of said gap as a dielectric barrier between said two neighboring metal regions.
3. The method of claim 1, wherein forming said recess comprises performing an etch process to remove material of said dielectric material selectively to said two neighboring metal regions.
4. The method of claim 1, further comprising providing a first etch control layer in said dielectric material to adjust a depth of said recess.
5. The method of claim 1, further comprising providing a second etch control layer in said dielectric material to adjust a depth of said gap.
6. The method of claim 1, further comprising removing said spacer element after forming said gap.
7. The method of claim 1, further comprising forming a mask to expose a first device region and cover a second device region, wherein said first device region comprises a space between said two neighboring metal regions.
8. The method of claim 1, wherein forming said spacer element comprises forming an etch stop layer above said dielectric material after forming said recess and forming a spacer layer on said etch stop layer.
9. The method of claim 8, wherein said etch stop layer comprises a barrier material for suppressing metal diffusion.
10. The method of claim 8, wherein said etch stop layer comprises a conductive material.
11. The method of claim 10, further comprising removing portions of said etch stop layer not covered by said spacer element.
12. The method of claim 1, wherein forming said spacer element comprises depositing a conductive material and anisotropically etching said conductive material so as to obtain said spacer element.
13. A method comprising:
- forming a recess between a first metal line and a second metal line, said first and second metal lines formed in a dielectric material of a metallization layer of a microstructure device;
- defining a reduced width of said recess by depositing a spacer layer into said recess; and
- forming a gap between said first and second metal lines on the basis of said reduced width.
14. The method of claim 13, wherein defining said reduced width comprises forming a spacer element in said recess.
15. The method of claim 13, wherein forming said gap comprises performing an anisotropic etch process and using said spacer layer as an etch mask.
16. The method of claim 15, wherein said performing said anisotropic etch process comprises removing material of said spacer layer and said dielectric material of said metallization layer in a common process.
17. The method of claim 14, further comprising removing said spacer element after forming said gap.
18. The method of claim 13, further comprising covering a portion of said metallization layer by an etch mask and forming said gap in a non-covered portion of said metallization layer.
19. The method of claim 13, further comprising depositing a dielectric cap layer above said metallization layer after forming said gap to maintain at least a portion of said gap for reducing capacitive coupling between said first and second metal lines.
20. A microstructure device, comprising:
- a first metal line formed in a dielectric material of a metallization layer;
- a second metal line formed in the dielectric material of said metallization layer laterally adjacent to said first metal line;
- an air gap located in said dielectric material between said first and second metal lines;
- a first spacer element formed at a portion of a first sidewall of said first metal line that faces a second sidewall of said second metal line; and
- a second spacer element formed at a portion of said second sidewall of said second metal line.
21. The device of claim 20, wherein said first and second spacer elements do not extend along the entire thickness of said first and second metal lines.
22. The device of claim 21, wherein said first and second spacer elements extend from a height level corresponding to a top surface of said first and second metal lines to less than half a thickness of said first and second metal lines.
23. The device of claim 20, further comprising at least some metal lines that are formed in said dielectric material of said metallization layer without an adjacent air gap.
24. The device of claim 20, further comprising transistor elements having a gate length of approximately 30 nm or less.
25. The device of claim 24, wherein a lateral size of said air gap is less than a gate length of said transistor elements.
International Classification: H01L 23/58 (20060101); H01L 21/764 (20060101);