Having Air-gap Dielectric (e.g., Groove, Etc.) Patents (Class 438/421)
  • Patent number: 10522549
    Abstract: Provided herein are approaches for forming a gate dielectric layer for a DRAM device, the method including providing a substrate having a recess formed therein, the recess including a sidewall surface and a bottom surface. The method may further include performing an ion implant into just the bottom surface of the recess, and forming a gate dielectric layer along the bottom surface of the recess and along the sidewall surface of the recess. Once formed, a thickness of the gate dielectric layer along the sidewall surface is approximately the same as a thickness of the gate dielectric layer along the bottom surface of the recess. In some embodiments, the gate dielectric layer is thermally grown within the recess. In some embodiments, the ion implant is performed after a mask layer atop the substrate is removed.
    Type: Grant
    Filed: February 17, 2018
    Date of Patent: December 31, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Baonian Guo, Qintao Zhang
  • Patent number: 10504915
    Abstract: An integrated circuit device includes a first insulating film, a second insulating film provided on the first insulating film, and having a composition different from a composition of the first insulating film, a first interconnect extending in a first direction crossing a vertical direction, and having a lower portion disposed in the first insulating film, and an upper portion disposed in the second insulating film, and a second interconnect extending in the first direction, and having a lower portion disposed in the first insulating film, and an upper portion disposed in the second insulating film. An air gap is formed in the first insulating film and in the second insulating film and also between the first interconnect and the second interconnect. A lower end of the air gap is located lower than a lower surface of the first interconnect and a lower surface of the second interconnect.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: December 10, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Masayoshi Tagami
  • Patent number: 10340181
    Abstract: A method of forming a semiconductor structure is provided. A conductive layer is formed over a substrate. The conductive layer is selectively etched to form a first conductive portion, a second conductive portion, and a spacing between the first conductive portion and the second conductive portion. A dielectric layer is formed over the first conductive portion, the second conductive portion, and the spacing, such that an air gap is formed in the spacing between the first and second conductive portions and is sealed by the dielectric layer.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: July 2, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-I Yang, Wei-Chen Chu, Hsin-Ping Chen, Chih-Wei Lu, Chung-Ju Lee
  • Patent number: 10332800
    Abstract: A method is presented for forming a semiconductor structure. The method includes forming a plurality of fins over a source/drain region, forming a first spacer within troughs defined by the plurality of fins and depositing a high-k dielectric layer, a work function material layer, and a conducting layer. The method further includes etching the high-k dielectric layer, the work function material layer, and the conducting layer to form recesses between the plurality of fins, depositing a liner dielectric, and etching portions of the liner dielectric to form a plurality of second spacers having a U-shaped configuration. The method further includes forming an epitaxial layer over the plurality of fins such that a gap region is defined between the plurality of second spacers and the epitaxial layer.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10211091
    Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: February 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myeong-Dong Lee, Keunnam Kim, Dongryul Lee, Minseong Choi, Jimin Choi, Yong Kwan Kim, Changhyun Cho, Yoosang Hwang
  • Patent number: 10096603
    Abstract: A method of fabricating a semiconductor device includes forming first cell patterns on a substrate, forming a first layer relative to the first cell patterns, and forming a second cell pattern and a peripheral pattern on the first layer. The second cell pattern includes first holes in a cell region and the peripheral pattern is located in a peripheral region. The method also includes filling the first holes, removing the second cell pattern to expose pillars, and forming second holes. Each of the second holes corresponds to adjacent cell spacers of the pillars. The method also includes removing the pillars to form third holes corresponding to respective ones of the cell spacers, and etching the substrate using the cell spacers, the first cell patterns, and the peripheral pattern as etch masks to form a trench.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: October 9, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Heejung Kim, Seok-Won Cho, Joonsoo Park, SoonMok Ha
  • Patent number: 10032676
    Abstract: A method is presented for forming a semiconductor structure. The method includes forming a plurality of fins over a source/drain region, forming a first spacer within troughs defined by the plurality of fins and depositing a high-k dielectric layer, a work function material layer, and a conducting layer. The method further includes etching the high-k dielectric layer, the work function material layer, and the conducting layer to form recesses between the plurality of fins, depositing a liner dielectric, and etching portions of the liner dielectric to form a plurality of second spacers having a U-shaped configuration. The method further includes forming an epitaxial layer over the plurality of fins such that a gap region is defined between the plurality of second spacers and the epitaxial layer.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: July 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 9997521
    Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: June 12, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Nam-Gun Kim, Joonkyu Rhee, Ji-Hye Lee, Chanmi Lee, Taeseop Choi
  • Patent number: 9991200
    Abstract: A device comprises a first protection layer over sidewalls and a bottom of a first trench in a first dielectric layer, a first barrier layer over the first protection layer, a first metal line in the first trench, a second protection layer over sidewalls and a bottom of a second trench in the first dielectric layer, a second barrier layer over the second protection layer, a second metal line in the first trench, an air gap between the first trench and the second trench and a third protection layer over sidewalls of a third trench in the first dielectric layer, wherein the first protection layer, the second protection layer and the third protection are formed of a same material.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: June 5, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yuan Ting, Jyu-Horng Shieh
  • Patent number: 9728604
    Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: August 8, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Nam Kim, Rak-Hwan Kim, Byung-Hee Kim, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee, Jong-Jin Lee, Ho-Yun Jeon, Eun-Ji Jung
  • Patent number: 9627253
    Abstract: A semiconductor device including air gaps and a method of fabricating the same. The semiconductor device in accordance with an embodiment may include a bit line structure having a bit line formed over a first contact plug, a second contact plug formed adjacent to the first contact plug and the bit line structure, an air gap structure comprising two or more air gaps to surround the second contact plug and have an outer sidewall in contact with the bit line structure, and one or more capping support layers separating the air gaps, a third contact plug capping a part of the air gap structure and being formed over the second contact plug, and a capping layer for capping a remainder of the air gap structure.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: April 18, 2017
    Assignee: SK Hynix Inc.
    Inventor: Min-Ho Kim
  • Patent number: 9576847
    Abstract: Methods for forming integrated circuit structures are provided. The method includes providing a substrate including a first diffusion region, a second diffusion region, and an isolation structure separating the first diffusion region and the second diffusion region. The method further includes forming a gate structure over the substrate and forming an inter-layer dielectric (ILD) layer over the substrate. The method further includes forming a cutting mask over a portion of the gate structure over the isolation structure, and the cutting mask has an extending portion covering a portion of the ILD layer. The method further includes forming a photoresist layer having an opening, and a portion of the extending portion of the cutting mask is exposed by the opening. The method further includes etching the ILD layer through the opening to form a trench and filling the trench with a conductive material to form a contact.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Ying Lin, Mei-Yun Wang, Hsien-Cheng Wang, Shih-Wen Liu, Fu-Kai Yang, Audrey Hsiao-Chiu Hsu
  • Patent number: 9564355
    Abstract: An interconnect and a method of forming an interconnect for a semiconductor device is provided. Conductive lines having different widths are formed. Wider conductive lines are used where the design includes an overlying via, and narrower lines are used in which an overlying via is not included. An overlying dielectric layer is formed and trenches and vias are formed extending through the overlying dielectric layer to the wider conductive lines. Voids or air gaps may be formed adjacent select conductive lines, such as the narrower lines.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: February 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chih-Yuan Ting
  • Patent number: 9356073
    Abstract: A semiconductor device including air gaps and a method of fabricating the same. The semiconductor device in accordance with an embodiment may include a bit line structure having a bit line formed over a first contact plug, a second contact plug formed adjacent to the first contact plug and the bit line structure, an air gap structure comprising two or more air gaps to surround the second contact plug and have an outer sidewall in contact with the bit line structure, and one or more capping support layers separating the air gaps, a third contact plug capping a part of the air gap structure and being formed over the second contact plug, and a capping layer for capping a remainder of the air gap structure.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: May 31, 2016
    Assignee: SK Hynix Inc.
    Inventor: Min-Ho Kim
  • Patent number: 9269609
    Abstract: A device includes a semiconductor substrate, a contact plug over the semiconductor substrate, and an Inter-Layer Dielectric (ILD) layer over the semiconductor substrate, with the contact plug being disposed in the ILD. An air gap is sealed by a portion of the ILD and the semiconductor substrate. The air gap forms a full air gap ring encircling a portion of the semiconductor substrate.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: February 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hong-Seng Shue, Tai-I Yang, Wei-Ding Wu, Ming-Tai Chung, Shao-Chi Yu
  • Patent number: 9214377
    Abstract: Embodiments of the present invention provide a methods for forming silicon recess structures in a substrate with good process control, particularly suitable for manufacturing three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of forming recess structures in a substrate includes etching a first portion of a substrate defined by a second portion formed in the substrate until a doping layer formed in the substrate is exposed.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: December 15, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Ying Zhang, Hua Chung, Srinivas D. Nemani, Ludovic Godet
  • Patent number: 9171852
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a plurality of memory cells, each of the memory cells including a tunneling insulating film provided on a substrate including silicon, a floating gate provided on the tunneling insulating film, an inter-gate insulating film provided on the floating gate, and a control gate provided on the inter-gate insulating film; and an element separation trench provided between the plurality of memory cells, the element separation trench having a gap in an interior of the element separation trench. The inter-gate insulating film is provided also above the element separation trench. An upper end of the gap is provided in an interior of the inter-gate insulating film provided above the element separation trench.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: October 27, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Muneyuki Tsuda
  • Patent number: 9117879
    Abstract: A semiconductor device includes a first semiconductor chip comprising a first metallic structure, a top surface, and a bottom surface, a second semiconductor chip comprising a second metallic structure, wherein the second semiconductor chip is bonded with the first semiconductor chip on the bottom surface, a conductive material connecting the first metallic structure and the second metallic structure, wherein a portion of the conductive material is inside the first semiconductor chip and the second semiconductor chip, and a dielectric layer disposed surrounding the portion of the conductive material.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: August 25, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheng-Ying Ho, Wen-De Wang, Jen-Cheng Liu, Dun-Nian Yaung
  • Patent number: 9048192
    Abstract: A method of forming a pattern includes forming a mask pattern on a substrate; etching the substrate by deep reactive ion etching (DRIE) and by using the mask pattern as an etch mask; partially removing the mask pattern to expose a portion of an upper surface of the substrate; and etching the exposed portion of the upper surface of the substrate. In the method, when a pattern is formed by DRIE, an upper portion of the pattern does not protrude or scarcely protrudes, and scallops of a sidewall of the pattern are smooth, and thus a conformal material layer may be easily formed on a surface of the pattern.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: June 2, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-kwon Kim, Ki-il Kim, Ah-young Cheon, Myeong-cheol Kim, Yong-jin Kim
  • Patent number: 9041122
    Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device. In order to improve reliability by solving a problem of conductivity that may occur when an air spacer structure that may reduce a capacitor coupling phenomenon between a plurality of conductive lines is formed, there are provided a semiconductor device including: a substrate having an active region; a contact plug connected to the active region; a landing pad spacer formed to contact a top surface of the contact plug; a contact conductive layer formed to contact the top surface of the contact plug and formed in a space defined by the landing pad spacer; a metal silicide layer formed on the contact conductive layer; and a landing pad connected to the contact conductive layer in a state in which the metal silicide layer is disposed between the landing pad and the contact conductive layer, and a method of manufacturing the semiconductor device.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: May 26, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-seok Yoo, Young-seok Kim, Han-jin Lim, Jeon-Il Lee
  • Patent number: 9035419
    Abstract: A semiconductor device including a substrate having a trench formed therein, a plurality of gate structures, an isolation layer pattern and an insulating interlayer pattern. The substrate includes a plurality of active regions defined by the trench and spaced apart from each other in a second direction. Each of the active regions extends in a first direction substantially perpendicular to the second direction. Each of the plurality of gate structures includes a tunnel insulation layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially stacked on the substrate. The isolation layer pattern is formed in the trench. First isolation layer pattern has at least one first air gap between sidewalls of at least one adjacent pair of the floating gates. The insulating interlayer pattern is formed between the gate structures, and the first insulating interlayer pattern extends in the second direction.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: May 19, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Woo Oh, Dae-Sin Kim, Young-Kwan Park, Keun-Ho Lee, Seon-Young Lee
  • Patent number: 9024390
    Abstract: The present invention aims to relax stress induced by through-silicon via formed on semiconductor substrate in order to prevent property fluctuation of a transistor. A semiconductor device includes a semiconductor substrate, a through-silicon via formed in semiconductor substrate, an insulating film formed between the semiconductor substrate and the through-silicon via, and a transistor formed on the semiconductor substrate so as to be apart from the through-silicon via with a predetermined distance. The insulating film does not exist on a region close to a surface of the semiconductor substrate between the semiconductor substrate and the through-silicon via. A gap is formed to be surrounded by the semiconductor substrate, the through silicon via, and the insulating film under the region close to the surface of the semiconductor substrate.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: May 5, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Hiroki Miyajima
  • Publication number: 20150115398
    Abstract: A method of manufacturing a semiconductor device may include: forming an interlayer insulating layer having openings on a substrate; forming a metal layer in the openings and on the interlayer insulating layer, the metal layer including a sidewall portion on a sidewall of each of the openings and a bottom portion on a bottom surface of each of the openings, wherein the bottom portion is thicker than the sidewall portion; reflowing the metal layer to form metal patterns in the openings, the metal patterns having top surfaces at a level lower than a topmost surface of the interlayer insulating layer; and/or forming capping patterns covering the metal patterns in the openings.
    Type: Application
    Filed: August 6, 2014
    Publication date: April 30, 2015
    Inventors: Euibok LEE, Jongmin BAEK, Dohyoung KIM, Tsukasa MATSUDA, Youngwoo CHO, Jongseo HONG
  • Patent number: 9006078
    Abstract: A method of fabricating a semiconductor device and a semiconductor device formed by the method. The method includes form a stack conductive structure by stacking a first conductive pattern and an insulation pattern over a substrate; forming a sacrificial pattern over sidewalls of the stack conductive structure; forming a second conductive pattern having a recessed surface lower than a top surface of the stack conductive structure; forming a sacrificial spacer to expose sidewalls of the insulation pattern by removing an upper portion of the sacrificial pattern; reducing a width of the exposed portion of the insulation patters; forming a capping spacer to cap the sidewalls of the insulation pattern having the reduced width over the sacrificial spacer; and forming an air gap between the first conductive pattern and the second conductive pattern by converting the sacrificial spacer to volatile byproducts.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: April 14, 2015
    Assignee: SK Hynix Inc.
    Inventor: Myung-Ok Kim
  • Patent number: 9006077
    Abstract: Methods for fabricating integrated circuits and FinFET transistors on bulk substrates with active channel regions isolated from the substrate with an insulator are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit includes forming fin structures overlying a semiconductor substrate, wherein each fin structure includes a channel material and extends in a longitudinal direction from a first end to a second end. The method deposits an anchoring material over the fin structures. The method includes recessing the anchoring material to form trenches adjacent the fin structures, wherein the anchoring material remains in contact with the first end and the second end of each fin structure. Further, the method forms a void between the semiconductor substrate and the channel material of each fin structure with a gate length independent etching process, wherein the channel material of each fin structure is suspended over the semiconductor substrate.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: April 14, 2015
    Assignee: GlobalFoundries, Inc.
    Inventors: Murat Kerem Akarvardar, Ajey Poovannummoottil Jacob
  • Publication number: 20150099343
    Abstract: A semiconductor memory device includes a plurality of auxiliary patterns formed over a semiconductor substrate, a plurality of gate line patterns disposed in parallel with one another over the semiconductor substrate between the plurality of auxiliary patterns, and an air gap formed between the plurality of gate line patterns and between each of the plurality of gate line patterns and each of the auxiliary patterns.
    Type: Application
    Filed: December 12, 2014
    Publication date: April 9, 2015
    Inventors: Tae Kyung KIM, Hyun Yul KWON
  • Patent number: 8999839
    Abstract: A method of manufacturing a semiconductor structure, the method includes removing a portion of a dielectric filler from a first metal-containing layer formed over a semiconductor substrate to define an air-gap region according to a predetermined air-gap pattern. The method further includes filling the air-gap region with a decomposable filler and forming a dielectric capping layer over the first metal-containing layer. The method further includes decomposing the decomposable filler.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Hui Su, Cheng-Lin Huang, Jiing-Feng Yang, Zhen-Cheng Wu, Ren-Guei Wu, Dian-Hau Chen, Yuh-Jier Mii
  • Publication number: 20150087132
    Abstract: Semiconductor device and method for forming a semiconductor device are presented. A substrate having top and bottom pad stacks is provided. Each pad stack includes at least first and second pad layers. The second pad layer of the bottom pad stack is removed by a batch process. Trench isolation regions are formed in the substrate.
    Type: Application
    Filed: September 20, 2013
    Publication date: March 26, 2015
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventor: Guowei ZHANG
  • Patent number: 8987860
    Abstract: A semiconductor device includes a substrate having a plurality of active regions defined by a device isolation region, a plurality of conductive patterns on the plurality of active regions, each of the conductive patterns having side walls, a conductive line that faces the side walls of the conductive patterns with an air spacer therebetween on the active regions, the conductive line extending in a first direction, and a first insulating film covering the side walls of the conductive patterns between the air spacer and the conductive pattern. A lower portion of the first insulating film that is near the substrate protrudes toward the air spacer.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bo-young Song, Cheol-ju Yun, Seung-hee Ko
  • Patent number: 8987854
    Abstract: A microelectronic device is provided, including: a substrate including a first semiconductor layer positioned on a dielectric layer and a second semiconductor layer; and an isolation trench disposed through the first semiconductor layer, the dielectric layer, and a part of the thickness of the second semiconductor layer, including a dielectric material and delimiting, in the first semiconductor layer, a roughly rectangular active area of the device, wherein in said part of the thickness of the second semiconductor layer, at least one portion of the dielectric material is positioned under the active area delimited by at least four side walls of the trench, and two of the at least four side walls are roughly parallel with one another and are positioned under the active area, and the other two of the at least four side walls are orthogonal to said two walls and are not positioned under the active area.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: March 24, 2015
    Assignee: Commissariat a l 'energie atomique et aux energies alternatives
    Inventors: Maud Vinet, Laurent Grenouillet, Yannick Le Tiec, Romain Wacquez
  • Patent number: 8987851
    Abstract: The invention provides a radio-frequency (RF) device package and a method for fabricating the same. An exemplary embodiment of a radio-frequency (RF) device package includes a base, wherein a radio-frequency (RF) device chip is mounted on the base. The RF device chip includes a semiconductor substrate having a front side and a back side. A radio-frequency (RF) component is disposed on the front side of the semiconductor substrate. An interconnect structure is disposed on the RF component, wherein the interconnect structure is electrically connected to the RF component, and a thickness of the semiconductor substrate is less than that of the interconnect structure. A through hole is formed through the semiconductor substrate from the back side of the semiconductor substrate, and is connected to the interconnect structure. A TSV structure is disposed in the through hole.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: March 24, 2015
    Assignee: MediaTek Inc.
    Inventors: Ming-Tzong Yang, Cheng-Chou Hung, Tung-Hsing Lee, Wei-Che Huang, Yu-Hua Huang
  • Patent number: 8975684
    Abstract: Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: March 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hwang Sim, Jinhyun Shin, HoJun Seong
  • Patent number: 8975129
    Abstract: A method of fabricating a fin-like field-effect transistor (FinFET) device is disclosed. A plurality of mandrel features are formed on a substrate. First spacers are formed along sidewalls of the mandrel feature and second spacers are along sidewalls of the first spacers. Two back-to-back adjacent second spacers separate by a gap in a first region and merge together in a second region of the substrate. A dielectric feature is formed in the gap and a dielectric mesa is formed in a third region of the substrate. A first subset of the first spacer is removed in a fine cut. Fins and trenches are formed by etching the substrate using the first spacer and the dielectric feature as an etch mask.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Feng Shieh, Hung-Chang Hsieh, Chen-Yu Chen
  • Patent number: 8962443
    Abstract: A method of forming a device having an airbridge on a substrate includes forming a plated conductive layer of the airbridge over at least a photoresist layer on a portion of the substrate, the plated conductive layer defining a corresponding opening for exposing a portion of the photoresist layer. The method further includes undercutting the photoresist layer to form a gap in the photoresist layer beneath the plated conductive layer at the opening, and forming an adhesion layer on the plated conductive layer and the exposed portion of the photoresist layer, the adhesion layer having a break at the gap beneath the plated conductive layer. The photoresist layer and a portion of the adhesion layer formed on the exposed portion of the photoresist layer is removed, which includes etching the photoresist layer through the break in the adhesion layer. An insulating layer is formed on at least the adhesion layer, enhancing adhesion of the insulating layer to the plated conductive layer.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: February 24, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Timothy J. Whetten, Wayne P. Richling
  • Patent number: 8962472
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of semiconductor structures over a substrate, forming an interlayer dielectric layer over the semiconductor structures, etching the interlayer dielectric layer, and defining open parts between the semiconductor structures to expose a surface of the substrate, forming sacrificial spacers on sidewalls of the open parts, forming conductive layer patterns in the open parts, and causing the conductive layer patterns and the sacrificial spacers to reach each other, and defining air gaps on the sidewalls of the open parts.
    Type: Grant
    Filed: March 16, 2013
    Date of Patent: February 24, 2015
    Assignee: SK Hynix Inc.
    Inventors: Il-Cheol Rho, Jong-Min Lee
  • Patent number: 8956949
    Abstract: Disclosed are a structure for electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure includes a trench extending through the top semiconductor layer and into a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a void is disposed in the handle wafer below the trench. A bottom opening of the trench connects the main body of the trench with the void forming a continuous cavity including the main body, the bottom opening of the trench, and the void such that the void improves electrical signal isolation between the adjacent devices situated in the top semiconductor layer. Unetched portions of the handle wafer are then available to provide mechanical support to the top semiconductor layer.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: February 17, 2015
    Assignee: Newport Fab, LLC
    Inventors: Paul D. Hurwitz, Robert L. Zwingman
  • Patent number: 8951881
    Abstract: A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Sik Lee, Jang-Hyun You, Jee-Hoon Han, Young-Woo Park, Sung-Hoi Hur, Sang-Ick Joo
  • Patent number: 8946048
    Abstract: High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between control gates and charge storage regions is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: February 3, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Vinod Robert Purayath, George Matamis, Henry Chien, James Kai, Yuan Zhang
  • Patent number: 8941204
    Abstract: A method for reducing cross talk in image sensors comprises providing a backside illuminated image sensor wafer, forming an isolation region in the backside illuminated image sensor wafer, wherein the isolation region encloses a photo active region, forming an opening in the isolation region from a backside of the backside illuminated image sensor wafer and covering an upper terminal of the opening with a dielectric material to form an air gap embedded in the isolation region of the backside illuminated image sensor wafer.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Shuang-Ji Tsai, Min-Feng Kao
  • Patent number: 8937366
    Abstract: An embodiment of the present disclosure is directed to a semiconductor device. The semiconductor devise comprises a substrate. An epitaxially grown semiconductor material is disposed over at least a portion of the substrate. A nanotemplate structure is disposed at least partially within the semiconductor material. The nanotemplate structure comprises a plurality of dielectric nanoscale features defining a plurality of nanoscale windows. An air gap is disposed between at least a portion of one or more of the nanoscale features and the semiconductor material.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: January 20, 2015
    Assignee: STC.UNM
    Inventors: Sang M. Han, Darin Leonhardt, Swapnadip Ghosh
  • Patent number: 8916467
    Abstract: A doped contact region having an opposite conductivity type as a bottom semiconductor layer is provided underneath a buried insulator layer in a bottom semiconductor layer. At least one conductive via structure extends from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer and to the doped contact region. The doped contact region is biased at a voltage that is at or close to a peak voltage in the RF switch that removes minority charge carriers within the induced charge layer. The minority charge carriers are drained through the doped contact region and the at least one conductive via structure. Rapid discharge of mobile electrical charges in the induce charge layer reduces harmonic generation and signal distortion in the RF switch. A design structure for the semiconductor structure is also provided.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Botula, Alvin J. Joseph, Edward J. Nowak, Yun Shi, James A. Slinkman
  • Publication number: 20140363950
    Abstract: The present invention is a process for forming an air gap within a substrate, the process comprising: providing a substrate; depositing a sacrificial material by deposition of at least one sacrificial material precursor; depositing a composite layer; removal of the porogen material in the composite layer to form a porous layer and contacting the layered substrate with a removal media to substantially remove the sacrificial material and provide the air gaps within the substrate; wherein the at least one sacrificial material precursor is selected from the group consisting of: an organic porogen; silicon, and a polar solvent soluble metal oxide and mixtures thereof.
    Type: Application
    Filed: July 3, 2014
    Publication date: December 11, 2014
    Inventors: Raymond Nicholas Vrtis, Dingjun Wu, Mark Leonard O'Neill, Mark Daniel Bitner, Jean Louise Vincent, Eugene Joseph Karwacki, JR., Aaron Scott Lukas
  • Patent number: 8901701
    Abstract: A chip package is disclosed. The package includes a semiconductor chip having a first surface and a second surface opposite thereto, at least one conductive pad adjacent to the first surface, and an opening extending toward the first surface from the second surface to expose the conductive pad. The caliber adjacent to the first surface is greater than that of the opening adjacent to the second surface. An insulating layer and a redistribution layer (RDL) are successively disposed on the second surface and extend to a sidewall and a bottom of the opening, in which the RDL is electrically connected to the conductive pad through the opening. A passivation layer covers the RDL and partially fills the opening to form a void between the passivation layer and the conductive pad in the opening. A fabrication method of the chip package is also disclosed.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: December 2, 2014
    Inventor: Chia-Sheng Lin
  • Patent number: 8883611
    Abstract: Semiconductor devices, and methods of fabricating the same, include forming a trench between a plurality of patterns on a substrate to be adjacent to each other, forming a first sacrificial layer in the trench, forming a first porous insulation layer having a plurality of pores on the plurality of patterns and on the first sacrificial layer, and removing the first sacrificial layer through the plurality of pores of the first porous insulation layer to form a first air gap between the plurality of patterns and under the first porous insulation layer.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Bo-Young Lee, Jongwan Choi, Myoungbum Lee
  • Patent number: 8878332
    Abstract: A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: November 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Hoon Na, Young-Woo Park, Dong-Hwa Kwak, Tae-Yong Kim, Jee-Hoon Han, Jang-Hyun You, Dong-Sik Lee, Su-Jin Park
  • Patent number: 8871606
    Abstract: Integrated circuit (1) comprising a substrate (2), an active component (13) above the substrate (2), a cavity (14) surrounding partially the active component (13), a low dielectric region (15) surrounding partially the cavity (14) and a protective barrier (16) arranged around the low dielectric region (15).
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: October 28, 2014
    Assignees: STMicroelectronics (Crolles 2) SAS, Koninklijke Philips Electronics, N.V.
    Inventors: Clement Charbuillet, Laurent Gosset
  • Publication number: 20140295641
    Abstract: A semiconductor memory device includes a semiconductor substrate in which an active region and an isolation region are defined, a tunnel insulating layer and a floating gate formed on the semiconductor substrate in the active region, a trench formed in the semiconductor substrate in the isolation region, a dielectric layer formed along a top surface and a portion of a side surface of the floating gate, wherein the dielectric layer extends higher than a surface of the semiconductor substrate in the isolation region and defines an air gap in the trench, and a control gate formed on the dielectric layer, wherein the dielectric layer includes the first nitride layer, a first oxide layer, a second nitride layer and a second oxide layer.
    Type: Application
    Filed: June 18, 2014
    Publication date: October 2, 2014
    Inventors: Jung Il CHO, Jong Moo CHOI, Eun Joo JUNG
  • Patent number: 8835279
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device is provided. In the method, a tunnel insulating film and a first conductive film are formed on a semiconductor layer. A trench is formed. A first sacrifice film is buried in the trench. A second sacrifice film having density higher than that of the first sacrifice film is formed on the first sacrifice film in the trench. An insulating film is formed on the first conductive film and the second sacrifice film. A second conductive film is formed on the insulating film. The second sacrifice film is exposed. The first sacrifice film and the second sacrifice film are removed.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keisuke Nakazawa
  • Patent number: 8829596
    Abstract: The nonvolatile memory device includes a semiconductor layer including trenches formed in a first direction, isolation layers filling the trenches, and active regions divided by the isolation layer, first insulating patterns formed on the semiconductor substrate in a second direction crossing the first direction, charge storage layer patterns formed over the respective active regions between the first insulating patterns, and second insulating patterns formed on the isolation layers between the charge storage layer patterns.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: September 9, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jong Man Kim
  • Patent number: RE45507
    Abstract: An integrated circuit includes electrical components that include one or more electrical elements on one or more dielectric layers. The electrical element has a geometric shape that exceeds prescribed integrated circuit manufacturing limits in at least one dimension. To achieve compliance with foundry rules, the electrical element is fabricated to include a non-conducting region that negligibly effects the electrical characteristics. The non-conducting region includes a hole, a series of holes, a slot and/or a series of slots spaced within the electrical element at dimensions that are less than the integrated circuit manufacturing limits.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: May 5, 2015
    Assignee: Broadcom Corporation
    Inventors: Harry Contopanagos, Christos Komninakis