Air Gaps (epo) Patents (Class 257/E21.573)
  • Patent number: 10160642
    Abstract: MEMS structures and methods utilizing a locker film are provided. In an embodiment a locker film is utilized to hold and support a moveable mass region during the release of the moveable mass region from a surrounding substrate. By providing additional support during the release of the moveable mass, the locker film can reduce the amount of undesired movement that can occur during the release of the moveable mass, and preventing undesired etching of the sidewalls of the moveable mass.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Hau Wu, Kuei-Sung Chang
  • Patent number: 10109519
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A conductive feature over a substrate is provided. A first dielectric layer is deposited over the conductive feature and the substrate. A via-forming-trench (VFT) is formed in the first dielectric layer to expose the conductive feature and the substrate around the conductive feature. The VFT is filled in by a sacrificial layer. A via-opening is formed in the sacrificial layer to expose the conductive feature. A metal plug is formed in the via-opening to connect to the conductive feature. The sacrificial layer is removed to form a surrounding-vacancy around metal plug and the conductive feature. A second dielectric layer is deposited over the substrate to seal a portion of the surrounding-vacancy to form an enclosure-air-gap all around the metal plug and the conductive feature.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: October 23, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiang-Lun Kao, Tien-Lu Lin, Yung-Chih Wang, Cheng-Chi Chuang
  • Patent number: 10096515
    Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: October 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Chih-Hui Huang, Sheng-Chau Chen, Shih-Pei Chou, Chia-Chieh Lin
  • Patent number: 9923010
    Abstract: The present technology relates to a solid-state imaging device, manufacturing method of a solid-state imaging device, and an electronic device, which can provide a solid-state imaging device having further improved features such as reduced optical color mixing and the like. Also, an electronic device using the solid-state imaging device thereof is provided. According to a solid-state imaging device having a substrate and multiple photoelectric converters that are formed on the substrate, an insulating film forms an embedded element separating unit. The element separating unit is configured of an insulating film having a fixed charge that is formed so as to coat the inner wall face of a groove portion, within the groove portion which is formed in the depth direction from the light input side of the substrate.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: March 20, 2018
    Assignee: Sony Corporation
    Inventors: Takeshi Yanagita, Itaru Oshiyama, Takayuki Enomoto, Harumi Ikeda, Shinichiro Izawa, Atsuhiko Yamamoto, Kazunobu Ota
  • Patent number: 9536777
    Abstract: A method comprises bonding a first chip on a second chip, depositing a first hard mask layer over a non-bonding side of the first chip, depositing a second hard mask layer over the first hard mask layer, etching a first substrate of the first semiconductor chip using the second hard mask layer as a first etching mask and etching the IMD layers of the first chip and the second chip using the first hard mask layer as a second etching mask.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacutring Company, Ltd.
    Inventors: Jeng-Shyan Lin, Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Shih Pei Chou, Min-Feng Kao, Szu-Ying Chen
  • Patent number: 9508810
    Abstract: A semiconductor device and method of forming a semiconductor device including a semiconductor substrate, a gate stack extending from the semiconductor substrate, wherein the gate stack includes a gate conductor layer, and at least two gate spacers adjacent to each side of the gate stack. The semiconductor device also includes a source/drain region on each side of the spacers, wherein the source/drain regions are adjacent to the semiconductor substrate, an ILD layer adjacent to outer surfaces of the two spacers, wherein a height of the ILD layer is level with a height of the gate stack, and an air gap positioned beneath each spacer.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: November 29, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9437524
    Abstract: Embodiments of the present invention provide a novel process integration for air gap formation at the sidewalls for a Through Silicon Via (TSV) structure. The sidewall air gap formation scheme for the TSV structure of disclosed embodiments reduces parasitic capacitance and depletion regions in between the substrate silicon and TSV conductor, and serves to also reduce mechanical stress in silicon substrate surrounding the TSV conductor.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: September 6, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shan Gao, Seung Man Choi
  • Patent number: 9312167
    Abstract: Methods for reducing the k value of a layer using air gaps and devices produced by said methods are disclosed herein. Methods disclosed herein can include depositing a carbon containing stack over one or more features in a substrate, depositing a porous dielectric layer over the carbon containing stack, and curing the substrate to volatilize the carbon containing stack. The resulting device includes a substrate with one or more features formed therein, a porous dielectric layer formed over the features with an air gap formed in the features.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: April 12, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Taewan Kim, Kang Sub Yim, Alexandros T. Demos
  • Patent number: 9281277
    Abstract: A wiring structure includes a first insulation layer, a plurality of wiring patterns, a protection layer pattern and a second insulation layer. The first insulation layer may be formed on a substrate. A plurality of wiring patterns may be formed on the first insulation layer, and each of the wiring patterns may include a metal layer pattern and a barrier layer pattern covering a sidewall and a bottom surface of the metal layer pattern. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: March 8, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Min Baek, Sang-Ho Rha, Woo-Kyung You, Sang-Hoon Ahn, Nae-In Lee, Ki-Chul Kim, Jeon-Il Lee
  • Patent number: 9041122
    Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device. In order to improve reliability by solving a problem of conductivity that may occur when an air spacer structure that may reduce a capacitor coupling phenomenon between a plurality of conductive lines is formed, there are provided a semiconductor device including: a substrate having an active region; a contact plug connected to the active region; a landing pad spacer formed to contact a top surface of the contact plug; a contact conductive layer formed to contact the top surface of the contact plug and formed in a space defined by the landing pad spacer; a metal silicide layer formed on the contact conductive layer; and a landing pad connected to the contact conductive layer in a state in which the metal silicide layer is disposed between the landing pad and the contact conductive layer, and a method of manufacturing the semiconductor device.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: May 26, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-seok Yoo, Young-seok Kim, Han-jin Lim, Jeon-Il Lee
  • Patent number: 9035462
    Abstract: An interconnect structure is provided that includes at least one patterned and cured low-k dielectric material located on a surface of a patterned inorganic antireflective coating that is located atop a substrate. The inorganic antireflective coating comprises atoms of M, C and H wherein M is at least one of Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La. The at least one cured and patterned low-k dielectric material and the patterned inorganic antireflective coating have conductively filled regions embedded therein and the at least one cured and patterned low-k dielectric material has at least one airgap located adjacent, but not directly in contact with the conductively filled regions.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: May 19, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Qinghuang Lin
  • Patent number: 9035419
    Abstract: A semiconductor device including a substrate having a trench formed therein, a plurality of gate structures, an isolation layer pattern and an insulating interlayer pattern. The substrate includes a plurality of active regions defined by the trench and spaced apart from each other in a second direction. Each of the active regions extends in a first direction substantially perpendicular to the second direction. Each of the plurality of gate structures includes a tunnel insulation layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially stacked on the substrate. The isolation layer pattern is formed in the trench. First isolation layer pattern has at least one first air gap between sidewalls of at least one adjacent pair of the floating gates. The insulating interlayer pattern is formed between the gate structures, and the first insulating interlayer pattern extends in the second direction.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: May 19, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Woo Oh, Dae-Sin Kim, Young-Kwan Park, Keun-Ho Lee, Seon-Young Lee
  • Patent number: 8999839
    Abstract: A method of manufacturing a semiconductor structure, the method includes removing a portion of a dielectric filler from a first metal-containing layer formed over a semiconductor substrate to define an air-gap region according to a predetermined air-gap pattern. The method further includes filling the air-gap region with a decomposable filler and forming a dielectric capping layer over the first metal-containing layer. The method further includes decomposing the decomposable filler.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Hui Su, Cheng-Lin Huang, Jiing-Feng Yang, Zhen-Cheng Wu, Ren-Guei Wu, Dian-Hau Chen, Yuh-Jier Mii
  • Patent number: 8962443
    Abstract: A method of forming a device having an airbridge on a substrate includes forming a plated conductive layer of the airbridge over at least a photoresist layer on a portion of the substrate, the plated conductive layer defining a corresponding opening for exposing a portion of the photoresist layer. The method further includes undercutting the photoresist layer to form a gap in the photoresist layer beneath the plated conductive layer at the opening, and forming an adhesion layer on the plated conductive layer and the exposed portion of the photoresist layer, the adhesion layer having a break at the gap beneath the plated conductive layer. The photoresist layer and a portion of the adhesion layer formed on the exposed portion of the photoresist layer is removed, which includes etching the photoresist layer through the break in the adhesion layer. An insulating layer is formed on at least the adhesion layer, enhancing adhesion of the insulating layer to the plated conductive layer.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: February 24, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Timothy J. Whetten, Wayne P. Richling
  • Patent number: 8962368
    Abstract: The present invention relates to a CMOS compatible MEMS microphone, comprising: an SOI substrate, wherein a CMOS circuitry is accommodated on its silicon device layer; a microphone diaphragm formed with a part of the silicon device layer, wherein the microphone diaphragm is doped to become conductive; a microphone backplate including CMOS passivation layers with a metal layer sandwiched and a plurality of through holes, provided above the silicon device layer, wherein the plurality of through holes are formed in the portions thereof opposite to the microphone diaphragm, and the metal layer forms an electrode plate of the backplate; a plurality of dimples protruding from the lower surface of the microphone backplate opposite to the diaphragm; and an air gap, provided between the diaphragm and the microphone backplate, wherein a spacer forming a boundary of the air gap is provided outside of the diaphragm or on the edge of the diaphragm.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: February 24, 2015
    Assignee: Goertek, Inc.
    Inventor: Zhe Wang
  • Patent number: 8956949
    Abstract: Disclosed are a structure for electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure includes a trench extending through the top semiconductor layer and into a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a void is disposed in the handle wafer below the trench. A bottom opening of the trench connects the main body of the trench with the void forming a continuous cavity including the main body, the bottom opening of the trench, and the void such that the void improves electrical signal isolation between the adjacent devices situated in the top semiconductor layer. Unetched portions of the handle wafer are then available to provide mechanical support to the top semiconductor layer.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: February 17, 2015
    Assignee: Newport Fab, LLC
    Inventors: Paul D. Hurwitz, Robert L. Zwingman
  • Patent number: 8951881
    Abstract: A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Sik Lee, Jang-Hyun You, Jee-Hoon Han, Young-Woo Park, Sung-Hoi Hur, Sang-Ick Joo
  • Patent number: 8946048
    Abstract: High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between control gates and charge storage regions is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: February 3, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Vinod Robert Purayath, George Matamis, Henry Chien, James Kai, Yuan Zhang
  • Patent number: 8941204
    Abstract: A method for reducing cross talk in image sensors comprises providing a backside illuminated image sensor wafer, forming an isolation region in the backside illuminated image sensor wafer, wherein the isolation region encloses a photo active region, forming an opening in the isolation region from a backside of the backside illuminated image sensor wafer and covering an upper terminal of the opening with a dielectric material to form an air gap embedded in the isolation region of the backside illuminated image sensor wafer.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Shuang-Ji Tsai, Min-Feng Kao
  • Patent number: 8937366
    Abstract: An embodiment of the present disclosure is directed to a semiconductor device. The semiconductor devise comprises a substrate. An epitaxially grown semiconductor material is disposed over at least a portion of the substrate. A nanotemplate structure is disposed at least partially within the semiconductor material. The nanotemplate structure comprises a plurality of dielectric nanoscale features defining a plurality of nanoscale windows. An air gap is disposed between at least a portion of one or more of the nanoscale features and the semiconductor material.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: January 20, 2015
    Assignee: STC.UNM
    Inventors: Sang M. Han, Darin Leonhardt, Swapnadip Ghosh
  • Patent number: 8921235
    Abstract: A method of forming and controlling air gaps between adjacent raised features on a substrate includes forming a silicon-containing film in a bottom region between the adjacent raised features using a flowable deposition process. The method also includes forming carbon-containing material on top of the silicon-containing film and forming a second film over the carbon-containing material using a flowable deposition process. The second film fills an upper region between the adjacent raised features. The method also includes curing the materials at an elevated temperature for a period of time to form the air gaps between the adjacent raised features. The thickness and number layers of films can be used to control the thickness, vertical position and number of air gaps.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 30, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Kiran V. Thadani, Jingjing Xu, Abhijit Basu Mallick, Joe Griffith Cruz, Nitin K. Ingle, Pravin K. Narwankar
  • Patent number: 8872304
    Abstract: A semiconductor device in which misalignment does not cause short-circuiting and inter-wiring capacitance is decreased. Plural wirings are provided in a first interlayer insulating layer. An air gap is made between at least one pair of wirings in the layer. A second interlayer insulating layer lies over the wirings and first interlayer insulating layer. The first bottom face of the second interlayer insulating layer is exposed to the air gap. When a pair of adjacent wirings whose distance is shortest are first wirings, the upper ends of the first interlayer insulating layer between the first wirings are in contact with the first wirings' side faces. The first bottom face is below the first wirings' upper faces. b/a?0.5 holds where a represents the distance between the first wirings and b represents the width of the portion of the first interlayer insulating layer in contact with the first bottom face.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: October 28, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Daisuke Oshida
  • Patent number: 8822303
    Abstract: A method of fabricating a semiconductor component that including the following steps is provided. A plurality of stacked structures is formed on a substrate. A first dielectric layer is formed to cover the stacked structures, wherein the first dielectric layer has a plurality of overhangs, the overhangs wrap top portions of the stacked structures. A dry conformable etching process is performed to conformably remove the first dielectric layer until a portion of the first dielectric layer located outside of the overhangs is removed. A second dielectric layer is formed on the stacked structures, wherein the second dielectric layer connects the adjacent overhangs to form an air gap between the stacked structures.
    Type: Grant
    Filed: September 15, 2012
    Date of Patent: September 2, 2014
    Assignee: Powerchip Technology Corporation
    Inventors: Tsu-Chiang Chen, Yu-Mei Liao, Cheng-Kuen Chen
  • Patent number: 8816472
    Abstract: According to one embodiment, a semiconductor device includes a first insulating film formed above a substrate, wires formed on the first insulating film, an air gap formed between the adjacent wires, and a second insulating film formed on the wires and the air gap. Each of the wires has a metal film formed on the first insulating film and a hard mask formed on the metal film, the hard mask has a first layer and a second layer, a second internal angle formed by the under surface and the side surface of the second layer on a cross section of the second layer is smaller than a first internal angle formed by the under surface and the side surface of the first layer on a cross section of the first layer, and the top surface of the air gap is higher than the top surface of the metal film.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Atsunobu Isobayashi
  • Patent number: 8778749
    Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Air gaps are formed at least partially in isolation regions between active areas of the substrate. The air gaps may further extend above the substrate surface between adjacent layer stack columns. A sacrificial material is formed at least partially in the isolation regions, followed by forming a dielectric liner. The sacrificial material is removed to define air gaps prior to forming the control gate layer and then etching it and the layer stack columns to form individual control gates and columns of non-volatile storage elements.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: July 15, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Jayavel Pachamuthu, Vinod R. Purayath, George Matamis
  • Patent number: 8772941
    Abstract: A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of interconnect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Matthew E. Colburn, Louis C. Hsu, Wai-Kin Li
  • Patent number: 8765573
    Abstract: A method of forming air gaps between adjacent raised features on a substrate includes forming a carbon-containing material in a bottom region between the adjacent raised features using a flowable deposition process. The method also includes forming a silicon-containing film over the carbon-containing material using a flowable deposition process, where the silicon-containing film fills an upper region between the adjacent raised features and extends over the adjacent raised features. The method also includes curing the carbon-containing material and the silicon-containing material at an elevated temperature for a period of time to form the air gaps between the adjacent raised features.
    Type: Grant
    Filed: September 10, 2011
    Date of Patent: July 1, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Abhijit Basu Mallick, Nitin Ingle
  • Patent number: 8753955
    Abstract: A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: June 17, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Sik Lee, Jang-Hyun You, Jee-Hoon Han, Young-Woo Park, Sung-Hoi Hur, Sang-Ick Joo
  • Patent number: 8742590
    Abstract: A method is provided for forming at least one TSV interconnect structure surrounded by at least one isolating trench-like structure having at least one airgap. The method comprises at least the steps of providing a substrate having a first main surface and producing simultaneous at least one a TSV hole and a trench-like structure surrounding the TSV hole and separated by remaining substrate material. The method also comprises thereafter depositing a dielectric liner in order to smoothen the sidewalls of the etched TSV hole and to pinch-off the opening of the trench-like structure at the first main surface of the substrate in order to create at least one airgap in said trench-like structure and depositing a conductive material in said TSV hole in order to create a TSV interconnect. A corresponding substrate is also provided.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: June 3, 2014
    Assignee: IMEC
    Inventor: Eric Beyne
  • Patent number: 8736061
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a standard cell having a first boundary, a second boundary opposite the first boundary, a third boundary interconnecting the first and second boundaries, and a fourth boundary opposite the third boundary and interconnecting the first and second boundaries. The standard cell further includes parallel active areas extending from the first boundary to the second boundary. Also, the standard cell has parallel gate strips extending from the third boundary to the fourth boundary and over the active areas. A cut mask overlies the gate strips. An interconnect is positioned overlying the cut mask and forms an electrical connection with a selected gate strip.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: May 27, 2014
    Assignees: GLOBALFOUNDRIES, Inc., International Business Machines, STMicroelectronics, Inc.
    Inventors: Frank Johnson, Olivier Menut, Marc Tarabbia, Gregory A. Northrop
  • Patent number: 8722508
    Abstract: A low harmonic radio-frequency (RF) switch in a silicon-on-insulator (SOI) substrate and methods of manufacture. A method includes forming at least one trench through an insulator layer. The at least one trench is adjacent a device formed in an active region on the insulator layer. The method also includes forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 13, 2014
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Botula, Dinh Dang, James S. Dunn, Alvin J. Joseph, Peter J. Lindgren
  • Patent number: 8716830
    Abstract: In one aspect of the present invention, an integrated circuit package will be described. The integrated circuit package includes at least two integrated circuits that are attached with a substrate. The integrated circuits and the substrates are at least partially encapsulated in a molding material. There is a groove or air gap that extends partially through the molding material and that is arranged to form a thermal barrier between the integrated circuits.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: May 6, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Anindya Poddar, Luu T. Nguyen
  • Publication number: 20140103484
    Abstract: In one embodiment, electrostatic discharge (ESD) devices are disclosed.
    Type: Application
    Filed: October 17, 2012
    Publication date: April 17, 2014
    Inventors: David D. Marreiro, Steven M. Etter, Sudhama C. Shastri
  • Patent number: 8680602
    Abstract: A semiconductor device includes a substrate including a first region and a second region, a gate group disposed in the first region of the substrate, the gate group including a plurality of cell gate patterns and at least one selection gate pattern, a first gate pattern disposed in the second region of the substrate, a group spacer covering a top surface and a side surface of the gate group, the group spacer having a first inflection point, and a first pattern spacer covering a top surface and a side surface of the first gate pattern, the first pattern spacer having a second inflection point.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: March 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hwang Sim, Jae-Bok Baek
  • Patent number: 8674473
    Abstract: A semiconductor cell includes storage node contact plugs disposed on a semiconductor substrate, a bit line formation area which is disposed between the storage node contact plugs and exposes the semiconductor substrate, and an air gap which is in contact with a lower portion of a sidewall of the bit line formation area and extends in a direction perpendicular to a direction in which the bit line formation area extends. Therefore, the coupling effect between adjacent bit lines as well as the coupling effect caused between adjacent storage node contact plugs and the coupling effect caused between the storage node contact plug and the bit line are controlled to improve characteristics of semiconductor devices.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: March 18, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Song Hyeuk Im
  • Patent number: 8664743
    Abstract: A structure includes a substrate, and a first metal line and a second metal line over the substrate, with a space therebetween. A first air gap is on a sidewall of the first metal line and in the space. A second air gap is on a sidewall of the second metal line and in the space. A dielectric material is disposed in the space and between the first and the second air gaps. A third air gap is underlying the lower portion of the dielectric material, wherein the first air gap, the second air gap, and the third air gap are interconnected to form a continuous air gap.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: March 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsiung Tsai, Chung-Ju Lee, Tien-I Bao
  • Patent number: 8659115
    Abstract: A method of fabricating an airgap-containing interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and a dielectric material is provided. Specifically, a simplified method of fabricating single-damascene and dual-damascene airgap-containing low-k interconnect structures with at least one patternable low-k dielectric and at least one inorganic antireflective coating is provided.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: February 25, 2014
    Assignee: International Business Machines Corporation
    Inventor: Qinghuang Lin
  • Patent number: 8629035
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming an isolation trench in a substrate, and forming an amorphous layer on a sidewall surface of the isolation trench. The method further includes forming a sacrificial layer in the isolation trench via the amorphous layer, and forming an air gap layer on the sacrificial layer. The method further includes forming an air gap in the isolation trench under the air gap layer by removing the sacrificial layer after forming the air gap layer.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: January 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keisuke Nakazawa
  • Patent number: 8629561
    Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: January 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Maxime Darnon, Qinghuang Lin, Anthony D. Lisi, Satyanarayana V. Nitta
  • Patent number: 8618670
    Abstract: A system and method prevent corrosive elements (or at least the oxidizing agent) from making contact with metal connections at the interface between two layers of a stacked IC device. When layers are positioned in proximity to each other, a cavity is formed at the boundary of the planar surfaces of the layers. This cavity is bounded by a peripheral seal between the layers. In one embodiment, a vacuum is created within the cavity thereby reducing the corrosive atmosphere within the cavity. In another embodiment, the cavity is filled with an inert gas, such as argon. Once the cavity has oxidizing elements reduced, the peripheral seal can be encapsulated to prevent seepage of contaminants into the cavity.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: December 31, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Shiqun Gu, Matthew Nowak
  • Patent number: 8609508
    Abstract: A shallow trench isolation is formed in a semiconductor substrate adjacent a MOS transistor. The shallow trench is filled with a fill material while other processing steps are performed. The fill material is later removed through a thin well etched into layers above the trench, leaving the trench hollow. A thin strain inducing layer is then formed on the sidewall of the hollow trench. The well is then plugged, leaving the trench substantially hollow except for the thin strain inducing layer on the sidewall of the trench. The strain inducing layer is configured to induce compressive or tensile strain on a channel region of the MOS transistor and thereby to enhance conduction properties of the transistor.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: December 17, 2013
    Assignee: STMicroelectronics, Inc.
    Inventor: Barry Dove
  • Patent number: 8610238
    Abstract: Structures and methods of forming crack stop trenches are disclosed. The method includes forming active regions disposed in cell regions of a substrate, the cell regions separated by dicing channels, and forming back end of line (BEOL) layers over the substrate, the BEOL layers being formed over the cell regions and the dicing channels. Crack stop trenches are then formed encircling the cell regions by etching a portion of the BEOL layers surrounding the cell regions. The wafer is diced along the dicing channels.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: December 17, 2013
    Assignee: Infineon Technologies AG
    Inventors: Erdem Kaltalioglu, Hermann Wendt
  • Patent number: 8609507
    Abstract: A semiconductor device includes gates formed over a semiconductor substrate that are spaced apart from one another and each have a stack structure of a tunnel insulation layer, a floating gate, a dielectric layer, a first conductive layer, and a metal silicide layer, a first insulation layer formed along the sidewalls of the gates and a surface of the semiconductor substrate between the gates and configured to have a height lower than the top of the metal silicide layer; and a second insulation layer formed along surfaces of the first insulation layer and surfaces of the metal silicide layer and configured to cover an upper portion of a space between the gates, wherein an air gap is formed between the gates.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: December 17, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Tae Kyung Kim, Min Sik Jang, Sung Deok Kim
  • Patent number: 8603890
    Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps that are elongated in a column direction between the active areas. At least one cap is formed over each isolation region, at least partially overlying air to provide an upper endpoint for the corresponding air gap. The caps may be formed at least partially along the sidewalls of adjacent charge storage regions. In various embodiments, selective growth processes are used to form capping strips over the isolation regions to define the air gaps. Word line air gaps that are elongated in a row direction between adjacent rows of storage elements are also provided.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: December 10, 2013
    Assignee: SanDisk Technologies Inc.
    Inventors: Vinod Robert Purayath, George Matamis, Eli Harari, Hiroyuki Kinoshita, Tuan Pham
  • Patent number: 8592941
    Abstract: The disclosure relates generally to fuse structures, methods of forming and programming the same, and more particularly to fuse structures having crack stop voids. The fuse structure includes a semiconductor substrate having a dielectric layer thereon and a crack stop void. The dielectric layer includes at least one fuse therein and the crack stop void is adjacent to two opposite sides of the fuse, and extends lower than a bottom surface and above a top surface of the fuse. The disclosure also relates to a design structure of the aforementioned.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Tom C. Lee, Kevin G. Petrunich, David C. Thomas
  • Publication number: 20130307044
    Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps that are elongated in a column direction between the active areas. A blocking layer can be introduced to inhibit the formation of materials in the air gaps during subsequent process steps. The blocking layer may result in selective air gap formation or varying dimension of air gaps at cell areas relative to select gate areas in the memory. The blocking layer may result in a smaller vertical dimension for air gaps formed in the isolation regions at select gate areas relative to cell areas. The blocking layer may inhibit formation of air gaps at the select gate areas in other examples. Selective etching, implanting and different isolation materials may be used to selectively define air gaps.
    Type: Application
    Filed: May 15, 2012
    Publication date: November 21, 2013
    Inventors: Hiroyuki Kinoshita, Ming Tian, Daisuke Maekawa, Naoki Watakabe, Seiji Shimabukuro, Hiroaki Iuchi, Hitomi Nakajima
  • Patent number: 8587095
    Abstract: A method for establishing and closing at least one trench of a semiconductor component, in particular a micromechanical or electrical semiconductor component, having the following steps: applying at least one metal layer over the trench to be formed; forming a lattice having lattice openings in the at least one metal layer over the trench to be formed; forming the trench below the metal lattice, and closing the lattice openings over the trench.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: November 19, 2013
    Assignee: Robert Bosch GmbH
    Inventors: Jochen Reinmuth, Eckhard Graf
  • Publication number: 20130277726
    Abstract: A semiconductor device includes a substrate including a plurality of active regions divided by a plurality of trenches, a plurality of tunnel insulating layer patterns formed over the active regions, a plurality of conductive film patterns formed over the tunnel insulating film patterns, a plurality of first isolation layers formed on sidewalls and bottom surfaces of the trenches, and a plurality of second isolation layers formed between the conductive film patterns.
    Type: Application
    Filed: August 29, 2012
    Publication date: October 24, 2013
    Inventor: Sang Hyuk NAM
  • Publication number: 20130256758
    Abstract: A method of forming an integrated circuit structure includes: forming a vent via extending through a shallow trench isolation (STI) and into a substrate; selectively removing an exposed portion of the substrate at a bottom of the vent via to form an opening within the substrate, wherein the opening within the substrate abuts at least one of a bottom surface or a sidewall of the STI; and sealing the vent via to form an air gap in the opening within the substrate.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Renata A. Camillo-Castillo, James S. Dunn, David L. Harame, Anthony K. Stamper
  • Patent number: 8518794
    Abstract: Provided is a semiconductor device. The semiconductor device includes: a substrate; an active layer on the substrate; a capping layer on the active layer; source/drain electrodes on the capping layer; a gate electrode on the active layer; and a first void region on a first sidewall of the gate electrode and a second void region on a second sidewall facing the first sidewall.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: August 27, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hokyun Ahn, Jong-Won Lim, Hyung Sup Yoon, Woojin Chang, Hae Cheon Kim