Abstract: A semiconductor package includes a package substrate, an interposer provided on the package substrate, a plurality of semiconductor devices on the interposer to be spaced apart from each other, the semiconductor devices being electrically connected to the package substrate through the interposer, and a molding layer on the interposer covering the semiconductor devices and exposing upper surfaces of the semiconductor devices, the molding layer including at least one groove extending in one direction between the semiconductor devices, the groove having a predetermined depth from an upper surface of the molding layer.

Abstract: The present disclosure provides a method for forming a three-dimensional (3D) memory. In an example, the method includes forming a stack structure having interleaved a plurality of stack first layers and a plurality of stack second layers, forming a stair in the stack structure, the stair having one of the stack first layers on a top surface, and forming a layer of sacrificial material having a first portion over a side surface of the stair and a second portion over the top surface of the stair. The method also includes partially removing the first portion of the layer of sacrificial material using an anisotropic etching process and removing a remaining portion of the first portion of the layer of sacrificial material using an isotropic etching process.

Abstract: A semiconductor device is provided. The semiconductor device includes a device substrate, having a device structure layer and a buried dielectric layer, wherein the buried dielectric layer is disposed on a semiconductor layer of the device structure layer and the device substrate comprises a device structure. A metal layer is disposed on the buried dielectric layer and surrounded by a first inter-layer dielectric (ILD) layer. A region of the metal layer has a plurality of openings. The buried dielectric layer has an air gap under and exposing the region of the metal layer with the openings, wherein the air gap is located above the device structure in the device substrate. A second ILD layer is disposed on the metal layer and sealing the air gap at the openings of the metal layer.

Abstract: A semiconductor device includes a gate structure including a gate electrode, a gate spacer layer on a side surface of the gate electrode, and a gate capping layer on the gate electrode. Moreover, the semiconductor device includes a source/drain region on at least one side of the gate structure, a contact plug on the source/drain region, and first and second insulating films between the contact plug and the gate structure and defining an air gap. The first insulating film includes a first surface, and a second surface extending from the first surface while forming a first angle. The second insulating film includes a third surface forming a second angle with the first surface of the first insulating film. The second angle is an acute angle narrower than the first angle. The air gap is defined by the first surface, the second surface, and the third surface.

Abstract: Disclosed are a motion-sensitive field effect transistor (MSFET), a motion detection system, and a method. The MSFET includes a gate structure with a reservoir containing conductive fluid and gate electrode(s). Given position(s) of the gate electrode(s) and a fill level of the fluid within the reservoir, contact between the gate electrode(s) and the fluid depends upon the orientation the MSFET channel region relative to the top surface of the conductive fluid and the orientation of the MSFET channel region relative to the top surface of the conductive fluid depends upon position in space and/or movement of the MSFET and, particularly, position in space and/or movement of the chip on which the MSFET is formed. An electrical property of the MSFET in response to specific bias conditions varies depending on whether or not or to what extent the gate electrode(s) contact the fluid and is, thus, measurable for sensing chip motion.

Abstract: The present disclosure relates to an integrated chip comprising a pair of first metal lines over a substrate. A first interlayer dielectric (ILD) layer is laterally between the pair of first metal lines. The first ILD layer comprises a first dielectric material. A pair of spacers are on opposite sides of the first ILD layer and are laterally separated from the first ILD layer by a pair of cavities. The pair of spacers comprise a second dielectric material. Further, the pair of cavities are defined by opposing sidewalls of the first ILD layer and sidewalls of the pair of spacers that face the first ILD layer.

Abstract: Disclosed is an inductor device and method of manufacturing the same. The inductor device includes an insulating layer, a coil pattern formed on two opposing surfaces of the insulating layer, a first insulating film and a second insulating film formed with different insulating materials on the coil pattern, and a magnetic member formed to enclose the insulating layer, the coil pattern and the first and the second insulating films. By forming thin dual insulating films having a high adhesive strength and breaking strength on an inductor coil, it is possible to improve Ls characteristics of the inductor device and increase the inductance.

Abstract: A method for depositing a film to form an air gap within a semiconductor device is disclosed. An exemplary method comprises pulsing a metal halide precursor onto the substrate and pulsing an oxygen precursor onto a selective deposition surface. The method can be used to form an air gap to, for example, reduce a parasitic resistance of the semiconductor device.

Abstract: A memory structure including a substrate, a gate structure, a charge storage layer, and a first control gate is provided. The substrate has a fin portion. A portion of the gate structure is disposed on the fin portion. The gate structure and the fin portion are electrically insulated from each other. The charge storage layer is coupled the gate structure. The charge storage layer and the gate structure are electrically insulated from each other. The first control gate is coupled to the charge storage layer. The first control gate and the charge storage layer are electrically insulated from each other.

Abstract: A semiconductor device with an air gap includes a plurality of gate stacks disposed on a substrate; a liner layer conformally covering the gate stacks and the substrate; and a dielectric stack disposed on the liner layer on the gate stacks. The air gap is formed between the liner layer and the dielectric stack on two adjacent gate stacks. A height of the air gap is greater than heights of the two adjacent gate stacks, and the air gap includes: a lower portion between the two adjacent gate stacks, sidewalls and a bottom of the lower portion exposing the liner layer; a middle portion above the lower portion; and an upper portion above the middle portion. Sidewalls of the upper portion expose the dielectric stack, a top surface of the upper portion is covered by the dielectric stack, and the upper portion has a smaller width than the lower portion.

Abstract: According to some aspects, there is provided a microelectromechanical systems (MEMS) device wherein one or more components of the MEMS device exhibit attenuated motion relative to one or more other moving components. The MEMS device may comprise a substrate; a proof mass coupled to the substrate and configured to move along a resonator axis; and a first shuttle coupled to the proof mass and comprising one of a drive structure configured to drive the proof mass along the resonator axis or a sense structure configured to move along a second axis substantially perpendicular to the resonator axis in response to motion of the proof mass along the resonator axis, wherein displacement of at least a first portion of the proof mass is attenuated relative to displacement of the first shuttle and/or a second portion of the proof mass.

Abstract: A damascene method for manufacturing a thin film resistor (TFR) module is provided. A pair of heads are formed spaced apart from each other. A dielectric region is deposited over the pair of heads, and an opening extending over both heads is formed in the dielectric region. A TFR layer is deposited over the dielectric region and extending into the opening to define a cup-shaped TFR layer structure including (a) a laterally-extending TFR element base conductively connected to both heads and (b) vertical ridges extending upwardly from the laterally-extending TFR element base. A high density plasma (HDP) ridge removal process is performed to remove or shorten the vertical ridges from the cup-shaped TFR layer structure, thereby defining a TFR element having removed or shorted vertical ridges. The removal or shortening of the vertical ridges may improve the temperature coefficient of resistance (TCR) characteristic of the TFR element.

Abstract: An image sensor includes a semiconductor substrate having a first surface and a second surface with a pixel region having photoelectric conversion regions, a gate electrode disposed on the pixel region and adjacent to the first surface, a first isolation structure extending from the first surface toward the second surface, the first isolation structure comprising a first pixel isolation pattern enclosing the pixel region, and a first inner isolation pattern spaced apart from the first pixel isolation pattern and positioned between the photoelectric conversion regions, and a second isolation structure extending from the second surface toward the first surface with a top surface vertically spaced apart from at least a portion of a bottom surface of the first isolation structure. The bottom surface of the first isolation structure is closer to the second surface of the semiconductor substrate than to the first surface thereof.

Abstract: Structures including an optical component, such as an edge coupler, and methods of fabricating a structure that includes an optical component, such as an edge coupler. The structure includes a substrate having a sealed cavity, an optical component, and a dielectric layer between the optical component and the sealed cavity. The optical component is positioned vertically over the substrate and the dielectric layer, and the optical component overlaps with the sealed cavity in the substrate.

Abstract: Interconnect structures are disclosed. An example includes conductive traces over a first dielectric layer, dielectric helmet structures over top surfaces of the conductive traces, and a second dielectric layer over the helmet structures. Spaces between adjacent ones of conductive traces are devoid of material. A bottom surface of the second dielectric layer is between top surfaces of the dielectric structures and bottom surfaces of the helmet structures, or co-planar with the top surface of the helmet structures, but the airgap extends above tops of the conductive traces. Another example includes a dielectric adjacent to upper sections but not lower sections of conductive traces, so as to provide airgaps between adjacent lower sections. Alternatively, a first dielectric material is adjacent the upper sections and a second compositionally different dielectric material is adjacent the lower sections. In either case, the sidewalls of the upper sections of the interconnect features may include scalloping.

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.

Abstract: A semiconductor structure includes a first device and a second device. The first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. The second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. The first air spacer and the second air spacer have different sizes.

Abstract: A method of forming an array of memory cells comprises forming an elevationally inner tier of memory cells comprising spaced inner tier lower first conductive lines, spaced inner tier upper second conductive lines, and programmable material of individual inner tier memory cells elevationally between the inner tier first lines and the inner tier second lines where such cross. First insulative material is formed laterally between the inner tier second lines to have respective elevationally outermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the inner tier second lines. Second insulative material is formed elevationally over the first insulative material and laterally between the inner tier second lines. The second insulative material is of different composition from that of the first insulative material.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of interconnects spaced apart from each other on a substrate. The plurality of interconnects each have an upper portion and a lower portion. In the method, a plurality of spacers are formed on sides of the upper portions of the plurality of interconnects. A space is formed between adjacent spacers of the plurality of spacers on adjacent interconnects of the plurality of interconnects. The method also includes forming a dielectric layer on the plurality of spacers and on the plurality of interconnects. The dielectric layer fills in the space between the adjacent spacers of the plurality of spacers, which blocks formation of the dielectric layer in an area below the space. The area below the space is between lower portions of the adjacent interconnects.

Abstract: A method for depositing a film to form an air gap within a semiconductor device is disclosed. An exemplary method comprises pulsing a metal halide precursor onto the substrate and pulsing an oxygen precursor onto a selective deposition surface. The method can be used to form an air gap to, for example, reduce a parasitic resistance of the semiconductor device.

Abstract: MEMS structures and methods utilizing a locker film are provided. In an embodiment a locker film is utilized to hold and support a moveable mass region during the release of the moveable mass region from a surrounding substrate. By providing additional support during the release of the moveable mass, the locker film can reduce the amount of undesired movement that can occur during the release of the moveable mass, and preventing undesired etching of the sidewalls of the moveable mass.

Abstract: MEMS structures and methods utilizing a locker film are provided. In an embodiment a locker film is utilized to hold and support a moveable mass region during the release of the moveable mass region from a surrounding substrate. By providing additional support during the release of the moveable mass, the locker film can reduce the amount of undesired movement that can occur during the release of the moveable mass, and preventing undesired etching of the sidewalls of the moveable mass.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A conductive feature over a substrate is provided. A first dielectric layer is deposited over the conductive feature and the substrate. A via-forming-trench (VFT) is formed in the first dielectric layer to expose the conductive feature and the substrate around the conductive feature. The VFT is filled in by a sacrificial layer. A via-opening is formed in the sacrificial layer to expose the conductive feature. A metal plug is formed in the via-opening to connect to the conductive feature. The sacrificial layer is removed to form a surrounding-vacancy around metal plug and the conductive feature. A second dielectric layer is deposited over the substrate to seal a portion of the surrounding-vacancy to form an enclosure-air-gap all around the metal plug and the conductive feature.

Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.

Abstract: The present technology relates to a solid-state imaging device, manufacturing method of a solid-state imaging device, and an electronic device, which can provide a solid-state imaging device having further improved features such as reduced optical color mixing and the like. Also, an electronic device using the solid-state imaging device thereof is provided. According to a solid-state imaging device having a substrate and multiple photoelectric converters that are formed on the substrate, an insulating film forms an embedded element separating unit. The element separating unit is configured of an insulating film having a fixed charge that is formed so as to coat the inner wall face of a groove portion, within the groove portion which is formed in the depth direction from the light input side of the substrate.

Abstract: A method comprises bonding a first chip on a second chip, depositing a first hard mask layer over a non-bonding side of the first chip, depositing a second hard mask layer over the first hard mask layer, etching a first substrate of the first semiconductor chip using the second hard mask layer as a first etching mask and etching the IMD layers of the first chip and the second chip using the first hard mask layer as a second etching mask.

Abstract: A semiconductor device and method of forming a semiconductor device including a semiconductor substrate, a gate stack extending from the semiconductor substrate, wherein the gate stack includes a gate conductor layer, and at least two gate spacers adjacent to each side of the gate stack. The semiconductor device also includes a source/drain region on each side of the spacers, wherein the source/drain regions are adjacent to the semiconductor substrate, an ILD layer adjacent to outer surfaces of the two spacers, wherein a height of the ILD layer is level with a height of the gate stack, and an air gap positioned beneath each spacer.

Abstract: Embodiments of the present invention provide a novel process integration for air gap formation at the sidewalls for a Through Silicon Via (TSV) structure. The sidewall air gap formation scheme for the TSV structure of disclosed embodiments reduces parasitic capacitance and depletion regions in between the substrate silicon and TSV conductor, and serves to also reduce mechanical stress in silicon substrate surrounding the TSV conductor.

Abstract: Methods for reducing the k value of a layer using air gaps and devices produced by said methods are disclosed herein. Methods disclosed herein can include depositing a carbon containing stack over one or more features in a substrate, depositing a porous dielectric layer over the carbon containing stack, and curing the substrate to volatilize the carbon containing stack. The resulting device includes a substrate with one or more features formed therein, a porous dielectric layer formed over the features with an air gap formed in the features.

Abstract: A wiring structure includes a first insulation layer, a plurality of wiring patterns, a protection layer pattern and a second insulation layer. The first insulation layer may be formed on a substrate. A plurality of wiring patterns may be formed on the first insulation layer, and each of the wiring patterns may include a metal layer pattern and a barrier layer pattern covering a sidewall and a bottom surface of the metal layer pattern. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen.

Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device. In order to improve reliability by solving a problem of conductivity that may occur when an air spacer structure that may reduce a capacitor coupling phenomenon between a plurality of conductive lines is formed, there are provided a semiconductor device including: a substrate having an active region; a contact plug connected to the active region; a landing pad spacer formed to contact a top surface of the contact plug; a contact conductive layer formed to contact the top surface of the contact plug and formed in a space defined by the landing pad spacer; a metal silicide layer formed on the contact conductive layer; and a landing pad connected to the contact conductive layer in a state in which the metal silicide layer is disposed between the landing pad and the contact conductive layer, and a method of manufacturing the semiconductor device.

Abstract: A semiconductor device including a substrate having a trench formed therein, a plurality of gate structures, an isolation layer pattern and an insulating interlayer pattern. The substrate includes a plurality of active regions defined by the trench and spaced apart from each other in a second direction. Each of the active regions extends in a first direction substantially perpendicular to the second direction. Each of the plurality of gate structures includes a tunnel insulation layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially stacked on the substrate. The isolation layer pattern is formed in the trench. First isolation layer pattern has at least one first air gap between sidewalls of at least one adjacent pair of the floating gates. The insulating interlayer pattern is formed between the gate structures, and the first insulating interlayer pattern extends in the second direction.

Abstract: An interconnect structure is provided that includes at least one patterned and cured low-k dielectric material located on a surface of a patterned inorganic antireflective coating that is located atop a substrate. The inorganic antireflective coating comprises atoms of M, C and H wherein M is at least one of Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La. The at least one cured and patterned low-k dielectric material and the patterned inorganic antireflective coating have conductively filled regions embedded therein and the at least one cured and patterned low-k dielectric material has at least one airgap located adjacent, but not directly in contact with the conductively filled regions.

Abstract: A method of manufacturing a semiconductor structure, the method includes removing a portion of a dielectric filler from a first metal-containing layer formed over a semiconductor substrate to define an air-gap region according to a predetermined air-gap pattern. The method further includes filling the air-gap region with a decomposable filler and forming a dielectric capping layer over the first metal-containing layer. The method further includes decomposing the decomposable filler.

Abstract: The present invention relates to a CMOS compatible MEMS microphone, comprising: an SOI substrate, wherein a CMOS circuitry is accommodated on its silicon device layer; a microphone diaphragm formed with a part of the silicon device layer, wherein the microphone diaphragm is doped to become conductive; a microphone backplate including CMOS passivation layers with a metal layer sandwiched and a plurality of through holes, provided above the silicon device layer, wherein the plurality of through holes are formed in the portions thereof opposite to the microphone diaphragm, and the metal layer forms an electrode plate of the backplate; a plurality of dimples protruding from the lower surface of the microphone backplate opposite to the diaphragm; and an air gap, provided between the diaphragm and the microphone backplate, wherein a spacer forming a boundary of the air gap is provided outside of the diaphragm or on the edge of the diaphragm.

Abstract: A method of forming a device having an airbridge on a substrate includes forming a plated conductive layer of the airbridge over at least a photoresist layer on a portion of the substrate, the plated conductive layer defining a corresponding opening for exposing a portion of the photoresist layer. The method further includes undercutting the photoresist layer to form a gap in the photoresist layer beneath the plated conductive layer at the opening, and forming an adhesion layer on the plated conductive layer and the exposed portion of the photoresist layer, the adhesion layer having a break at the gap beneath the plated conductive layer. The photoresist layer and a portion of the adhesion layer formed on the exposed portion of the photoresist layer is removed, which includes etching the photoresist layer through the break in the adhesion layer. An insulating layer is formed on at least the adhesion layer, enhancing adhesion of the insulating layer to the plated conductive layer.

Abstract: Disclosed are a structure for electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure includes a trench extending through the top semiconductor layer and into a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a void is disposed in the handle wafer below the trench. A bottom opening of the trench connects the main body of the trench with the void forming a continuous cavity including the main body, the bottom opening of the trench, and the void such that the void improves electrical signal isolation between the adjacent devices situated in the top semiconductor layer. Unetched portions of the handle wafer are then available to provide mechanical support to the top semiconductor layer.

Abstract: A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.

Abstract: High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between control gates and charge storage regions is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction.

Abstract: A method for reducing cross talk in image sensors comprises providing a backside illuminated image sensor wafer, forming an isolation region in the backside illuminated image sensor wafer, wherein the isolation region encloses a photo active region, forming an opening in the isolation region from a backside of the backside illuminated image sensor wafer and covering an upper terminal of the opening with a dielectric material to form an air gap embedded in the isolation region of the backside illuminated image sensor wafer.

Abstract: An embodiment of the present disclosure is directed to a semiconductor device. The semiconductor devise comprises a substrate. An epitaxially grown semiconductor material is disposed over at least a portion of the substrate. A nanotemplate structure is disposed at least partially within the semiconductor material. The nanotemplate structure comprises a plurality of dielectric nanoscale features defining a plurality of nanoscale windows. An air gap is disposed between at least a portion of one or more of the nanoscale features and the semiconductor material.

Abstract: A method of forming and controlling air gaps between adjacent raised features on a substrate includes forming a silicon-containing film in a bottom region between the adjacent raised features using a flowable deposition process. The method also includes forming carbon-containing material on top of the silicon-containing film and forming a second film over the carbon-containing material using a flowable deposition process. The second film fills an upper region between the adjacent raised features. The method also includes curing the materials at an elevated temperature for a period of time to form the air gaps between the adjacent raised features. The thickness and number layers of films can be used to control the thickness, vertical position and number of air gaps.

Abstract: A semiconductor device in which misalignment does not cause short-circuiting and inter-wiring capacitance is decreased. Plural wirings are provided in a first interlayer insulating layer. An air gap is made between at least one pair of wirings in the layer. A second interlayer insulating layer lies over the wirings and first interlayer insulating layer. The first bottom face of the second interlayer insulating layer is exposed to the air gap. When a pair of adjacent wirings whose distance is shortest are first wirings, the upper ends of the first interlayer insulating layer between the first wirings are in contact with the first wirings' side faces. The first bottom face is below the first wirings' upper faces. b/a?0.5 holds where a represents the distance between the first wirings and b represents the width of the portion of the first interlayer insulating layer in contact with the first bottom face.

Abstract: A method of fabricating a semiconductor component that including the following steps is provided. A plurality of stacked structures is formed on a substrate. A first dielectric layer is formed to cover the stacked structures, wherein the first dielectric layer has a plurality of overhangs, the overhangs wrap top portions of the stacked structures. A dry conformable etching process is performed to conformably remove the first dielectric layer until a portion of the first dielectric layer located outside of the overhangs is removed. A second dielectric layer is formed on the stacked structures, wherein the second dielectric layer connects the adjacent overhangs to form an air gap between the stacked structures.

Abstract: According to one embodiment, a semiconductor device includes a first insulating film formed above a substrate, wires formed on the first insulating film, an air gap formed between the adjacent wires, and a second insulating film formed on the wires and the air gap. Each of the wires has a metal film formed on the first insulating film and a hard mask formed on the metal film, the hard mask has a first layer and a second layer, a second internal angle formed by the under surface and the side surface of the second layer on a cross section of the second layer is smaller than a first internal angle formed by the under surface and the side surface of the first layer on a cross section of the first layer, and the top surface of the air gap is higher than the top surface of the metal film.

Abstract: Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Air gaps are formed at least partially in isolation regions between active areas of the substrate. The air gaps may further extend above the substrate surface between adjacent layer stack columns. A sacrificial material is formed at least partially in the isolation regions, followed by forming a dielectric liner. The sacrificial material is removed to define air gaps prior to forming the control gate layer and then etching it and the layer stack columns to form individual control gates and columns of non-volatile storage elements.

Abstract: A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of interconnect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects.

Abstract: A method of forming air gaps between adjacent raised features on a substrate includes forming a carbon-containing material in a bottom region between the adjacent raised features using a flowable deposition process. The method also includes forming a silicon-containing film over the carbon-containing material using a flowable deposition process, where the silicon-containing film fills an upper region between the adjacent raised features and extends over the adjacent raised features. The method also includes curing the carbon-containing material and the silicon-containing material at an elevated temperature for a period of time to form the air gaps between the adjacent raised features.

Abstract: A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.

Abstract: A method is provided for forming at least one TSV interconnect structure surrounded by at least one isolating trench-like structure having at least one airgap. The method comprises at least the steps of providing a substrate having a first main surface and producing simultaneous at least one a TSV hole and a trench-like structure surrounding the TSV hole and separated by remaining substrate material. The method also comprises thereafter depositing a dielectric liner in order to smoothen the sidewalls of the etched TSV hole and to pinch-off the opening of the trench-like structure at the first main surface of the substrate in order to create at least one airgap in said trench-like structure and depositing a conductive material in said TSV hole in order to create a TSV interconnect. A corresponding substrate is also provided.