COL (CHIP-ON-LEAD) MULTI-CHIP PACKAGE
A Chip-On-Lead (COL) multi-chip package is revealed, primarily comprising a plurality of leads, a first chip disposed on the first leads, one or more second chips stacked on the first chip, and an encapsulant. The leads have a plurality of internal leads encapsulated inside the encapsulant where the internal leads are fully formed on a downset plane toward and parallel to a bottom surface of the encapsulant. The height between the internal leads to a top surface of the encapsulant is three times or more greater than the height between the internal leads and the bottom surface. Since the number and the thickness of the second chips is under controlled, tile thickness between the top surface of the encapsulant and the most adjacent one of the second chips is about the same as the one between the internal leads and the bottom surface of the encapsulant. Therefore, the internal leads of the leads without downset bends in the encapsulant can balance the upper and lower mold flows and carry more chips without shifting nor tilting.
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The present invention relates to packaged semiconductor devices, especially to Chip-On-Lead (COL) multi-chip packages.
BACKGROUND OF THE INVENTIONIn the conventional semiconductor packages, leadframes have been widely implemented as chip carriers and as electrical connection media. There are several basic packaging configurations according to the features of the chip carriers such as Chip-On-Lead packages (COL), Lead-On-Chip (LOC) packages, and conventional “chip on die pad” packages where COL packages are to attach the back surfaces of the chips, i.e., the surfaces of the chips without ICs, to certain internal sections of the leads, then the chips and the leads of leadframes are encapsulated by molding. In order to balance the upper and lower mold flows during transfer molding, at least two downset bends are formed on the leads or on the tie bars of the die pad leading to shaking of the leads. Once experienced the pressure of the mold flows during molding processes, the leads having downset bends are sensitive to shift or deform, therefore, space should be reserved in the encapsulant to prevent the internal packaging components such as chips or leads from atmosphere exposure and contaminations. Hence, the number of chips can be stacked inside a package is limited, especially the structural strengths of the leads of COL packages are not strong enough to hold and stack the chips leading to shifting and tilting. Once the chip position changes, the upper and lower mold flows cannot be balanced.
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The main purpose of the present invention is to provide a Chip-On-Lead (COL) multi-chip package without any downset bend of internal leads in an encapsulant to balance the upper and lower mold flows and to reduce the shifting of the leads due to mold flows. Therefore, more chips can be stacked on the leads of the Chip-On-Lead (COL) multi-chip package without any shifting nor tilting.
According to the present invention, a Chip-On-Lead (COL) multi-chip package is revealed, primarily comprising a plurality of first leads, a first chip, one or more second chips, and an encapsulant. Each first lead has a first internal lead inside the encapsulant. The first chip is disposed on the first leads, and the second chips are disposed on the first chip. The encapsulant encapsulates the first chip, the second chips, and the first internal leads of the first leads where the encapsulant has a first surface and a second surface parallel to each other. Moreover, the first internal leads are fully formed on a downset plane toward and parallel to the second surface. Moreover, the height between the first internal leads and the first surface is three times or more greater than the height between the first internal leads and the second surface. The encapsulant further has a thickness from the first surface to the second chips about the same as the height from the first internal leads to the second surface of the encapsulant.
Please refer to the attached drawings, the present invention will be described by means of embodiments below.
According to the preferred embodiment of the present invention, a Chip-On-Lead (COL) multi-chip package is revealed in the cross-sectional view of
Each first lead 210 has a first internal lead 211 and a first external lead 212 where the internal leads 211 are portions of the first leads 210 disposed inside the encapsulant 250 and the external leads 212 disposed outside the encapsulant 250. The first leads 210 are parts of a metal leadframe made of iron, copper, or other metal alloy where the first leads 210 have an appropriate thickness such as 0.125 mm or more with enough structural strengths to support the first chip 230 and the second chips 240. Preferably, the thickness of the first lead 210 can not be smaller than the one of the first chip 230. Moreover, the first internal leads 211 are coplanarly downset, i.e., the first internal leads 211 are fully formed on a downset plane 201 without weakening the structural strengths to support the chips 230 and 240. The term “fully downset” means that all of the first internal leads 211 are formed on the downset plane 201 so that the first lead 210 have no any downset bend inside the encapsulant 250. The term “downset bend” means that the first internal leads 211 are bent with 90° or other angles to form different bends on different planes from the downset plane 201. To be more specific, the first internal leads 211 are inwardly extended from one side of the encapsulant 250 passing under the back surface of the first chip 230 so that the back surface of the first chip 230 covers certain sections of the first internal leads 211 except a plurality of internal ends of the first internal leads 211. The internal ends of the first internal leads 211 exposed from the first chip 230 are configured as bonding fingers for wire-bonding connections. In the present embodiment, the lengths of the first internal leads 211 are long enough to cross the central line of the COL multi-chip package 200 to support the first chip 230 and the second chips 240. In the present embodiment, the first external leads 212 of the first leads 210 extend from the same side of the encapsulant 250 for mounting to an external printed circuit board, not shown in the figure. The first external leads 212 are bent into gull leads, I-leads, J-leads or other shapes.
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The encapsulant 250 is normally formed by transfer molding to encapsulate the first chip 230, the second chips 240, and the first internal leads 211 from the contaminations of the environment. As shown in
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In the present embodiment, the thickness of the Chip-On-Lead (COL) multi-chip package 200 is set at 1.000 mm. To be more specific, the height H1 is the distance from the upper surfaces of the first internal leads 211 on which the first chip 230 are disposed to the first surface 251 where the height H1 is equal to the total amount including the thicknesses of the first chip 230 (about 0.125 mm), the three second chips 240 (about 0.125 mm per each), the four electrically isolating die-attaching films 234 and 244 (about 0.025 mm per each), and the thickness T1 (about 0.138 mm). Therefore, the height H1 can be calculated to be about 0.738 mm and the H2 is about 0.138 mm. In the present embodiment, it is very obvious that the height H1 is about five times greater than the height H2 to stack four chips. In different embodiments, the ratio of the height H1 to the height H2 can be 3 to 1 or 4 to 1 to stack two or three chips.
Therefore, the first internal leads 211 of the first leads 210 can balance the upper and lower mold flows and reduce the shifting and tilting of the chip and avoid the leads exposed or/and the bonding wires broken due to mold flows without forming any downset bends of the first internal leads 211 inside the encapsulant 250 so that more chips can be stacked on the first internal leads 211 of the first leads 210 without shifting nor tilting. Since the first internal leads 211 inside the encapsulant 250 are fully formed on the downset plane 201 without affecting by the mold flows, the first internal leads 211 of the first leads 210 can be kept in parallel to the adjacent second surface 252 of the encapsulant 250 during the molding processes. More space above the first chip 230 is provided for stacking more second chips 240. Therefore, the memory capacity can be increased by stacking more chips without increasing the total package thickness nor changing product reliability. Preferably, since the second chips 240 are stair-like staggeredly stacked to save conventional interposer, the chip attached height between the second chips 240 (equal to the thickness of the electrically isolating die-attaching film 244) can be about the same as the chip attached height between the first chip 230 and the first internal leads 211 (equal to the thickness of the electrically isolating die-attaching film 234). This is very easy to calculate to the thickness TI and the stacking number of the chips to achieve the upper and lower mold flows. Furthermore, the production cycle time of the Chip-On-Lead (COL) multi-chip package 200 can be shortened by eliminating the step of formation extra downset bends.
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In the second embodiment of the present invention, as shown in
The above description of embodiments of this invention is intended to be illustrative but not limiting. Other embodiments of this invention will be obvious to those skilled in the art in view of the above disclosure.
Claims
1. A Chip-Oil-Lead (COL) multi-chip package primarily comprising:
- a plurality of first leads each having a first internal lead; a first chip disposed on the first leads;
- one or more second chips stacked on the first chip; and
- an encapsulant encapsulating the first chip, the second chips, and the first internal leads of the first leads, the encapsulant having a first surface and a second surface parallel to each other;
- wherein the first internal leads are fully formed on a downset plane toward and parallel to the second surface and the height between the first internal leads and the first surface are three times or more greater than the height between the first internal leads and the second surface; wherein the encapsulant further has a thickness from the first surface to the second chips about the same as the height from the first internal leads to the second surface of the encapsulant.
2. The COL multi-chip package as claimed in claim 1, wherein the number of the second chips is three.
3. The COL multi-chip package as claimed in claim 1, wherein the first chip has a first active surface, a first back surface, and a plurality of first bonding pads formed on the first active surface, wherein the first back surface is attached to the first internal leads.
4. The COL multi-chip package as claimed in claim 3, further comprising a plurality of first bonding wires electrically connecting the first bonding pads to a plurality of internal ends of the first internal leads extending from the first chip.
5. The COL multi-chip package as claimed in claim 1, wherein the thickness of each second chip is not greater than the one of the first chip, and the thickness of the first leads is not smaller than the one of the first chip.
6. The COL multi-chip package as claimed in claim 1, wherein each first lead further has a first external lead extending from one side of the encapsulant.
7. The COL multi-chip package as claimed in claim 6, wherein the first external leads of the first leads are bent toward the first surface of the encapsulant.
8. The COL multi-chip package as claimed in claim 7, further comprising a plurality of second leads each having a second internal lead, wherein the second internal leads are shorter than the first internal leads without carrying the first chip.
9. The COL multi-chip package as claimed in claim 8, wherein the second internal leads of the second leads are coplanar with the first internal leads.
10. The COL multi-chip package as claimed in claim 9, wherein the number of the second leads is the same as the one of the first leads.
11. The COL multi-chip package as claimed in claim 9, wherein each second lead further has a second external lead extending from one side of the encapsulant.
12. The COL multi-chip package as claimed in claim 11, wherein the second external leads of the second leads are bent toward the first surface of the encapsulant.
13. The COL multi-chip package as claimed in claim 8, wherein each second chip further has a plurality of second bonding pads, wherein the second chips are stair-like staggeredly stacked on each other without covering the second bonding pads.
14. The COL multi-chip package as claimed in claim 13, further comprising a plurality of second bonding wires electrically connecting the second bonding pads to the first bonding pads.
15. The COL multi-chip package as claimed in claim 14, further comprising a plurality of interconnecting bonding wires electrically connecting the second bonding pads of two adjacent second chips.
16. The COL multi-chip package as claimed in claim 15, further comprising a plurality of first bonding wires electrically connecting the first bonding pads to the first internal leads and the second internal leads.
17. The COL multi-chip package as claimed in claim 1, further comprising a space-keeping tape attached to a plurality of surfaces of the first internal leads of the first leads facing to the second surface of the encapsulant.
18. The COL multi-chip package as claimed in claim 1, wherein the first chip and the second chips are thinned by lapping each to have a chip thickness not greater than the height between the first internal leads and the second Surface.
19. The COL multi-chip package as claimed in claim 18, further comprising a plurality of electrically isolating die-attaching films fully attached to a plurality of back Surfaces of the first chip and the second chips.
Type: Application
Filed: Jun 5, 2008
Publication Date: Dec 10, 2009
Applicant:
Inventor: Wen-Jeng Fan (Hukou Shiang)
Application Number: 12/133,892
International Classification: H01L 23/495 (20060101);