Lead Frames Or Other Flat Leads (epo) Patents (Class 257/E23.031)

  • Patent number: 9573303
    Abstract: A manufacturing method of metal and plastic composite bodies integrated by etching a surface of a metal member and forming a thermoplastic resin on an etching surface may include forming a printing layer which prints a pattern or a character on an exposed surface of a metal member and a protective layer for protecting the printed pattern thereon, grease-removing and cleaning to remove a passivation oxidized film at a rear side of the metal member to be integrally coupled with a plastic portion, surface-treating a surface by using and etching a ferric chloride solution in a range of pH 3 to 4.5 so as to form a minute unevenness at the rear side, removing a smut generated in the surface-treating process, and molding for integrally forming the plastic portion with the metal member.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: February 21, 2017
    Assignees: Hyndai Motor Company, Kia Motors Corporation, Hankook National Co., Ltd.
    Inventors: Byung Seob Yu, Yang Gi Lee, Chan Mook Choi, Hyung Chul Kim
  • Patent number: 9041182
    Abstract: A semiconductor package according to embodiments includes: a semiconductor chip including a front electrode on a front surface thereof and a back electrode on a back surface thereof; a front-side cap portion including an air gap in a portion between the semiconductor chip and the front-side cap portion and a front-side penetrating electrode, and is positioned to face the front surface of the semiconductor chip; a back-side cap portion bonded with a first cap portion to hermetically seal the semiconductor chip, includes an air gap at least in a portion between the semiconductor chip and the back-side cap portion and a back-side penetrating electrode, and is positioned to face the back surface of the semiconductor chip; a front-side connecting portion which electrically connects the front electrode and the front-side penetrating electrode; and a back-side connecting portion which electrically connects the back electrode and the back-side penetrating electrode.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: May 26, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshihiko Nagano, Kazuhide Abe, Hiroshi Yamada, Kazuhiko Itaya, Taihei Nakada
  • Patent number: 9035440
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent to the package paddle; depositing a lead conductive cap on the lead, the lead conductive cap includes a nickel layer having a thickness between 2.55 ?m to 8.00 ?m deposited on the lead, a palladium layer deposited on the nickel layer, and a gold layer deposited on the palladium layer; mounting an integrated circuit over the package paddle; attaching an electrical connector between the lead conductive cap and the integrated circuit; and forming an encapsulation over the integrated circuit, a portion of the lead, and a portion of the package paddle.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: May 19, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Emmanuel Espiritu, Elizar Andres, Henry Descalzo Bathan, Zigmund Ramirez Camacho
  • Patent number: 9035438
    Abstract: The present specification relates to a semiconductor device in which a metal plate is attached onto a surface of a resin package, and provides a structure in which the metal plate is not easy to separate. The semiconductor device disclosed in the present specification includes semiconductor chips (IGBT, diode), a resin package molding the semiconductor chips, and metal plates fixed onto the surface of the resin package. An anchoring member is bridged between two points on a back face of the metal plate. A space between one of the metal plates and the anchoring member is filled with a molding resin of the resin package. The anchoring member firmly bites the resin package, and therefore, the metal plate is difficult to be released from the resin package.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: May 19, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Shoji Hayashi
  • Patent number: 9029999
    Abstract: A semiconductor sensor device is packaged using a footed lid instead of a pre-molded lead frame. A semiconductor sensor die is attached to a first side of a lead frame. The die is then electrically connected to leads of the lead frame. A gel material is dispensed onto the sensor die. The footed lid is attached to the substrate such that the footed lid covers the sensor die and the electrical connections between the die and the lead frame. A molding compound is then formed over the substrate and the footed lid such that the molding compound covers the substrate, the sensor die and the footed lid.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: May 12, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Wai Yew Lo
  • Patent number: 9029903
    Abstract: A light emitting diode package including a package body with a cavity, a plurality of light emitting diode (LED) chips in the cavity, a plurality of wires connected to the plurality of LED chips, and a plurality of lead frames in the package body, wherein the lead frames comprise a first lead frame electrically connected to a first electrode of a first LED chip, a second lead frame electrically connected to a second electrode of the first LED chip and a second electrode of a second LED chip, a third lead frame electrically connected to a first electrode of the second LED chip, and fourth lead frame electrically connected to a second electrode of a third LED chip. Further, ends of the lead frames are exposed outside of the package body and penetrate the package body, and the first electrodes are P electrodes and the second electrodes are N electrodes.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: May 12, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: Won-Jin Son
  • Patent number: 9029991
    Abstract: An example semiconductor package with reduced solder voiding is described, which has a leadframe having an I/O pad and a thermal pad, a fabricated semiconductor die having a bond pad, where the fabricated semiconductor die is attached to a top surface of the thermal pad, and a wire bond connecting the bond pad to the I/O pad, where a bottom surface of the thermal pad has channels.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: May 12, 2015
    Assignee: Conexant Systems, Inc.
    Inventors: Robert W. Warren, Hyun Jung Lee, Nic Rossi
  • Patent number: 9024420
    Abstract: Some exemplary embodiments of a multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections have been disclosed. One exemplary embodiment comprises a PQFN semiconductor package comprising a leadframe, a driver integrated circuit (IC) coupled to the leadframe, a plurality of vertical conduction power devices coupled to the leadframe, and a plurality of wirebonds providing electrical interconnects, including at least one wirebond from a top surface electrode of one of the plurality of vertical conduction power devices to a portion of the leadframe, wherein the portion of the leadframe is electrically connected to a bottom surface electrode of another of the plurality of vertical conduction power devices. In this manner, efficient multi-chip circuit interconnections can be provided in a PQFN package using low cost leadframes.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: May 5, 2015
    Assignee: International Rectifier Corporation
    Inventors: Dean Fernando, Roel Barbosa
  • Patent number: 9018746
    Abstract: One embodiment is directed towards a packaged chip including a lead frame. At least one chip is mounted on the lead frame. At least one edge the lead frame has a solder flow impeding feature located thereon. The solder flow impeding feature includes an integral portion of the lead frame that extends in a first projection outward at an edge of the lead frame and parallel to an external surface of the lead frame. An internal surface of the first projection is aligned with an internal surface of the main portion of the lead frame. The solder flow impeding feature also includes a second projection that extends from an external side of the first projection in a direction generally perpendicular to the first projection.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: April 28, 2015
    Assignee: Intersil Americas LLC
    Inventors: Randolph Cruz, Loyde Milton Carpenter, Jr.
  • Patent number: 9012268
    Abstract: Embodiments of the present disclosure are directed to leadframe strips and methods of forming packages that include first separating adjacent leads of a leadframe strip and subsequently singulating components into individual packages. In one embodiment, the adjacent leads are separated by etching through the leads, thereby providing electrical isolation of the adjacent packages. In that regard, if desired, the individual adjacent packages may be electrically tested in leadframe strip form. Subsequently, the individual packages are formed by sawing through the encapsulation material.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics, Inc.
    Inventors: Jonathan Jaurigue, Rogelio Real, Francis Ann Llana, Ricky Calustre, Rodolfo Gacusan
  • Patent number: 9013032
    Abstract: A plastic SON/QFN package for high power has a pair of oblong metal pins exposed from a surface of the plastic, the pins straddling a corner of the package; each pin has a long axis, the long axes of the pair forming a non-orthogonal angle.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: April 21, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Sreenivasan K. Koduri
  • Patent number: 9006873
    Abstract: A method includes providing a carrier having a first cavity, providing a dielectric foil with a metal layer attached to the dielectric foil, placing a first semiconductor chip in the first cavity of the carrier, and applying the dielectric foil to the carrier.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: April 14, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ivan Nikitin, Joachim Mahler
  • Patent number: 8994161
    Abstract: Some embodiments have a semiconductor chip supported above a substrate, a filler layer encapsulating the semiconductor chip, a heat sink; and through contacts extending upwardly from the substrate nearly to an upper surface of the filler layer. In some embodiments of electronic packages, the through contacts separated from the heat sink by a trench cut into the upper surface of the filler layer, the through contacts intersecting one wall of the trench and the heat sink intersecting the other wall of the trench an electronic semiconductor package. A method of forming the package and a lead frame are also disclosed.
    Type: Grant
    Filed: January 2, 2007
    Date of Patent: March 31, 2015
    Assignee: Infineon Technologies AG
    Inventors: Michael Ahr, Bakuri Lanchava
  • Patent number: 8994160
    Abstract: A resin-encapsulated semiconductor device includes: a semiconductor element mounted on a die pad portion; a plurality of lead portions disposed so that distal end parts thereof are opposed to the die pad portion; a metal thin wire for connecting an electrode of the semiconductor element to the lead portion; and an encapsulating resin for partially encapsulating those components. A bottom surface part of the die pad portion, and a bottom surface part, an outer surface part, and an upper end part of the lead portion are exposed from the encapsulating resin. A plated layer is formed on the exposed lead bottom surface part and the exposed lead upper end part.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: March 31, 2015
    Assignee: Seiko Instruments Inc.
    Inventor: Noriyuki Kimura
  • Patent number: 8981548
    Abstract: An integrated circuit package system including: providing a die pad with a top, sides, and a bottom, the bottom having a relief with a flat surface and defining a wall and a center pad; mounting a barrier under the bottom of the die pad; mounting an integrated circuit die on the top of the die pad; encapsulating the integrated circuit die and the top and sides of the die pad with the wall preventing encapsulation from flowing along the barrier to reach the center pad; and mounting an external interconnect on the center pad.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: March 17, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Il Kwon Shim, Jeffrey D. Punzalan, Henry Descalzo Bathan
  • Patent number: 8975733
    Abstract: There is provided a technology enabling the improvement of the reliability of a semiconductor device manufactured by physically fixing separately formed chip mounting portion and lead frame. A feature of an embodiment resides in that, a second junction portion formed in a suspension lead is fitted into a first junction portion formed in a chip mounting portion, thereby to physically fix the chip mounting portion and the suspension lead. Specifically, the first junction portion is formed of a concave part disposed in the surface of the chip mounting portion. The second junction portion forms a part of the suspension lead.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: March 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yukihiro Sato, Nobuya Koike
  • Patent number: 8975738
    Abstract: A structure may include a spacer element overlying a first portion of a first surface of a substrate; first terminals at a second surface of the substrate opposite the first surface; and second terminals overlying a third surface of the spacer element facing away from the first surface. Traces extend from the second terminals along an edge surface of the spacer element that extends from the third surface towards the first surface, and may be electrically coupled between the second terminals and the first terminals or electrically conductive elements at the first surface. The spacer element may at least partially define a second portion of the first surface, which is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some of the conductive elements are at the second portion and may permit connection with such microelectronic element.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: March 10, 2015
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed
  • Patent number: 8963300
    Abstract: A semiconductor device includes a leadframe, a semiconductor chip, a packaging compound. The leadframe has a pad with straps. Leads on the leadframe include first and second portions. The pad, the straps, and the leads have a mechanically rough surface. The semiconductor chip is attached to the pad and wire bonded to the first lead portions. A packaging compound encapsulates the chip, the pad, the straps, the bonding wires and the first lead portions. The second lead portions are left un-encapsulated. The strap ends are exposed on the surface of the package. At least one of the straps includes a portion adjacent to the exposed end. This portion having a mechanically smooth surface transitioning by a step into the rough surface of the remainder of the strap.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: February 24, 2015
    Assignee: Texas Instruments Incorporation
    Inventor: Donald C. Abbott
  • Patent number: 8963305
    Abstract: A packaged semiconductor device may include a leadframe and a die carrier mounted to the leadframe. The die carrier is formed from an electrically and thermally conductive material. A die is mounted to a surface of the die carrier with die attach material having a melting point in excess of 240° C. A first electrical interconnect couples the die and the leadframe. A housing covers portions of the leadframe, die carrier, die and first electrical interconnect.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: February 24, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Fernando A. Santos, Audel A. Sanchez, Lakshminarayan Viswanathan
  • Patent number: 8945990
    Abstract: Embodiments provide a method of forming a chip package. The method may include attaching at least one chip on a carrier, the chip including a plurality of chip pads on a surface of the chip opposite to the carrier; depositing a first adhesion layer on the carrier and on the chip pads of the chip, the first adhesion layer including tin or indium; depositing a second adhesion layer on the first adhesion layer, the second adhesion layer including a silane organic material; and depositing a lamination layer or an encapsulation layer on the second adhesion layer and the chip.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: February 3, 2015
    Assignee: Infineon Technologies AG
    Inventors: Holger Torwesten, Manfred Mengel, Stefan Schmid, Soon Lock Goh, Swee Kah Lee
  • Patent number: 8941221
    Abstract: A semiconductor package includes a die pad, at least one semiconductor die mounted on the die pad, a plurality of leads disposed along peripheral edges of the die pad, at least one connecting bar for supporting the die pad, a first power bar disposed on one side of the connecting bar, a second power bar disposed on the other side of the connecting bar, and a connection member traversing the connecting bar and electrically connecting the first power bar with the second power bar.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: January 27, 2015
    Assignee: Mediatek Inc.
    Inventor: Nan-Jang Chen
  • Patent number: 8936971
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle group having a first package paddle electrically isolated from a second package paddle; attaching an integrated circuit device on the first package paddle and the second package paddle; forming a standoff terminal adjacent the package paddle group and electrically connected to the integrated circuit device; connecting a paddle connector to the integrated circuit device and the first package paddle and another paddle connector to the integrated circuit device and the second package paddle; and forming an encapsulation over the integrated circuit device, the first package paddle, the second package paddle, and the standoff terminal, the encapsulation exposing a portion of the first package paddle, the second package paddle, and the standoff terminal.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: January 20, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Henry Descalzo Bathan
  • Patent number: 8933547
    Abstract: A lead frame for a packaged semiconductor device has multiple, configurable power bars that can be selectively electrically connected, such as with bond wires, to each other and/or to other leads of the lead frame to customize the lead frame for different package designs. One or more of the configurable power bars may extend into one or more cut-out regions in a die paddle of the lead frame, which allows for short bond wires to be used to connect the power bars to die pads of a semiconductor die mounted on the die paddle.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: January 13, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jia Lin Yap, Yin Kheng Au, Ahmad Termizi Suhaimi, Seng Kiong Teng, Boon Yew Low, Navas Khan Oratti Kalandar
  • Patent number: 8927343
    Abstract: A package structure and a package process are provided. The package structure comprises a carrier having a carrying portion and a plurality of supporting bar remnants disposed around and extending outward from the carrying portion, a chip mounted to the carrying portion, and an encapsulant disposed on the carrier and covering the chip, wherein the supporting bar remnants are encapsulated by the encapsulant, and each of the supporting bar remnants has a distal end shrank from an outer surface of the encapsulant. A package process for fabricating the package structure is also provided.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: January 6, 2015
    Assignee: Aptos Technology Inc.
    Inventor: Chi-Jang Lo
  • Patent number: 8927342
    Abstract: The present invention specifies a leadframe for electronic components and a corresponding manufacturing process, in which the bonding islands are formed by welding individual, prefabricated segments of a bonding-capable material onto a stamped leadframe.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: January 6, 2015
    Assignee: Tyco Electronics AMP GmbH
    Inventors: Peter Goesele, Friedrich Seger, Josef Sinder, Joachim Stifter, Oliver Werner
  • Patent number: 8921985
    Abstract: A semiconductor device includes: a semiconductor chip including a main surface electrode; a first mounting lead; a second mounting lead; a connection lead which overlaps with the main surface electrode, the first mounting lead and the second mounting lead when viewed in a thickness direction of the semiconductor chip and makes electrical conduction between the main surface electrode, the first mounting lead and the second mounting lead; and a resin portion which covers the semiconductor chip, the first mounting lead and the second mounting lead, wherein the resin portion has a resin bottom lying on the same plane as a bottom of the first mounting lead and a bottom of the second mounting lead.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: December 30, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Koshun Saito
  • Patent number: 8912636
    Abstract: A lead frame includes an inner lead area overlapping with a chip mounting area, an outer lead portion having outer leads disposed outside the inner lead area, and an inner lead portion having inner leads disposed in the inner lead area. A semiconductor chip is mounted on the chip mounting area of the lead frame. Electrode pads of the semiconductor chip are electrically connected to inner leads via metal wires. Portions of the inner leads located on an area in the inner lead area except the chip mounting area are depressed.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: December 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiaki Goto
  • Patent number: 8906741
    Abstract: A method for making an electronic package structure is provided which comprises: providing a substrate; providing an inductor module; assembling the inductor module and the substrate so that they define a space; injecting package glue into the space defined by the inductor module and the substrate so as to form a package layer.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: December 9, 2014
    Assignee: Cyntec Co., Ltd.
    Inventors: Bau-Ru Lu, Kai-Peng Chiang, Da-Jung Chen, Tsung-Chan Wu
  • Patent number: 8896131
    Abstract: A switching device includes a low voltage normally-off transistor and a control circuit built into a common die. The device includes source, gate and drain electrodes for the transistor and one or more auxiliary electrodes. The drain electrode is on one surface of a die on which the transistor is formed, while each of the remaining electrodes is located on an opposite surface. The one or more auxiliary electrodes provide electrical contact to the control circuit, which is electrically connected to one or more of the other electrodes.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: November 25, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Anup Bhalla, Sik Lui, Jun Hu, Fei Wang
  • Patent number: 8890308
    Abstract: An integrated circuit package includes an electronic sensor protected by a lid structure. The electronic sensor includes a transducer placed on a backside surface of a lead frame assembly. The lid structure is placed over the transducer and is attached to the lead frame assembly on the backside surface. The lid can define an air cavity around the transducer, such that mold compound, gel, or other protective chemical material is not placed in contact with the transducer. The transducer is therefore protected without a chemical protectant, lowering the cost of the integrated circuit package and maintaining the sensitivity and performance of the transducer.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: November 18, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Stephen R. Hooper, William C. Stermer, Jr.
  • Patent number: 8890310
    Abstract: A power module package includes a power circuit element, a control circuit element, a lead frame, an aluminum oxide substrate having a heat sink and an insulation layer, and a sealing resin. The control circuit element is electrically connected with the power circuit element to control chips within the power circuit element. The lead frame has external connection terminal leads in its edge and has a first surface to which the power circuit element and the control circuit element are attached and a second surface which is used as a heat transmission path. The heat sink is a plate made of metal such as aluminum and the electrical insulation layer is formed at least on an upper surface of the heat sink and made of aluminum oxide. The electrical insulation layer may be formed over an entire surface of the heat sink. Here, the insulation layer is attached to the second surface by an adhesive, on a region below where the power circuit element is attached, to the first surface of the lead frame.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: November 18, 2014
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventors: Keunhyuk Lee, Oseob Jeon, Seungwon Lim
  • Patent number: 8884413
    Abstract: A leadframe (e.g., incorporated in a device package) includes a feature (e.g., a die pad or lead) with a vent hole formed between first and second opposed surfaces. The cross-sectional area of the vent hole varies substantially between the surfaces (e.g., the vent hole has a constricted portion). The vent hole may be formed from a first opening extending from the first surface toward the second surface to a first depth that is less than a thickness of the leadframe feature, and a second opening extending from the second surface toward the first surface to a second depth that is less than the thickness of the leadframe feature, but that is large enough for the second opening to intersect the first opening. Vertical central axes of the openings are horizontally offset from each other, and the constricted portion of the vent hole corresponds to the intersection of the openings.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: November 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Philip H. Bowles, Stephen R. Hooper
  • Patent number: 8877564
    Abstract: One embodiment is directed towards a method of manufacturing a packaged circuit. The method includes partially etching an internal surface of a lead frame at dividing lines between future sections of the lead frame as first partial etch. One or more dies are attached to the internal surface of the lead frame and encapsulated. The method also includes partially etching an external surface of the lead frame at the dividing lines to disconnect different sections of lead frame as a second partial etch, wherein the second partial etch removes a laterally wider portion of the lead frame than the first partial etch of the internal surface; and partially etching the external surface of the lead frame as a third partial etch, wherein the third partial etch overlaps a portion of the second partial etch and extends deeper into the lead frame than the second partial etch.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: November 4, 2014
    Assignee: Intersil Americas LLC
    Inventors: Randolph Cruz, Loyde M. Carpenter, Jr.
  • Patent number: 8871571
    Abstract: A frame includes heat slug pads coupled together in a N×M matrix such that singulation of the heat slug pads consists of one or more passes across the frame, wherein the one or more passes are parallel. A method of attaching heat slug pads to packages includes gathering a plurality of packages, preparing a heat slug frame including a N×M matrix of heat slug pads, dispensing thermally conductive material onto surfaces of the heat slug pads, attaching the plurality of packages onto the heat slug pads, and singulating the heat slug pads, wherein the singulating step consists of one or more parallel passes across the N×M matrix. A method of attaching heat slug foil to packages includes preparing a plurality of packages, laminating the heat slug foil to one side of the plurality of packages using thermally conductive material, and singulating the plurality of packages.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: October 28, 2014
    Assignee: UTAC Thai Limited
    Inventor: Saravuth Sirinorakul
  • Patent number: 8866273
    Abstract: The present invention relates to the field of semiconductor package structures, and more specifically to a lead frame and a semiconductor package structure thereof. In one embodiment, a lead frame can include a plurality of parallel-arrayed lead fingers with a plurality of grooves situated on surfaces of the lead fingers, where the depths of the grooves can be smaller than the thickness of the lead fingers. In one embodiment, a flip chip semiconductor package structure can include a chip, a group of bumps, and the above-described lead frame. The first surfaces of the bumps can be coupled to the front surface of the chip, and the second surfaces of the bumps can be coupled to the upper surface of the lead frame.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: October 21, 2014
    Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd
    Inventor: Xiaochun Tan
  • Patent number: 8866283
    Abstract: Methods and structures related to packaging a chip are disclosed. In one embodiment, a chip package structure includes: (i) a chip having a plurality of first and second contact pads thereon; (ii) a lead frame having a plurality of pins for external connection to the package structure, where the chip is disposed on the lead frame; (iii) a plurality of first bonding wires for connecting the first contact pads to the lead frame; and (iv) a plurality of second bonding wires for connecting the second contact pads to the plurality of pins on the lead frame.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: October 21, 2014
    Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd.
    Inventors: Wei Chen, XiaoChun Tan
  • Patent number: 8865524
    Abstract: A lead carrier provides support for an integrated circuit chip and associated leads during manufacture as packages containing such chips. The lead carrier includes a temporary support member with multiple package sites. Each package site includes a die attach pad surrounded by a plurality of terminal pads. The pads are formed of a sintered electrically conductive material. A chip is mounted upon the die attach pad and wire bonds extend from the chip to the terminal pads. The pads, chip and wire bonds are all encapsulated within a mold compound. The temporary support member can be peeled away and then the individual package sites can be isolated from each other to provide completed packages including multiple surface mount joints for mounting within an electronics system board. Edges of the pads are contoured to cause the pads to engage with the mold compound to securely hold the pads within the package.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: October 21, 2014
    Assignee: EoPlex Limited
    Inventor: Philip E. Rogren
  • Patent number: 8860194
    Abstract: One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: October 14, 2014
    Assignee: International Rectifier Corporation
    Inventors: Ling Ma, Andrew N. Sawle, David Paul Jones, Timothy D. Henson, Niraj Ranjan, Vijay Viswanathan, Omar Hassen
  • Patent number: 8847379
    Abstract: A method for manufacturing a package comprises a first step of forming a metal pattern including a frame and a plurality of leads extending inward from the frame, a second step of molding a resin pattern including a first resin portion which holds the plurality of leads from an inner side thereof, and second resin portions which cover bottom surfaces of peripheral portions, adjacent to portions to be removed, in the plurality of leads while exposing bottom surfaces of the portions to be removed in the plurality of leads, so as to hold the plurality of leads from a lower side thereof, and a third step of cutting the plurality of leads into a plurality of first leads and a plurality of second leads by removing the portions to be removed in the plurality of leads while the resin pattern keeps holding the peripheral portions in the plurality of leads.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 30, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Koji Ono
  • Patent number: 8847369
    Abstract: Packaging structures and methods for semiconductor devices are disclosed. In one embodiment, a substrate for packaging a semiconductor device includes a core substrate, an insulating material disposed over the core substrate, and conductive lines disposed in the insulating material. Contact pads are disposed over the insulating material and the conductive lines. The contact pads are disposed in an integrated circuit mounting region of the core substrate. A solder mask define (SMD) material is disposed over the insulating material. Portions of the contact pads are exposed through openings in the SMD material. A stress-relief structure (SRS) is disposed in the SMD material proximate the contact pads. The SRS is disposed entirely in the integrated circuit mounting region of the core substrate.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chih Yew, Wen-Yi Lin, Jiun Yi Wu, Po-Yao Lin
  • Patent number: 8836107
    Abstract: A plastic SON/QFN package (300) for high power has a pair of oblong metal pins (320, 321) exposed from a surface of the plastic (301), the pins straddling a corner (302) of the package; each pin has a long axis (320a, 321a), the long axes of the pair forming a non-orthogonal angle. Package (300) further includes a chip assembly pad (310), acting as a thermal spreader.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: September 16, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Sreenivasan K. Koduri
  • Patent number: 8822273
    Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: September 2, 2014
    Assignee: Vishay-Siliconix
    Inventors: Frank Kuo, Suresh Belani
  • Patent number: 8816480
    Abstract: The electronic device package includes a package substrate including a frame portion and a cantilever portion surrounded by the frame portion, at least one semiconductor chip mounted on the cantilever portion, and a molding member disposed on the package substrate to cover the at least one semiconductor chip. The cantilever portion has a first edge connected to the frame portion and declines from the first edge toward a second edge located opposite to the first edge. Related methods are also provided.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: August 26, 2014
    Assignee: SK Hynix Inc.
    Inventor: Tae Jim Kang
  • Patent number: 8803300
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead-frame having a die attach paddle and a contact pad connected by a link; mounting an integrated circuit die over the die attach paddle; molding a package body on the lead-frame and the integrated circuit die including leaving portions of the die attach paddle, the contact pad, and the link exposed from the package body; forming an exposed edge by etching away the link between the contact pad, and the die attach paddle; and depositing a solder-resistant layer on the exposed edge.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: August 12, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Emmanuel Espiritu, Jeffrey D. Punzalan
  • Patent number: 8796816
    Abstract: A semiconductor module is provided which is capable of lowering surges caused when switching elements are switched on and off. The module has a plurality of lead frames, switching elements, electronic components, and a sealing member. The switching elements are electrically connected to the lead frames respectively. Part of the lead frames, the switching elements, and the electronic components are sealed by the sealing member. The electronic components are mounted on primary surfaces of the lead frames respectively.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: August 5, 2014
    Assignee: Denso Corporation
    Inventors: Yuji Hayashi, Yuuichi Handa
  • Patent number: 8796833
    Abstract: A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: August 5, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Hua Chang, Cheng-Lin Huang, Jing-Cheng Lin
  • Patent number: 8796832
    Abstract: A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device connects an electrode on a semiconductor chip with an external wiring device, and has an insulating layer, a metal substrate and a copper wiring layer. The wiring device has a semiconductor chip support portion provided on the side of the copper wiring layer with respect to the insulating layer. The copper wiring layer includes a first terminal, a second terminal and a wiring portion. The first terminal is connected with the electrode. The second terminal is connected with the external wiring device. The wiring portion connects the first terminal with the second terminal.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: August 5, 2014
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Susumu Baba, Masachika Masuda, Hiromichi Suzuki
  • Patent number: 8796826
    Abstract: A device and method for minimizing the forces that may compromise a lead frame mount to a support structure in an integrated circuit die package during various packaging method steps. When a window clamp is used to provide pressure during a lead frame bonding step or during a wire bonding step during packaging, the vertical force applied by the window clamp may be transferred in lateral direction by the physical contour of the top plate of the support structure. By changing the physical contour of the top plate of the support structure, such as by disposing a specific kind of contoured protrusion, one may minimize or eliminate the lateral forces that act against achieving a solid bond of the lead frame to the support structure. Further, during wire bonding, the same minimization or elimination of lateral forces lead to improved wire bonding.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: August 5, 2014
    Assignee: STMicroelectronics Pte Ltd
    Inventors: Xueren Zhang, Kim-Yong Goh, Wingshenq Wong
  • Patent number: 8791556
    Abstract: An integrated circuit packaging system, and a method of manufacture therefor, including: electrical terminals; circuitry protective material around the electrical terminals and formed to have recessed pad volumes; routable circuitry on the top surface of the circuitry protective material; and an integrated circuit die electrically connected to the electrical terminals.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: July 29, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8791555
    Abstract: A semiconductor device including a semiconductor element, a die pad of a plane size smaller than that of the semiconductor element, a plurality of hanging leads extending from the die pad, and sealing resin for covering the semiconductor element, the die pad, and the hanging leads. The width of a first main surface of each hanging lead, integrated with the mounting surface of the die pad, is smaller than the width of a second main surface thereof, integrated with the opposite surface of the die pad.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: July 29, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Takahiro Yurino