STORAGE CAPACITOR IN OLED PIXELS AND DRIVING CIRCUITS AND METHOD FOR FORMING THE SAME
An electroluminescence device includes a substrate and a plurality of pixels. Each pixel includes a first area including at least a first capacitor and a second capacitor, the first capacitor including a first conductive layer, a first dielectric layer over the first conductive layer, and a second conductive layer over the first dielectric layer, and the second capacitor including the second conductive layer, a second dielectric layer over the second conductive layer, and a third conductive layer over the second dielectric layer, and a transistor in a second area. The transistor includes a first semiconductor layer formed on the substrate, a first gate oxide layer over the first semiconductor layer, a fourth conductive layer over the first gate oxide layer, and a seventh conductive layer contacting the first semiconductor layer, wherein the seventh conductive layer is formed of the same conductive film as the second conductive layer.
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This application is a Divisional of U.S. patent application Ser. No. 11/005,648, filed Dec. 7, 2004, and entitled “Storage Capacitor In OLED Pixels And Driving Circuits And Method For Forming The Same.”
BACKGROUND OF THE INVENTION1. Field of the Invention
This invention relates in general to an electroluminescence device and, more particularly, to a storage capacitor of an electroluminescence device and a method for forming the storage capacitor.
2. Description of the Related Art
An electroluminescence (“EL”) device is a device which makes use of the phenomenon of electroluminescence to emit light. An EL device generally includes thin film transistors (“TFTs”) and light-emitting diodes (“LEDs”). Each LED further includes a light-emitting layer. If the light-emitting layer contains organic light-emitting material, the device is referred to as an organic EL device. When a current passes between a cathode and an anode of the LED device, light is emitted from the light-emitting layer.
Generally, an active matrix organic light emitting diode (“OLED”) device or a polymer light emitting diode (“PLED”) device, either voltage-driven or current-driven, includes an array of pixels, where each pixel comprises a set of sub-pixels. Each sub-pixel further includes a switching transistor, a driving transistor and a storage capacitor. If charging conditions permit, it is desirable to design a storage capacitor with a large capacitance in order to avoid an issue of gray scale fading due to crosstalk or feed-through effect. For bottom-emission pixels, a storage capacitor having a greater capacitance may disadvantageously result in a smaller aperture ratio. In OLED pixels, thin film transistors, scan lines, data lines and power lines included therein may further reduce the aspect ratio. It is thus desirable to have a storage capacitor that includes improved capacitance in a limited area.
BRIEF SUMMARY OF INVENTIONConsistent with embodiments of the present invention, there is provided an electroluminescence (EL) device that includes a substrate and a plurality of pixels formed on the substrate. Each pixel is formed in a respective pixel area, each pixel area including at least a first area and a second area. Each pixel includes at least a first capacitor and a second capacitor in the first area, the first capacitor including a first conductive layer, a first dielectric layer over the first conductive layer, and a second conductive layer over the first dielectric layer, and the second capacitor including the second conductive layer, a second dielectric layer over the second conductive layer, and a third conductive layer over the second dielectric layer, and a first semiconductor layer formed on the substrate in the second area, a first gate oxide layer over the first semiconductor layer, and a fourth conductive layer over the first gate oxide layer.
Consistent with embodiments of the present invention, there is also provided an electroluminescence (EL) device that includes a substrate and a plurality of pixels formed on the substrate. Each pixel is formed in a respective pixel area, each pixel area including at least a first area and a second area. Each pixel includes a first capacitor in the first area, including a first semiconductor layer over the substrate, a first gate oxide layer over the first semiconductor layer, and a first conductive layer over the first gate oxide layer, a second capacitor in the first area, including the first conductive layer, a first interlayer dielectric (ILD) layer over the first conductive layer, and a second conductive layer over the first ILD layer, a third capacitor in the first area, including the second conductive layer, a layer of passivation silicon nitride over the second conductive layer, and a third conductive layer over the passivation silicon nitride, a fourth capacitor in the first area, including the third conductive layer, a first dielectric layer over the third conductive layer, and a fourth conductive layer over the first dielectric layer, and a transistor in the second area, the transistor including a second semiconductor layer over the substrate, a second gate oxide layer over the second semiconductor layer, and a fifth conductive layer over the second gate oxide layer.
Consistent with embodiments of the present invention, there is also provided an electroluminescence (EL) device that includes a substrate and a plurality of pixels over the substrate. Each pixel is in a respective pixel area and each pixel area includes at least a first area and a second area. Each pixel includes a semiconductor layer over the first area and the second area, a gate oxide layer over the first area and the second area, a first metal layer over the first area and the second area, an interlayer dielectric (ILD) layer over the first metal layer over the first area and the second area, a layer of indium tin oxide (ITO) over the ILD layer over the first area, a layer of passivation silicon nitride over the layer of ITO over the first area and over the ILD layer over the second area, a second metal layer over the passivation silicon nitride over the first area and over the second area, wherein the second metal layer over the second area provides contact to the semiconductor layer over the second area through a via hole in the layer of passivation silicon nitride and the gate oxide layer, a layer of capping silicon nitride over the second metal layer over the first area and the second area, a layer of organics over the layer of capping silicon nitride over the first area and the second area, and a third metal layer over the layer of organics over the first area and the second area, wherein the semiconductor layer over the first area, the gate oxide layer over the first area, and the first metal layer over the first area collectively form a first capacitor, the first metal layer over the first area, the ILD layer over the first area, and the layer of ITO over the first area collectively form a second capacitor, the layer of ITO over the first area, the layer of passivation silicon nitride over the first area, and the second metal layer over the first area collectively form a third capacitor, the second metal layer over the first area, the layer of capping silicon nitride over the first area, the layer of organics over the first area, and the third metal layer over the first area collectively form a fourth capacitor, and the semiconductor layer over the second area, the gate oxide layer over the second area, and the first metal layer over the second area collectively form a transistor.
Consistent with embodiments of the present invention, there is also provided a method for forming a pixel of an electroluminescence device that includes providing a substrate; defining at least a first area for capacitors and a second area for a transistor on the substrate; forming a first conductive layer over the first area; forming a first dielectric layer over the first conductive layer over the first area; forming a second conductive layer over the first dielectric layer over the first area; forming a second dielectric layer over the second conductive layer over the first area; forming a third conductive layer over the second dielectric layer over the first area, forming a semiconductor layer over the second area; forming a gate oxide layer over the second area; and forming a fourth conductive layer over the gate oxide layer over the second area, wherein the first conductive layer over the first area is connectable to a power supply voltage, and wherein the first conductive layer, the first dielectric layer, and the second conductive layer over the first area collectively form a first one of the capacitors over the first area, the second conductive layer, the second dielectric layer, and the third conductive layer over the first area collectively form a second one of the capacitors over the first area, and the semiconductor layer, the gate oxide layer, and the fourth conductive layer over the second area collectively form a transistor.
Consistent with embodiments of the present invention, there is also provided a method of forming an electroluminescence (EL) device that includes providing a substrate; and forming a plurality of pixels over the substrate, each pixel being in a respective pixel area, each pixel area including at least a first area and a second area. Forming each pixel includes forming a semiconductor layer over the first area and the second area, forming a gate oxide layer over the first area and the second area, forming a first metal layer over the first area and the second area, forming an interlayer dielectric (ILD) layer over the first metal layer over the first area and the second area, forming a layer of indium tin oxide (ITO) over the ILD layer over the first area, forming a layer of passivation silicon nitride over the layer of ITO over the first area and over the ILD layer over the second area, forming a second metal layer over the passivation silicon nitride over the first area and over the second area, wherein the second metal layer over the second area provides contact to the first metal layer over the second area through a via hole in the layer of passivation silicon and the gate oxide layer, forming an organic layer over the first area, and forming a third metal layer over the organic layer over the first area, wherein the semiconductor layer over the first area, the gate oxide layer over the first area, and the first metal layer over the first area collectively form a first capacitor, the first metal layer over the first area, the ILD layer over the first area, and the layer of ITO over the first area collectively form a second capacitor, the layer of ITO over the first area, the layer of passivation silicon nitride over the first area, and the second metal layer over the first area collectively form a third capacitor, the second metal layer over the first area, the organic layer over the first area, and the third metal layer over the first area collectively form a fourth capacitor, and the semiconductor layer over the second area, the gate oxide layer over the second area, and the first metal layer over the second area collectively form a transistor.
Additional features and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The features and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
An electroluminescence (EL) device may include an array of pixels formed on a substrate such as glass and
The gate of transistor 102 is coupled to the source of transistor 106. The source of transistor 102 is coupled to a power supply voltage VDD. The drain of transistor 102 is coupled to drive OLED 110. The gates of both transistors 104 and 106 are coupled to a scan line, the drain of transistor 106 is coupled to the source of transistor 104, and the drain of transistor 104 is coupled to a data line to receive data. Capacitor 108 is coupled between the gate and source of transistor 102. OLED 110 has an anode coupled to the drain of transistor 102 and a cathode coupled to a power supply voltage VSS. In one aspect, VSS is ground. In operation, capacitor 108 holds a charge when transistors 104 and 106 are turned off, to maintain a voltage between the gate and source of transistor 102 for driving OLED 110.
Pixel 100 further includes a capacitor 112 coupled between the gate of transistor 102 and the cathode of OLED 110. Thus, both capacitors 108 and 112 store charge when transistors 104 and 106 are turned off, to maintain the gate voltage of transistor 102. In this sense, capacitors 108 and 112 are coupled to each other in parallel and may be collectively viewed as a storage capacitor of pixel 100 whose capacitance is equal to the sum of the capacitances of both capacitors 108 and 112.
In one aspect, capacitor 112 is physically formed over the same area of a substrate where capacitor 108 is formed. Therefore, the storage capacitance of pixel 100 is increased without a chip area thereof being increased. In another aspect, capacitor 112 is formed at the same time OLED 110 and other parts of pixel 100 are formed, without requiring additional masks.
Referring to
Referring to
Over area A, first metal pattern 206A, ILD 208, and second metal pattern 210A collectively form capacitor 108; and second metal pattern 210A, passivation SiN 212, organic 218, and third metal 220 collectively form capacitor 110. Over area B, polysilicon pattern 202B provides the source and drain of transistor 102 and first metal pattern 206B serves as the gate of transistor 102. Over area C, ITO pattern 214C, capping SiN 216, organic 218, and third metal 220 collectively form part of OLED 110. Also, first metal pattern 206A is coupled to power supply voltage VDD, second metal pattern 210A is coupled to the gate of transistor 102, i.e., first metal pattern 206B, and third metal 220 is coupled to VSS.
As shown in
In
It is to be understood that the configuration of pixel 100 as shown in
Further, in
For example, consistent with a second embodiment of the present invention, organic 218 may be removed from area A, as shown in
As shown in
Further,
In
Also consistent with embodiments of the present invention, more than two capacitors may be formed over the same area (area A) of substrate 200 and connected in parallel with one another. An example of four capacitors is shown in
One skilled in the art should appreciate that the formation of capacitors 108, 112, 114, and 116 does not require more masks in addition to those already existing for the formation of pixel 100. For example, doped polysilicon pattern 202A may be formed at the same time doped polysilicon pattern 202B is formed, first metal pattern 206A may be formed at the same time first metal pattern 206B is formed, and ITO pattern 214A may be formed at the same time ITO pattern 214C is formed. Additionally, since all of capacitors 108,112, 114, and 116 are formed over area A of substrate 200, the area of the storage capacitor of pixel 100 is not increased and, therefore, an aperture ratio is not decreased, while the storage capacitance is significantly increased.
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims
1. An electroluminescence (EL) device, comprising:
- a substrate; and
- a plurality of pixels formed on the substrate, each pixel being in a respective pixel area, each pixel area including at least a first area and a second area, each pixel including at least a first capacitor and a second capacitor in the first area, the first capacitor including a first conductive layer, a first dielectric layer over the first conductive layer, and a second conductive layer over the first dielectric layer, and the second capacitor including the second conductive layer, a second dielectric layer over the second conductive layer, and a third conductive layer over the second dielectric layer; a transistor in the second area, the transistor including a first semiconductor layer formed on the substrate, a first gate oxide layer over the first semiconductor layer, a fourth conductive layer over the first gate oxide layer, and a seventh conductive layer contacting the first semiconductor layer, wherein the seventh conductive layer is formed of the same conductive film as the second conductive layer; and a light emitting device in the third area, the light emitting device including a fifth conductive layer, a first organic layer over the fifth conductive layer, and a sixth conductive layer over the first organic layer.
2. The device of claim 1, wherein the first conductive layer is formed of the same conductive film as the fourth conductive layer.
3. The device of claim 1, wherein the third conductive layer is formed of the same conductive film as the sixth conductive layer.
4. The device of claim 1, wherein the fifth conductive layer is an ITO layer and the ITO layer contacts the seventh conductive layer.
5. The device of claim 1, wherein the first organic layer extends to the first area and is between the second dielectric layer and the third conductive layer in the.
6. The device of claim 1, wherein the first dielectric layer comprises an interlayer dielectric.
7. The device of claim 1, wherein the second dielectric layer comprises a layer of passivation silicon nitride.
Type: Application
Filed: Aug 13, 2009
Publication Date: Dec 31, 2009
Applicant: AU OPTRONICS CORP. (Hsinchu)
Inventor: Wein-Town Sun (Hsinchu)
Application Number: 12/540,517
International Classification: H01L 29/04 (20060101);