Characterized By Their Crystalline Structure (e.g., Polycrystalline, Cubic) Particular Orientation Of Crystalline Planes (epo) Patents (Class 257/E29.003)
  • Patent number: 9040400
    Abstract: In connection with various example embodiments, an organic electronic device is provided with an organic material that is susceptible to decreased mobility due to the trapping of electron charge carriers in response to exposure to air. The organic material is doped with an n-type dopant that, when combined with the organic material, effects air stability for the doped organic material (e.g., exhibits a mobility that facilitates stable operation in air, such as may be similar to operation in inert environments). Other embodiments are directed to organic electronic devices n-doped and exhibiting such air stability.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: May 26, 2015
    Inventors: Peng Wei, Zhenan Bao, Joon Hak Oh
  • Patent number: 9040989
    Abstract: One embodiment of the present invention is to achieve high mobility in a device using an oxide semiconductor and provide a highly reliable display device. An oxide semiconductor layer including a crystal region in which c-axis is aligned in a direction substantially perpendicular to a surface is formed and an oxide insulating layer is formed over and in contact with the oxide semiconductor layer. Oxygen is supplied to the oxide semiconductor layer by third heat treatment. A nitride insulating layer containing hydrogen is formed over the oxide insulating layer and fourth heat treatment is performed, so that hydrogen is supplied at least to an interface between the oxide semiconductor layer and the oxide insulating layer.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: May 26, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9040331
    Abstract: In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Patent number: 9029985
    Abstract: Films having a comb-like structure of nanocolumns of Sm2O3 embedded in a SrTiO3 formed spontaneously on a substrate surface by pulsed laser deposition. In an embodiment, the nanocolumns had a width of about 20 nm with spaces between nanocolumns of about 10 nm. The films exhibited memristive behavior, and were extremely uniform and tunable. Oxygen deficiencies were located at vertical interfaces between the nanocolumns and the matrix. The substrates may be single-layered or multilayered.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: May 12, 2015
    Assignee: Los Alamos National Security, LLC
    Inventors: Judith L. Driscoll, ShinBuhm Lee, Quanxi Jia
  • Patent number: 8987696
    Abstract: According to one embodiment, a resistance change memory includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction, a cell unit which is provided at the intersection of the first interconnect line and the second interconnect line and which includes a memory element and a non-ohmic element that are connected in series. The non-ohmic element has a first semiconductor layer which includes at least one diffusion buffering region and a conductive layer adjacent to the first semiconductor layer. The diffusion buffering region is different in crystal structure from a semiconductor region except for the diffusion buffering region in the first semiconductor layer.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Sonehara, Nobuaki Yasutake
  • Patent number: 8980650
    Abstract: Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: March 17, 2015
    Assignee: Intel Corporation
    Inventors: Kaan Oguz, Mark L. Doczy, Brian Doyle, Uday Shah, David L. Kencke, Roksana Golizadeh Mojarad, Robert S. Chau
  • Patent number: 8957426
    Abstract: Embodiments of the invention provide a crystalline aluminum carbide layer, a laminate substrate having the crystalline aluminum carbide layer formed thereon, and a method of fabricating the same. The laminate substrate has a GaN layer including a GaN crystal and an AlC layer including an AlC crystal. Further, the method of fabricating the laminate substrate, which has the AlN layer including the AlN crystal and the AlC layer including the AlC crystal, includes supplying a carbon containing gas and an aluminum containing gas to grow the AlC layer.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: February 17, 2015
    Assignee: Seoul Viosys Co., Ltd.
    Inventor: Shiro Sakai
  • Patent number: 8946011
    Abstract: A manufacturing method of a semiconductor device having a stacked structure in which a lower layer is exposed is provided without increasing the number of masks. A source electrode layer and a drain electrode layer are formed by forming a conductive film to have a two-layer structure, forming an etching mask thereover, etching the conductive film using the etching mask, and performing side-etching on an upper layer of the conductive film in a state where the etching mask is left so that part of a lower layer is exposed. The thus formed source and drain electrode layers and a pixel electrode layer are connected in a portion of the exposed lower layer. In the conductive film, the lower layer and the upper layer may be a Ti layer and an Al layer, respectively. The plurality of openings may be provided in the etching mask.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: February 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Takafumi Mizoguchi
  • Patent number: 8933543
    Abstract: A nitride-based semiconductor device of the present invention includes: a nitride-based semiconductor multilayer structure 20 which includes a p-type semiconductor region with a surface 12 being inclined from the m-plane by an angle of not less than 1° and not more than 5°; and an electrode 30 provided on the p-type semiconductor region. The p-type semiconductor region is formed by an AlxInyGazN (where x+y+z=1, x?0, y?0, and z?0) layer 26. The electrode 30 includes a Mg layer 32 and an Ag layer 34 provided on the Mg layer 32. The Mg layer 32 is in contact with the surface 12 of the p-type semiconductor region of the semiconductor multilayer structure 20.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: January 13, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Toshiya Yokogawa, Mitsuaki Oya, Atsushi Yamada, Akihiro Isozaki
  • Patent number: 8921858
    Abstract: In a light-emitting device having an inverted staggered thin film transistor, the inverted staggered thin film transistor is formed as follows: a gate insulating film is formed over a gate electrode; a microcrystalline semiconductor film which functions as a channel formation region is formed over the gate insulating film; a buffer layer is formed over the microcrystalline semiconductor film; a pair of source and drain regions are formed over the buffer layer; and a pair of source and drain electrodes are formed in contact with the source and drain regions so as to expose a part of the source and drain regions.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: December 30, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yukie Suzuki, Hideaki Kuwabara, Hidekazu Miyairi
  • Patent number: 8921850
    Abstract: A thin film transistor (TFT), a method for fabricating a TFT, an array substrate for a display device having a TFT, and a method for fabricating the same are provided. An oxide thin film transistor (TFT) includes: a gate electrode formed on a substrate; a gate insulating layer formed on the gate electrode; an active layer formed on the gate insulating layer above the gate electrode; an etch stop layer pattern formed on the active layer; a source alignment element and a drain alignment element formed on the etch stop layer pattern and spaced apart from one another; and a source electrode in contact with the source alignment element and the active layer and a drain electrode in contact with the drain alignment element and the active layer.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: December 30, 2014
    Assignee: LG Display Co., Ltd.
    Inventor: SangHee Yu
  • Patent number: 8895335
    Abstract: A method for impurity-induced disordering in III-nitride materials comprises growing a III-nitride heterostructure at a growth temperature and doping the heterostructure layers with a dopant during or after the growth of the heterostructure and post-growth annealing of the heterostructure. The post-growth annealing temperature can be sufficiently high to induce disorder of the heterostructure layer interfaces.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: November 25, 2014
    Assignee: Sandia Corporation
    Inventors: Jonathan J. Wierer, Jr., Andrew A. Allerman
  • Patent number: 8889569
    Abstract: The disclosed systems and method for non-periodic pulse sequential lateral solidification relate to processing a thin film. The method for processing a thin film, while advancing a thin film in a selected direction, includes irradiating a first region of the thin film with a first laser pulse and a second laser pulse and irradiating a second region of the thin film with a third laser pulse and a fourth laser pulse, wherein the time interval between the first laser pulse and the second laser pulse is less than half the time interval between the first laser pulse and the third laser pulse. In some embodiments, each pulse provides a shaped beam and has a fluence that is sufficient to melt the thin film throughout its thickness to form molten zones that laterally crystallize upon cooling. In some embodiments, the first and second regions are adjacent to each other. In some embodiments, the first and second regions are spaced a distance apart.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: November 18, 2014
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: James S. Im, Ui-Jin Chung, Alexander B. Limanov, Paul C. Van Der Wilt
  • Patent number: 8884297
    Abstract: A manufacturing method of a microcrystalline silicon film includes the steps of forming a first microcrystalline silicon film over an insulating film by a plasma CVD method under a first condition; and forming a second microcrystalline silicon film over the first microcrystalline silicon film under a second condition. As a source gas supplied to a treatment chamber, a deposition gas containing silicon and a gas containing hydrogen are used. In the first condition, a flow rate of hydrogen is set at a flow rate 50 to 1000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 67 to 1333 Pa inclusive. In the second condition, a flow rate of hydrogen is set at a flow rate 100 to 2000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 1333 to 13332 Pa inclusive.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: November 11, 2014
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Sachiaki Tezuka, Yasuhiro Jinbo, Toshinari Sasaki, Hidekazu Miyairi, Yosuke Kanzaki, Masao Moriguchi
  • Patent number: 8872309
    Abstract: Group-III nitride crystal composites made up of especially processed crystal slices, cut from III-nitride bulk crystal, whose major surfaces are of {1-10±2}, {11-2±2}, {20-2±1} or {22-4±1} orientation, disposed adjoining each other sideways with the major-surface side of each slice facing up, and III-nitride crystal epitaxially present on the major surfaces of the adjoining slices, with the III-nitride crystal containing, as principal impurities, either silicon atoms or oxygen atoms.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: October 28, 2014
    Assignee: Sumitomo Electronic Industries, Ltd.
    Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
  • Patent number: 8872149
    Abstract: A memory cell and method includes a first electrode formed in an opening in a first dielectric layer, the first dielectric layer being formed on a substrate including a metal layer, the opening being configured to allow physical contact between the first electrode and the metal layer, the first electrode having a first width W1 and extending a distance beyond a region defined by the opening, a resistive layer formed on the first electrode and having substantially the first width W1, a capping layer, having a second width W2 less than the first width W1, formed on the resistive layer, a second electrode formed on the capping layer and having substantially the second width W2, a first composite spacer region having at least two different dielectric layers formed on the resistive layer between the first width W1 and the second width W2, and a via coupled to the second electrode.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Pei Hsieh, Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 8860004
    Abstract: A device that incorporates teachings of the present disclosure may include, for example, a memory array having a first array of nanotubes, a second array of nanotubes, and a state changing material located between the first and second array of nanotubes. Other embodiments are disclosed.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: October 14, 2014
    Assignee: The Board of Trustees of the University of Illinois
    Inventor: Eric Pop
  • Patent number: 8847230
    Abstract: A thin film transistor is provided that includes a gate electrode, a source electrode, and a drain electrode, an oxide semiconductor active layer formed over the gate electrode, a fixed charge storage layer formed over a portion of the oxide semiconductor active layer, and a fixed charge control electrode formed over the fixed charged storage layer.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: September 30, 2014
    Assignee: Sony Corporation
    Inventors: Yasuhiro Terai, Eri Fukumoto, Toshiaki Arai
  • Patent number: 8835905
    Abstract: Described herein is device configured to be a solar-blind UV detector comprising a substrate; a plurality of pixels; a plurality of nanowires in each of the plurality of pixel, wherein the plurality of nanowires extend essentially perpendicularly from the substrate.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: September 16, 2014
    Assignee: Zena Technologies, Inc.
    Inventors: Munib Wober, Young-June Yu
  • Patent number: 8835291
    Abstract: Embodiments of the invention provide a semiconductor device and a method of manufacture. MOS devices along with their polycrystalline or amorphous gate electrodes are fabricated such that the intrinsic stress within the gate electrode creates a stress in the channel region between the MOS source/drain regions. Embodiments include forming an NMOS device and a PMOS device after having converted a portion of the intermediate NMOS gate electrode layer to an amorphous layer and then recrystallizing it before patterning to form the electrode. The average grain size in the NMOS recrystallized gate electrode is smaller than that in the PMOS recrystallized gate electrode. In another embodiment, the NMOS device comprises an amorphous gate electrode.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: September 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chao Huang, Fu-Liang Yang
  • Patent number: 8835893
    Abstract: A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom electrode. The shapes of the variable resistance region and the top electrode are configured to evenly distribute a current with a generally hemispherical current density distribution around the first electrode.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: September 16, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Mike Violette
  • Patent number: 8829519
    Abstract: A PIN diode includes an anode electrode, a P layer, an I layer, an N layer and a cathode electrode. A polysilicon film is formed in a region near the pn junction or n+n junction where the density of carriers implanted in a forward bias state is relatively high, as a predetermined film having a crystal defect serving as a recombination center. The lifetime can thus be controlled precisely.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: September 9, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hidenori Fujii
  • Patent number: 8823082
    Abstract: The present invention is a semiconductor device including a first electrode over a substrate; a pair of oxide semiconductor films in contact with the first electrode; a second electrode in contact with the pair of oxide semiconductor films; a gate insulating film covering at least the first electrode and the pair of oxide semiconductor films; and a third electrode that is in contact with the gate insulating film and is formed at least between the pair of oxide semiconductor films. When the donor density of the oxide semiconductor films is 1.0×1013/cm3 or less, the thickness of the oxide semiconductor films is made larger than the in-plane length of each side of the oxide semiconductor films which is in contact with the first electrode.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: September 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Makoto Yanagisawa
  • Patent number: 8822996
    Abstract: A semiconductor device including a memory cell is provided. The memory cell comprises a transistor, a memory element and a capacitor. One of first and second electrodes of the memory element and one of first and second electrodes of the capacitor are formed by a same metal film. The metal film functioning as the one of first and second electrodes of the memory element and the one of first and second electrodes of the capacitor is overlapped with a film functioning as the other of first and second electrodes of the capacitor.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: September 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takayuki Abe, Yasuyuki Takahashi
  • Patent number: 8822967
    Abstract: Phase change devices, particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. Structure allows application in which an electrical connection can be created between two active terminals, with control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals, allowing use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. Programming control can be placed outside of main signal path through the phase change device, reducing impact of associated capacitance and resistance of the device.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: September 2, 2014
    Assignee: Agate Logic, Inc.
    Inventors: Louis Charles Kordus, II, Antonietta Oliva, Narbeh Derhacobian, Vei-Han Chan
  • Patent number: 8809115
    Abstract: To provide a method for manufacturing a thin film transistor in which contact resistance between an oxide semiconductor layer and source and drain electrode layers is small, the surfaces of the source and drain electrode layers are subjected to sputtering treatment with plasma and an oxide semiconductor layer containing In, Ga, and Zn is formed successively over the source and drain electrode layers without exposure of the source and drain electrode layers to air.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: August 19, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Masashi Tsubuku
  • Patent number: 8809852
    Abstract: One of objects is to provide a semiconductor film having stable characteristics. Further, one of objects is to provide a semiconductor element having stable characteristics. Further, one of objects is to provide a semiconductor device having stable characteristics. Specifically, a structure which includes a seed crystal layer (seed layer) including crystals each having a first crystal structure, one of surfaces of which is in contact with an insulating surface, and an oxide semiconductor film including crystals growing anisotropically, which is on the other surface of the seed crystal layer (seed layer) may be provided. With such a heterostructure, electric characteristics of the semiconductor film can be stabilized.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: August 19, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Takahashi, Tetsunori Maruyama
  • Patent number: 8810009
    Abstract: A composition comprises a semiconductor substrate having a crystallographic plane oriented parallel to a surface of the substrate and at least one planar semiconductor nanowire epitaxially disposed on the substrate, where the nanowire is aligned along a crystallographic direction of the substrate parallel to the crystallographic plane. To fabricate a planar semiconductor nanowire, at least one nanoparticle is provided on a semiconductor substrate having a crystallographic plane oriented parallel to a surface of the substrate. The semiconductor substrate is heated within a first temperature window in a processing unit. Semiconductor precursors are added to the processing unit, and a planar semiconductor nanowire is grown from the nanoparticle on the substrate within a second temperature window. The planar semiconductor nanowire grows in a crystallographic direction of the substrate parallel to the crystallographic plane.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: August 19, 2014
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Xiuling Li, Seth A. Fortuna
  • Patent number: 8809133
    Abstract: There is provided a technique to form a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film. A catalytic element for facilitating crystallization of an amorphous semiconductor thin film is added to the amorphous semiconductor thin film, and a heat treatment is carried out to obtain a crystalline semiconductor thin film. After the crystalline semiconductor thin film is irradiated with ultraviolet light or infrared light, a heat treatment at a temperature of 900 to 1200° C. is carried out in a reducing atmosphere. The surface of the crystalline semiconductor thin film is extremely flattened through this step, defects in crystal grains and crystal grain boundaries disappear, and the single crystal semiconductor thin film or substantially single crystal semiconductor thin film is obtained.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: August 19, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Tamae Takano
  • Patent number: 8802580
    Abstract: Crystallization of thin films using pulsed irradiation The method includes continuously irradiating a film having an x-axis and a y-axis, in a first scan in the x-direction of the film with a plurality of line beam laser pulses to form a first set of irradiated regions, translating the film a distance in the y-direction of the film, wherein the distance is less than the length of the line beam, and continuously irradiating the film in a second scan in the negative x-direction of the film with a sequence of line beam laser pulses to form a second set of irradiated regions, wherein each of the second set of irradiated regions overlaps with a portion of the first set of irradiated regions, and wherein each of the first and the second set of irradiated regions upon cooling forms one or more crystallized regions.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: August 12, 2014
    Assignee: The Trustees of Columbia University in the City of New York
    Inventor: James S. Im
  • Patent number: 8803155
    Abstract: According to an aspect of the present invention, there is provided a thin-film transistor (TFT) sensor, including a bottom gate electrode on a substrate, an insulation layer on the bottom gate electrode, an active layer in a donut shape on the insulation layer, the active layer including a channel through which a current generated by a charged body flows, an etch stop layer on the active layer, the etch stop layer including a first contact hole and a second contact hole, and a source electrode and a drain electrode burying the first and second contact holes, the source and drain electrodes being disposed on the etch stop layer so as to face each other.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: August 12, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Mu-Gyeom Kim, Chang-Mo Park
  • Patent number: 8797303
    Abstract: This disclosure provides systems, methods and apparatus for fabricating thin film transistor devices. In one aspect, a substrate having a source region, a drain region, and a channel region between the source region and the drain region is provided. The substrate also includes an oxide semiconductor layer, a first dielectric layer overlying the channel region, and a first metal layer on the dielectric layer. A second metal layer is formed on the oxide semiconductor layer overlying the source region and the drain region. The oxide semiconductor layer and the second metal layer are treated to form a heavily doped n-type oxide semiconductor in the oxide semiconductor layer overlying the source region and the drain region. An oxide in the second metal layer also can be formed.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: August 5, 2014
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventors: Cheonhong Kim, John Hyunchul Hong, Yaoling Pan
  • Patent number: 8779428
    Abstract: A transistor includes a first active layer having a first channel region and a second active layer having a second channel region. A first gate of the transistor is configured to control electrical characteristics of at least the first active layer and a second gate is configured to control electrical characteristics of at least the second active layer. A source electrode contacts the first and second active layers. A drain electrode also contacts the first and second active layers.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: July 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eok-su Kim, Sang-yoon Lee, Myung-kwan Ryu
  • Patent number: 8772775
    Abstract: A display device includes a substrate; a gate wire including a gate electrode and a first capacitor electrode formed on the substrate; a gate insulating layer formed on the gate wire; a semiconductor layer pattern formed on the gate insulating layer, and including an active region overlapping at least a part of the gate electrode and a capacitor region overlapping at least a part of the first capacitor electrode; an etching preventing layer formed on a part of the active region of the semiconductor layer pattern; and a data wire including a source electrode and a drain electrode formed over the active region of the semiconductor layer from over the etching preventing layer, and separated with the etching preventing layer therebetween, and a second capacitor electrode formed on the capacitor region of the semiconductor layer.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: July 8, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Joung-Keun Park, Jae-Hyuk Jang
  • Patent number: 8759205
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device, wherein an amorphous semiconductor film comprising a microcrystal is annealed using a microwave, to crystallize the amorphous semiconductor film comprising the microcrystal using the microcrystal as a nucleus.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomonori Aoyama, Yusuke Oshiki, Kiyotaka Miyano
  • Patent number: 8753962
    Abstract: When a mixed gas of trichlorosilane and dichlorosilane is used as source gas, a silicon layer is epitaxially grown on a surface of a silicon wafer within a temperature range of 1000 to 1100° C., preferably, 1040 to 1080° C. When dichlorosilane is used as source gas, a silicon layer is epitaxially grown on a surface of a silicon wafer within a temperature range of 900 to 1150° C., preferably, 1000 to 1150° C. According to this, a silicon epitaxial wafer, which has low haze level, excellent flatness (edge roll-off), and reduced orientation dependence of epitaxial growth rate, and is capable of responding to the higher integration of semiconductor devices, can be obtained, and this epitaxial wafer can be used widely in production of semiconductor devices.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: June 17, 2014
    Assignee: Sumco Corporation
    Inventor: Naoyuki Wada
  • Patent number: 8748890
    Abstract: A method of manufacturing a semiconductor wafer of the present invention includes the steps of: obtaining a composite base by forming a base surface flattening layer having a surface RMS roughness of not more than 1.0 nm on a base; obtaining a composite substrate by attaching a semiconductor crystal layer to a side of the composite base where the base surface flattening layer is located; growing at least one semiconductor layer on the semiconductor crystal layer of the composite substrate; and obtaining the semiconductor wafer including the semiconductor crystal layer and the semiconductor layer by removing the base surface flattening layer by wet etching and thereby separating the semiconductor crystal layer from the base.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 10, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yuki Seki, Issei Satoh, Koji Uematsu, Yoshiyuki Yamamoto
  • Patent number: 8729607
    Abstract: Structures and methods are presented relating to formation of finFET semiconducting devices. A finFET device is presented comprising fin(s) formed on a substrate, wherein the fin(s) has a needle-shaped profile. The needle-shaped profile, in conjunction with at least a buffer layer or a doped layer, epitaxially formed on the fin(s), facilitates strain to be induced into the fin(s) by the buffer layer or the doped layer. The fin(s) can comprise silicon aligned on a first plane, while at least one of the buffer layer or the doped layer are grown on a second plane, the alignment of the first and second planes are disparate and are selected such that formation of the buffer layer or the doped layer generates a stress in the fin(s). The generated stress results in a strain being induced into the fin(s) channel region, which can improve electron and/or hole mobility in the channel.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Itokawa, Akira Hokazono
  • Publication number: 20140117356
    Abstract: A semiconductor device includes a substrate, a semiconductor layer, and a material layer. The semiconductor layer is formed over the substrate. The material layer is formed over the semiconductor layer. The semiconductor layer and the material layer have a tapered profile in a vertical direction extending from the substrate.
    Type: Application
    Filed: October 30, 2012
    Publication date: May 1, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Jeng Hwa Liao, Jung Yu Shieh, Ling Wuu Yang
  • Patent number: 8703554
    Abstract: An array substrate for an LCD device includes a gate line crossing a data line to define a pixel region. A thin film transistor (TFT) includes a gate electrode connected to the gate line, insulating and active layers on the gate electrode, a source electrode connected to the data line, and a drain electrode spaced apart from the source electrode. An auxiliary common electrode includes a horizontal portion disposed in the pixel region. A metal layer overlaps the insulating layer and contacts the horizontal portion of the auxiliary common electrode through a contact hole defined through the insulating layer. A passivation layer is disposed on the TFT and the metal layer. A pixel electrode has a horizontal portion overlapping the metal layer with the passivation layer therebetween to form a storage capacitor, the pixel electrode connected to the drain electrode through a second contact hole defined through the passivation layer.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: April 22, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Il-Man Choi, Ho-June Kim
  • Patent number: 8704340
    Abstract: A compound semiconductor substrate includes a first substrate and a second substrate made of single crystal gallium nitride. In each of the first substrate and the second substrate, one surface is a (0001) Ga-face and an opposite surface is a (000-1) N-face. The first substrate and the second substrate are bonded to each other in a state where the (000-1) N-face of the first substrate and the (000-1) N-face of the second substrate face each other, and the (0001) Ga-face of the first substrate and the (0001) Ga-face of the second substrate are exposed.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: April 22, 2014
    Assignee: DENSO CORPORATION
    Inventors: Hiroaki Fujibayashi, Masami Naito, Nobuyuki Ooya
  • Patent number: 8674359
    Abstract: A thin film transistor (TFT), an array substrate including the TFT, and methods of manufacturing the TFT and the array substrate. The TFT includes an active layer, and a metal member that corresponds to a portion of each of the source region and the drain region of the active layer, and is arranged on the active layer, a portion of the metal member contacts the source and drain regions of the active layer and the source and drain electrodes, and portions of the active layer that corresponds to portions below the metal member of the active layer are not doped.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: March 18, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dae-Hyun Noh, Sung-Ho Kim
  • Publication number: 20140070215
    Abstract: A method of forming a strained semiconductor material that in one embodiment includes forming a cleave layer in a host semiconductor substrate, and contacting a strain inducing material layer on a surface of a transfer portion of the host semiconductor substrate. A handle substrate is then contacted to an exposed surface of the stress inducing material layer. The transfer portion of the host semiconductor substrate may then be separated from the host semiconductor substrate along the cleave layer. A dielectric layer is formed directly on the transfer portion of the host semiconductor substrate. The handle substrate and the stress inducing material are then removed, wherein the transferred portion of the host semiconductor substrate provides a strained semiconductor layer that is in direct contact with a dielectric layer.
    Type: Application
    Filed: September 13, 2012
    Publication date: March 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Publication number: 20140061655
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a front surface and a backside surface; integrated circuit features formed on the front surface of the semiconductor substrate; and a polycrystalline silicon layer disposed on the backside surface of the semiconductor substrate.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hao Hsu, Chia-Chen Chen, Tzung-Chi Fu, Tzu-Wei Kao, Yu Chao Lin
  • Publication number: 20140054653
    Abstract: An integrated circuit device and a process for making the integrated circuit device. The integrated circuit device including a substrate having a trench formed therein, a first layer of isolation material occupying the trench, a second layer of isolation material formed over the first layer of isolation material, an epitaxially-grown silicon layer on the substrate and horizontally adjacent the second layer of isolation material, and a gate structure formed on the epitaxially-grown silicon, the gate structure defining a channel.
    Type: Application
    Filed: August 24, 2012
    Publication date: February 27, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min Hao Hong, You-Hua Chou, Chih-Tsung Lee, Shiu-Ko JangJian, Miao-Cheng Liao, Hsiang-Hsiang Ko, Chen-Ming Huang
  • Publication number: 20140048804
    Abstract: A method of forming a semiconductor device includes forming a mandrel on top of a substrate; forming a first spacer adjacent to the mandrel on top of the substrate; forming a cut mask over the first spacer and the mandrel, such that the first spacer is partially exposed by the cut mask; partially removing the partially exposed first spacer; and etching the substrate to form a fin structure corresponding to the partially removed first spacer in the substrate.
    Type: Application
    Filed: August 20, 2012
    Publication date: February 20, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Chun-Chen Yeh
  • Patent number: 8648393
    Abstract: An accumulation mode transistor has an impurity concentration of a semiconductor layer in a channel region at a value higher than 2×1017 cm?3 to achieve a large gate voltage swing.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: February 11, 2014
    Assignees: National University Corporation Tohoku University, Foundation for Advancement of International Science
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Rihito Kuroda
  • Publication number: 20140034953
    Abstract: A display device includes a first substrate and a second substrate facing each other, a thin film transistor on the first substrate, a color filter and a black matrix on the first substrate, a column spacer on the first substrate and electrically connected to the thin film transistor, a pixel electrode on one surface of the second substrate, a common electrode on the pixel electrode on the one surface of the second substrate, and a transparent electrode on the other surface of the second substrate. The column spacer is electrically connected to the pixel electrode.
    Type: Application
    Filed: November 5, 2012
    Publication date: February 6, 2014
    Inventor: Jae Kyung GO
  • Patent number: 8643060
    Abstract: Disclosed is a technology of manufacturing, at low cost, an epitaxial crystal substrate provided with a high-quality and uniform epitaxial layer, said technology being useful in the case of growing the epitaxial layer composed of a semiconductor having a lattice constant different from that of the substrate. The substrate, which is composed of a first compound semiconductor, and which has a step-terrace structure on the surface, is used, and on the surface of the substrate, a composition modulation layer composed of a second compound semiconductor is grown by step-flow, while changing the composition in the same terrace. Then, the epitaxial crystal substrate is manufactured by growing, on the composition modulation layer, the epitaxial layer composed of the third compound semiconductor having the lattice constant different from that of the first compound semiconductor.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: February 4, 2014
    Assignee: JX Nippon Mining & Metals Corporation
    Inventors: Hajime Momoi, Koji Kakuta
  • Publication number: 20140027773
    Abstract: A semiconductor device includes a transistor cell array in the semiconductor body of a first conductivity type. The semiconductor device further includes a first trench in the transistor cell array between transistor cells. The first trench extends into the semiconductor body from a first side and includes a pn junction diode electrically coupled to the semiconductor body at a sidewall.
    Type: Application
    Filed: July 24, 2012
    Publication date: January 30, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Thorsten Meyer, Andreas Meiser