ETHERNET SYSTEM
Four (4) unshielded twisted pairs of wires connect a hub and a computer in an Ethernet system: one (1) pair for transmission only, another for reception only and the other two (2) for transmission and reception. The signals in the wires are in packets each having timing signals defining a preamble and thereafter having digital signals representing information as by individual ones of three (3) amplitude levels. The signals received at the computer are provided with an automatic gain control (AGC) and then with digital conversions at a particular rate. A control loop operative upon the digital conversions regulates the AGC gain at a particular value. An equalizer operative only during the occurrence of the digital signals in each packet selects an individual one of the three (3) amplitude levels closest to the amplitude of each digital conversion at the time assumed to constitute the conversion peak. The amplitudes of the timing signals in each preamble at the times assumed to constitute the peaks and zero crossings of such signals are multiplied. The rate of such digital conversions is adjusted in accordance with the polarity and magnitude of the multiplication product. The relative amplitudes of the successive equalizer values following each preamble are evaluated at the times assumed to be the peaks of the digital conversions. The rate of the digital conversions is adjusted in accordance with such evaluations, thereby further regulating the digital conversions at the particular rate. The equalizer thus operates on the information signals in each packet at the signal peaks.
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This invention relates to systems for, and methods of, operating in local area networks to provide for the transmission and reception of signals through unshielded twisted pairs of wires between a computer and a hub. The invention particularly relates to systems for, and methods of, using digital techniques for enhancing the recovery, and the quality of such recovery, of the digital signals passing through the unshielded twisted pairs to the computer so that the information represented by such digital signals can be restored at the computer.
Systems now exist for passing information between different computers in a local area network. The systems include a hub connected to computers located at spaced positions around the hub. The connections between the hub and each computer are generally through unshielded twisted pairs of wires. These wires are generally made from copper so that they have relatively large losses. This has limited the distance through which the signals can pass between the hub and each computer. The unshielded twisted pairs of wires have also limited the rate at which the signals can be transmitted. Until relatively recently, the distance between the hub and each computer has been limited to approximately one hundred (100 m.) and the rate of signal transmission has been limited to approximately 10 megabits per second (10 Mb/sec.).
The systems discussed in the previous paragraph and constituting the prior art have used analog techniques at the computer to recover the information represented by the digital signals. For example, the systems of the prior art have used analog equalizers to compensate for deteriorations in the characteristics of the digital signals as the digital signals pass through the unshielded twisted pairs of wires. These analog techniques have been satisfactory when the signals have passed through the unshielded twisted pairs of wires at a frequency of ten megabits per second (10 Mb/sec.)
The amount of information being transmitted through the unshielded twisted pairs of lines has been increasing at a relatively rapid rate. To provide for this increased transmission of information, the rate of transmission has been increased to one hundred megabits per second (100 Mb/sec.). The increased rate of signal transmission has prevented analog equalizers from operating effectively in restoring at the computer the signals transmitted from the hub.
Digital circuits have been considered for use in systems employing unshielded twisted pairs of wires and transmitting signals at one hundred megabits per second (100 Mb/sec) through distances as great as one hundred meters (100 m.). For example, digital adaptive equalization technology has been considered for such systems. However, such digital systems have been rejected for several reasons. One reason has been that the systems considered have not provided significantly enhanced performance. Furthermore, the complexity of such systems has been quite high, particularly in relation to any enhanced performance obtained from such systems. The cost of such digital systems has also been considered to be excessive.
This invention provides a system for, and method of, receiving at a computer packets of digital signals transmitted from a hub displaced by a distance of as much as one hundred meters (100 m.) from the computer and for recovering the information represented by the digital signals in the packets. The system and method of this invention provide for such recovery whether the digital signals are transmitted through the wires at a, frequency of ten megabits per second (10 Mb/sec.) or one hundred megabits per second (100 Mb/sec).
The system of this invention includes a digital adaptive equalizer for recovering the information represented by the digital signals in the packets. This equalizer is of an advanced design and includes feedback techniques to enhance the resolution provided by the equalizer in determining the amplitude level of each of the digital signals in each packet. The system and method of this invention are particularly adapted to operate with four (4) unshielded twisted pairs of wires, three (3) of the four (4) transmitting information whether the transmission is from the hub to the computer or from the computer to the hub. The system and method of this invention also include circuits and techniques for synchronizing the operation of the equalizer with the digital signals in the packets to enhance the recovery of the amplitudes of the digital signals by the equalizer.
In one embodiment of the invention, four (4) unshielded twisted pairs of wires connect a hub and a computer in an Ethernet system: one (1) pair of transmission only, another for reception only and the other two (2) for transmission and reception. The signals in the wires are in packets each having timing signals defining a preamble and thereafter having digital signals representing information as by individual ones of three (3) amplitude levels.
The signals received at the computer are provided with an automatic gain control (AGC) and then with digital conversion at a particular rate. A control loop operative upon the digital conversions regulates the AGC gain at a particular value. An equalizer operative only during the occurrence of the digital signals in each packet selects an individual one of the three (3) amplitude levels closest to the amplitude of each digital conversion at the time assumed to constitute the conversion peak.
The amplitudes of the timing signals in each preamble at the times assumed to constitute the peaks and zero crossings of such signals are multiplied. The rate of such digital conversions is adjusted in accordance with the polarity and magnitude of the multiplication product. The relative amplitudes of the successive equalizer values following each preamble are evaluated at the times assumed to be the peaks of the digital conversions. The rate of the digital conversions is adjusted in accordance with such evaluations, thereby further regulating the digital conversions at the particular rate. The equalizer thus operates on the information signals in each packet at the signal peaks.
In the drawings:
An Ethernet system incorporating the features of this invention is generally indicated at 10 in
The hub 12 is connected to each of the computers 14, 16, 18 and 20 by unshielded twisted pairs of wires or cables. Generally, the wires or cables are formed from copper. Four (4) unshielded twisted pairs of wires are provided in the system 10 between each computer and the hub 12. For example, four (4) unshielded twisted pairs of wires 22 are provided between the hub 12 and the computer 14. The system shown in
An amplifier 32 at the computer 14 and an amplifier 34 at the hub 12 are connected to transmit digital signals through the unshielded twisted pairs 22 of wires only in the direction from the computer 14 to the hub 12. An amplifier 36 at the hub 12 and an amplifier 38 at the computer 14 are connected to transmit digital signals through the unshielded twisted pair 26 of wires only from the hub 12 to the computer 14.
Each of the unshielded twisted pairs 28 and 30 of wires or cables is connected to pass signals from the hub 12 to the computer 14 and also from the computer to the hub. This results from the connections of amplifiers 40 and 42 in opposite directions in the computer 14 to the unshielded twisted pairs 28 of wires or cables and from the connections of amplifiers 44 and 46 in opposite directions in the hub 12 to such unshielded twisted pairs of wires. Similar connections are made to the unshielded twisted pairs 30 of wires.
The signals to be transmitted are introduced to an encoder 52 which encodes each of the signals to one (1) of three (3) amplitude levels dependent upon the information represented by such signal. The encoding of the signals to the individual ones of the three (3) amplitude levels effectively provides a reduction in the frequency of the signals. The signals then pass to a data splitter 53 which operates as a demultiplexer to pass the signals in successive packets into successive ones of three (3) channels on a cyclic basis. This causes the frequency of the signals in the packets in each of the channels to be reduced to one third (⅓) of the frequency of the packets of signals from the encoder 52.
One of the three (3) channels in
In addition to passing through the unshielded twisted pairs 60 and 62 of wires on cables, the signals received by the computer 14 pass through an unshielded twisted pair 64 (designated as Pair 2), a filter/coupler 66 and a carrier sensor 68 to the media access controller 50 to activate the media access controller when a collision in the computer 14 between transmitted and received signals is about to occur.
The signals from the data recovery stage 68 and the other two (2) data recovery stages are introduced to a data combiner 70 which acts as a multiplexer to recombine the signals in the three (3) received channels. A decoder 72 then recovers the information represented by the individual ones of the three (3) amplitude levels for the successive signals in the packets. The decoded signals then pass to the media access controller 50 also shown in
As previously described, the signals in the unshielded twisted pairs 58, 60, 62 and 64 of wires or cables have a data rate of one hundred megabits per second (100 Mb/sec.). The rate of the transmission of such signals is at twenty five megabauds per second (25 Mbaud/sec.). The signals are in packets each having signals identifying the beginning of such packet and each having, after such identifying signals, a plurality of timing signals at the beginning of such packet.
The timing signals are provided in preambles in the packets. There may illustratively be eighteen (18) timing signals in each packet. Each of the timing signals have two (2) amplitude levels (positive and negative). The timing signals for the different packets are respectively illustrated at 76a, 76b and 76c in
Although the digital signals representing the data in the packets have a frequency of one hundred megabits (100 Mb/sec.) per second, this frequency is reduced by the encoder 52 as a result of the conversion of the signals to three (3) amplitude levels. The frequency of such digital signals is also reduced by the data splitter 53 in
The system shown in
The signals from the receivers and equalizers 84a, 84b and 84c pass to a clock recovery stage 86 which operates upon these signals to recover a clock signal. The stage 86 is included within the features of this invention. This clock signal is used to synchronize the operation of the receivers and equalizers 84a, 84b and 84c and the data combiner and decoder 88. The clock signal from the stage 86 and the signals from the receivers and equalizers 84a, 84b and 84c are introduced to a stage 88 which constitutes a combination of the data combiner (or multiplexer) 70 and the decoder 72 in
The signals from the converter 92 pass to an AGC control loop 94. The signals from the AGC control loop 94 regulate the gain of the signals of the AGC stage 90 at a particular value. In this way, the amplitudes of the signals from the converter 92 are independent of any variation in the gain in the signals. The rate of production of the digital conversions is regulated by a timing recovery stage generally indicated at 96 so that the digital conversions of the signals from the stage 92 are at a particular rate and in a particular phase. The timing recovery stage 96 is shown in additional detail in subsequent Figures.
The output from the converter 92 is introduced to a digital adaptive equalizer generally indicated at 98 in
The adder 102 adds the outputs of the feed forward equalizer 100 and the decision feedback equalizer 104 to provide an output which is introduced to the slicer 106. This addition may be seen from
The output from the adder 102 is introduced to the slicer 106 in
This invention recovers in the computer 14 the pattern of the successive signals transmitted through each of the unshielded pairs 64, 60 and 62 of wires from the hub 12 even after such signals have travelled a distance of approximately one hundred meters (100 m.) from the hub and have suffered the degradation shown in
The signal xp from the converter 90 is shown in
The loop filter 126 also receives clock signals on a line 128 at a baud clock rate of twenty five megahertz (25 MHz). The loop filter 126 additionally receives signals, designated as “boost & boost 2”, on a line 130 from a high gain error generator 132. Signals designated as “high gain error” are introduced on a line 134 from the high gain error generator 132 to the loop filter 126. A phase inverter 136 provides signals (designated as “freeze”) on a line 138 to the loop filter 126. The output from the loop filter 126 passes through a line 140 to a ring oscillator generally indicated at 186 shown in additional detail in
The phase inverter 136 receives the clock signals on the line 122 at the master clock frequency of fifty megahertz (50 MHz) and clock signals at the baud clock frequency of twenty five megahertz (25 MHz). The clock signals on the line 128 also pass to internal blocks. The clock signals on the lines 122 and 128 also pass to a controller 142. The controller 142 also receives on a line 144 signals which indicate the start of each packet. These signals are provided in a special pattern at the beginning of each packet. The controller 142 provides other control signals on a line 146.
The signals xp and xo at the times respectively assumed to be the peaks and zero crossings of the timing signals 76a, 76b and 76c (
When the product of xp and xo for a timing signal is zero, no correction has to be made since the time assumed by the baud clock signal on the line 128 to be the zero crossing for a timing signal is actually the time that the zero crossing has occurred. When the signal xp occurs at a time indicated at 148 in
Sometimes, however, the baud clock signals on the line 128 are considerably out of synchronism with the signals xp and xo respectively assumed to constitute the peaks and zero crossings. This is shown in
When the phase shift of 90° occurs in the time relationship shown in
The phase inverter 136 in
Only one phase shift of 90° is provided during the preamble in each packet. This is indicated by the “freeze” indication on the line 138 in
Furthermore, the phase shifts in the clock signals on the line 128 are made only during a first limited number of timing signals in each preamble. This results from the introduction of a signal (designated as “time out”) on a line 139 from the controller 142 to the phase inverter 136. For example, if there are eighteen (18) timing signals in each preamble, the phase shifts in the clock signals on the line 128 will preferably be made only in the first ten (10) timing signals in such preamble. This prevents large amplitudes of noise in the last eight (8) timing signals of a preamble from producing undesired phase shifts of 90° in the clock baud signals on the line 128. Such large phase shifts in the last timing signals in each preamble tend to create instabilities, particularly when such large phase shifts result from the introduction of noise into the system.
Sometimes the gain of the signals from the converter 90 is relatively low. When the gain of the converter 90 as represented by the xp and xo signals is at least fifty percent (50%) below the dynamic range of the converter 90, a signal is introduced on the line 130 to the loop filter 126. This causes the loop gain to be doubled. The loop gain is doubled again when the gain of the converter 90 as represented by the xp and xo signals is below twenty five percent (25%) of the dynamic range of the converter 90.
The low gain error generator 124 provides error corrections during the occurrence of the digital signals following the timing signals in the preamble of each packet. These digital signals indicate the data or information in each packet. As a result of these error corrections, the phase of the digital conversions by the A-D converter 90 is regulated so that the signal xo occurs at the zero crossings of the digital signals following the preamble in the packet and the signal {circumflex over (x)} from the equalizer 98 represents the peak of such digital signals.
The low-gain error generator 124 provides such phase regulation by operating upon successive ones of the digital signals. This may be seen from
As will be seen,
In
Since only half transitions are involved in
The signals from the high gain error generator 132 and the low gain error generator 124 are introduced to the loop filter 126 shown as a block in
The signals on the line 170 in
The signals from the amplifier 172 in
The multiplexer 182 receives the signals from a voltage controlled oscillator generally indicated at 186 and shown within broken lines in
Each packet has signals in a unique pattern to indicate the beginning of the packet. The controller 142 (
When the signal on the line 146 indicates the occurrence of the timing signals, the signals from the high gain error generator 132 pass through the select stage and the loop filter 126 to the multiplexer 182. These signals activate the multiplexer 182 to pass the signals from one of the amplifiers 188a-188h. By selecting a different one of the amplifiers 188a-188h in each cycle phase is adjusted in accordance with the characteristics of the signals from the high gain error generator 132. The phase-adjusted clock signals are introduced to the A-D converter 90 to obtain the generation of the digital conversions by the converter.
Except for the instances where a phase inversion is provided, the phase adjustment in each cycle is limited to a particular magnitude. For example, when sixteen (16) amplifiers are provided in the ring oscillator 186, each phase adjustment may be limited to that provided by two (2) successive amplifiers in the ring oscillator 186. This enhances the stability in adjusting the phase of the clock signals on the line 128 so that the signal xo occurs at the zero crossing of the clock signals.
When a phase inversion of 90° occurs, an adjustment in the phase of the clock signals on the line 128 in
When the signal on the line 146 in
Although this invention has been disclosed and illustrated with reference to particular embodiments, the principles involved are susceptible for use in numerous other embodiments which will be apparent to persons skilled in the art. The invention is, therefore, to be limited only as indicated by the scope of the appended claims.
Claims
1-103. (canceled)
104. Apparatus adapted to be coupled to at least a twisted first wire pair enabling receipt of at least first, second and third discrete analog signal levels with different amplitudes representing information, a twisted second wire pair enabling receipt of at least fourth, fifth and sixth discrete analog signal levels with different amplitudes representing information and a twisted third wire pair enabling receipt of at least seventh, eighth and ninth discrete analog signal levels with different amplitudes representing information, the analog signal levels being received one discrete signal level at a time, the apparatus comprising:
- an analog to digital converter arranged to convert the first discrete analog signal level to a corresponding digital first information signal, to convert the second discrete analog signal level to a corresponding digital second information signal, to convert the third discrete analog signal level to a corresponding digital third information signal, to convert the fourth analog signal level to a corresponding digital fourth information signal, to convert the fifth discrete analog signal level to a corresponding digital fifth information signal, to convert the sixth discrete analog signal level to a corresponding digital sixth information signal, to convert the seventh discrete analog signal level to a corresponding digital seventh information signal, to convert the eighth discrete analog signal level to a corresponding digital eighth information signal and to convert the ninth discrete analog signal level to a corresponding digital ninth information signal; and
- circuitry arranged to individually identify each of the first, second, third, fourth, fifth, sixth, seventh, eighth and ninth discrete analog signal levels, to shift in time the first information signal relative to the first discrete analog signal level, to shift in time the second information signal relative to the second discrete analog signal level, to shift in time the third information signal relative to the third discrete analog signal level, to shift in time the fourth information signal relative to the fourth discrete analog signal level, to shift in time the fifth information signal relative to the fifth discrete analog signal level, to shift in time the sixth information signal relative to the sixth discrete analog signal level, to shift in time the seventh information signal relative to the seventh discrete analog signal level, to shift in time the eighth information signal relative to the eighth discrete analog signal level and to shift in time the ninth information signal relative to the ninth discrete analog signal level.
105. The apparatus of claim 104, wherein the analog to digital converter is arranged to convert the discrete analog signals levels to corresponding digital information signals at a particular rate and wherein the circuitry comprises a timing recovery circuit arranged to regulate the particular rate at which said analog to digital converter converts the discrete analog signal levels.
106. The apparatus of claim 105, wherein the circuitry comprises a digital adaptive equalizer arranged to identify the discrete analog signal level being received on each of the wire pairs.
107. The apparatus of claim 106, further comprising an automatic gain control circuit coupled to the analog to digital converter.
108. The apparatus of claim 106, further comprising a decoder circuit coupled to the digital adaptive equalizer.
109. The apparatus of claim 108, further comprising a media access controller coupled to said decoder circuit.
110. The apparatus of claim 106, wherein the digital adaptive equalizer includes a feedforward equalizer, a data slicer and a decision feedback equalizer.
111. The apparatus of claim 106, wherein said timing recovery circuit regulates the particular rate in accordance with a product of a plurality of signal samples.
112. The apparatus of claim 104, further comprising a clock arranged to generate clock signals having a phase and wherein the analog to digital converter is arranged to convert the discrete analog signal levels to the corresponding digital information digital signals in response to the clock signals and wherein the circuitry is arranged to shift the phase of the clock signals so that the time at which the analog to digital converter samples the discrete analog signal levels is adjusted.
113. The apparatus of claim 112, wherein the circuitry shifts the phase of the clock signals in accordance with a product of a plurality of signal samples.
114. The apparatus of claim 112, wherein each of the wire pairs enables receipt of timing discrete analog signal levels, wherein the analog to digital converter is arranged to convert the timing discrete analog signal levels to corresponding timing digital signals in response to the clock signals, and wherein the circuitry is arranged to shift the phase of the clock signals in response to the timing digital signals.
115. The apparatus of claim 114, wherein the circuitry is arranged to shift the phase of the clock signals in response to both the timing digital signals and the information digital signals.
116. In apparatus adapted to be coupled to at least a twisted first wire pair enabling receipt of at least first, second and third discrete analog signal levels with different amplitudes representing information, a twisted second wire pair enabling receipt of at least fourth, fifth and sixth discrete analog signal levels with different amplitudes representing information and a twisted third wire pair enabling receipt of at least seventh, eighth and ninth discrete analog signal levels with different amplitudes representing information, the analog signal levels being received one discrete signal level at a time, a method of processing the received discrete analog signal levels comprising:
- converting the first discrete analog signal level to a corresponding digital first information signal;
- converting the second discrete analog signal level to a corresponding digital second information signal;
- converting the third discrete analog signal level to a corresponding digital third information signal;
- converting the fourth discrete analog signal level to a corresponding digital fourth information signal;
- converting the fifth discrete analog signal level to a corresponding digital fifth information signal;
- converting the sixth discrete analog signal level to a corresponding digital sixth information signal;
- converting the seventh discrete analog signal level to a corresponding digital seventh information signal;
- converting the eighth discrete analog signal level to a corresponding digital eighth information signal;
- converting the ninth discrete analog signal level to a corresponding digital ninth information signal;
- individually identifying each of the first, second, third, fourth, fifth, sixth, seventh, eighth and ninth discrete analog signal levels;
- shifting in time the first information signal relative to the first discrete analog signal level;
- shifting in time the second information signal relative to the second discrete analog signal level;
- shifting in time the third information signal relative to the third discrete analog signal level;
- shifting in time the fourth information signal relative to the fourth discrete analog signal level;
- shifting in time the fifth information signal relative to the fifth discrete analog signal level;
- shifting in time the sixth information signal relative to the sixth discrete analog signal level;
- shifting in time the seventh information signal relative to the seventh discrete analog signal level;
- shifting in time the eighth information signal relative to the eighth discrete analog signal level; and
- shifting in time the ninth information signal relative to the ninth discrete analog signal level.
117. The method of claim 116, wherein each of the converting steps comprises converting one of the discrete analog signals levels to a corresponding one of the information signals at a particular rate and further comprising regulating the particular rate.
118. The method of claim 117, wherein said regulating comprises regulating the particular rate in accordance with a product of a plurality of signal samples.
119. The method of claim 116, further comprising controlling the gain of the each of the received discrete analog signal levels.
120. The method of claim 116, further comprising decoding each of the digital information signals.
121. The method of claim 116, further comprising controlling media access.
122. The method of claim 116, further comprising generating clock signals having a phase and wherein each of the converting steps comprises converting one of the discrete analog signal levels to one of the corresponding digital information signals in response to the clock signals and wherein each of the shifting steps comprises shifting the phase of the clock signals so that the time at which the converting occurs is adjusted.
123. The method of claim 122, wherein the shifting comprises shifting the phase of the clock signals in accordance with a product of a plurality of signal samples.
124. The method of claim 122, wherein each of the wire pairs enables receipt of timing discrete analog signal levels, wherein the converting comprises converting the timing discrete analog signal levels to corresponding timing digital signals in response to the clock signals, and wherein the shifting comprises shifting the phase of the clock signals in response to the timing digital signals.
125. The method of claim 124, wherein the shifting comprises shifting the phase of the clock signals in response to both the timing digital signals and the digital information signals.
126. A communication system for decoding signals having three or more analog signal levels to represent information transmitted by a first computer over a plurality of pairs of twisted wires to a second computer, said communication system including a transceiver comprising:
- a plurality of receivers and transmitters operatively coupled to respective ones of said plurality of said pairs of twisted wires, wherein each of said plurality of receivers comprises:
- an analog to digital converter;
- an automatic gain control circuit; and
- a digital adaptive equalizer that includes a feed forward equalizer, a decision feedback equalizer and a data slicer,
- wherein each of said analog to digital converters sampling said analog signal at a sampling rate, each of said automatic gain control circuits receiving said analog signal from one of said pairs of twisted wires and providing gain control at the input to a respective one of said analog to digital converters, and each of said equalizers producing recovered digital data from said sampled analog signal provided at the input of said equalizer, and
- wherein said transceiver includes a plurality of transmitters that simultaneously transmit three or more analog signal levels to said first computer over said plurality of pairs of twisted wires.
127. The system of claim 126, wherein said transceiver combines said recovered data from each of said digital adaptive equalizers into a single recovered digital data stream.
128. The system of claim 127, wherein said single recovered data stream is Ethernet data.
129. The system of claim 126, wherein said communication system is an Ethernet system.
130. The system of claim 126, wherein the digital data is Ethernet data with a data rate of at least 100 Mbps.
131. The system of claim 126, wherein each of said equalizer includes an adder that sums the output of respective ones of said decision feedback equalizers and said feed forward equalizers.
132. The system of claim 131, wherein the digital data is Ethernet data.
133. A computer network device, comprising:
- transmitting circuitry including an encoder and data splitter circuitry, a first transmitter, a second transmitter and a third transmitter, wherein the first transmitter, the second transmitter and the third transmitter are coupled to a network via a respective pair of twisted wires;
- receiving circuitry including clock recover circuitry, data combiner and decoder circuitry, a first receiver and equalizer, a second receiver and equalizer and a third receiver and equalizer, wherein the clock recover circuitry is disposed along a data path between the receivers and equalizers and the data combiner and decoder circuitry, wherein the first receiver and equalizer, the second receiver and equalizer and the third receiver and equalizer is coupled to the network via a respective pair of twisted wires;
- a media access control coupled to a system bus, the encoder and data splitter circuitry of the transmitting circuitry and the data combiner and decoder circuitry of the receiver circuitry; and
- collision detect and link control circuitry coupled to the media access control, the transmitters and the receivers and equalizers,
- wherein the first receiver and equalizer comprises an automatic gain control stage, an analog-to-digital converter and a digital adaptive equalizer, wherein the automatic gain control state is coupled to the analog-to-digital converter, and wherein the analog-to-digital converter is coupled to the digital adaptive equalizer.
134. The computer network device according to claim 133, wherein the digital adaptive equalizer comprises a feed forward equalizer, a three-level data slicer and a decision feedback equalizer.
135. The computer network device according to claim 134, wherein the digital adaptive equalizer comprises an adder that has a first input, a second input and an output, wherein the first input is coupled to the feed forward equalizer, wherein the second input is coupled to the decision feedback equalizer and wherein the output is coupled to the three-level data slicer.
136. The computer network device according to claim 134, wherein first receiver and equalizer comprises timing recovery circuitry, wherein timing recover circuitry comprises a low gain error generator, a high gain error generator, a loop filter, a phase inverter and a controller.
Type: Application
Filed: Dec 14, 2009
Publication Date: Jun 17, 2010
Applicant: Broadcom Corporation (Irvine, CA)
Inventors: Henry Samueli (Corona Del Mar, CA), Mark Berman (Newport Coast, CA), Fang Lu (Rowland Heights, CA)
Application Number: 12/637,629
International Classification: H03M 1/06 (20060101); H03M 1/00 (20060101);